KR102195408B1 - Data interface and data transmit method - Google Patents

Abstract

A data interface and a data transmission method are provided. The data interface generates a first bit set including a first bit included in first image data and a third bit included in second image data, and is included in the first image data and the first bit A formater for generating a second bit set including a second bit that is an upper bit of the second bit and a fourth bit that is an upper bit of the third bit and included in the second image data, and the first bit set A first serializer for serializing, a second serializer for serializing the second bit set, a first output driver for converting the serialized first bit set into a first differential signal, and a second serialized second bit set A second output driver that converts into a differential signal, and a clock generator that generates a plurality of clock signals transmitted to the formatter, the first and second serializers, and the first and second output drivers. do.

Description

Data interface and data transmit method}

The present invention relates to a data interface and a data transmission method.

The image pickup device includes an image sensor. An image sensor is one of semiconductor devices that convert optical information into electrical signals. Such an image sensor may transmit optical information converted into an electrical signal to an image signal processor (ISP). A data interface may be used in the process of transmitting optical information.

The data interface includes a serializer-deserializer (SerDes), which serializes data and transmits it through a transmission channel, and deserializes the received serialized data. In addition, the data interface restores the frequency of the received data using a clock data recovery circuit (CDR) and operates the sampler circuit with a clock of the restored frequency. Accordingly, the receiving side can continue to receive data transmitted by the transmitting side operating at a frequency different from the reference clock frequency used by the receiving side as a reference. However, as the amount of data transmitted by the image sensor increases recently, power consumption increases, and accordingly, problems such as localized image quality shading and a reduction in battery life have occurred.

The technical problem to be solved by the present invention is to provide a data interface capable of reducing power consumption by minimizing the number of CDRs in the data interface.

Another technical problem to be solved by the present invention is to provide a data transmission method capable of reducing power consumption by minimizing the number of CDRs in a data interface.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

The data interface according to an embodiment of the present invention for achieving the above technical problem generates a first bit set including a first bit included in the first image data and a third bit included in the second image data. And a second bit set including a second bit included in the first image data and being an upper bit of the first bit, and a fourth bit included in the second image data and being an upper bit of the third bit. A formatter that generates, a first serializer that serializes the first bit set, a second serializer that serializes the second bit set, and a second that converts the serialized first bit set to a first differential signal 1 output driver, a second output driver for converting the serialized second bit set into a second differential signal, and a plurality of transmitted to the formatter, the first and second serializers, and the first and second output drivers It includes a clock generator for generating a clock signal of.

In some embodiments of the present invention, the first differential signal may be transmitted through a High Density (HD) channel, and the second differential signal may be transmitted through a Light Density (LD) channel.

In some embodiments of the present invention, when there is no transition in the first or second bit set received from the formatter, a pre-logic for converting the first or second bit set into a bit set including one or more transitions (pre-logic) may be further included.

In some embodiments of the present invention, the first and second image data includes N (N is an even number) bits, and the first bit set is the lower N/2 bits of the first and second image data. And, the second bit set may include higher N/2 bits of the first and second image data.

In some embodiments of the present invention, the formatter converts the first and second image data into a third bit set, wherein the third bit set is included in the first image data, and the first bit and the second A fifth bit positioned between the bits and a sixth bit included in the second image data and positioned between the third bit and the fourth bit may be included.

In some embodiments of the present invention, a third serializer for serializing the third bit set and a third output driver for converting the serialized third bit set into a third differential signal may be further included.

In some embodiments of the present invention, the formatter includes a plurality of toggle counters for counting the number of transitions included in upper bits and lower bits of the first and second image data, and the first and second image data. A comparator for comparing the number of transitions included in the high-order bit and the low-order bit, and allocating a bit with a large transition among the high-order bit and the low-order bit to the first bit set, and a transition among the high-order bit and the low-order bit The plurality of multiplexers allocating fewer bits to the second bit set, and a dummy bit generator generating dummy bits indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set. ) Can be included.

In some embodiments of the present invention, the first bit set and the second bit set may further include a first dummy bit and a second dummy bit generated by the dummy bit generator, respectively.

A data transmission method according to an embodiment of the present invention for achieving the above technical problem includes a first bit set including a first bit included in the first image data and a third bit included in the second image data. A second bit that is received through a first channel and is included in the first image data and is an upper bit of the first bit, and a fourth bit that is included in the second image data and is an upper bit of the third bit. A second bit set is received through a second channel, the first and second bit sets are sampled based on a clock signal provided from a clock generator, and a multi-phase clock provided by a clock data recovery circuit (CDR circuit) By adjusting the signal, the sampling timing of each of the first and second bit sets is adjusted.

In some embodiments of the present invention, a first bit set including a first bit included in the first image data and a third bit included in the second image data is generated, and the first bit set is included in the first image data. A second bit set including a second bit that is an upper bit of the first bit and a fourth bit that is an upper bit of the third bit and included in the second image data is generated, and the first bit set and the second bit are It may further include serializing the two bit sets, and converting the serialized first bit set and the second bit set into a first differential signal and a second differential signal.

Details of other embodiments are included in the detailed description and drawings.

1 is a block diagram of an image capturing apparatus according to an embodiment of the present invention.
2 is a block diagram of a data interface according to an embodiment of the present invention.
3 is a diagram for explaining the frequency of transitions of an input signal of a data interface according to some embodiments of the present invention.
4 is a diagram illustrating a method of changing a data format of a data interface according to some embodiments of the present invention.
5 is a conceptual diagram illustrating a function of a clock data recovery circuit of a data interface according to some embodiments of the present invention.
6 is a timing diagram illustrating a sampling operation of a sampler according to some embodiments of the present invention.
7 is a block diagram of a data interface according to another embodiment of the present invention.
8 is a block diagram for explaining the structure of the pre-logic circuit of FIG. 7.
9 is a diagram for explaining the operation of the pre-logic circuit of FIG. 7.
10 is a block diagram of a data interface according to another embodiment of the present invention.
11 is a diagram illustrating a method of changing a data format of a data interface according to another embodiment of the present invention.
12 is a block diagram of a formatter according to some embodiments of the present invention.
13 is a block diagram of an image capturing apparatus according to another exemplary embodiment of the present invention.
14 is a block diagram of an image pickup device according to another embodiment of the present invention.
15 is a block diagram illustrating an example of application of an image pickup device according to embodiments of the present invention to a computing system.
16 is a block diagram illustrating an example of an interface used in the computing system of FIG. 15.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms different from each other, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have it, and the invention is only defined by the scope of the claims. The sizes and relative sizes of components indicated in the drawings may be exaggerated for clarity of description. Throughout the specification, the same reference numerals refer to the same elements, and “and/or” includes each and all combinations of one or more of the recited items.

When an element or layer is referred to as “on” or “on” of another element or layer, it is possible to interpose another layer or other element in the middle as well as directly above the other element or layer. All inclusive. On the other hand, when a device is referred to as "directly on" or "directly on", it indicates that no other device or layer is interposed therebetween.

When one element is referred to as “connected to” or “coupled to” with another element, when directly connected or coupled to another element, or interposing another element in the middle Includes all cases. On the other hand, when one element is referred to as “directly connected to” or “directly coupled to” with another element, it indicates that no other element is intervened.

Spatially relative terms "below", "beneath", "lower", "above", "upper", etc., as shown in the figure It may be used to easily describe the correlation between the device or components and other devices or components. Spatially relative terms should be understood as terms including different directions of the device during use or operation in addition to the directions shown in the drawings. For example, if an element shown in the figure is turned over, an element described as “below” or “beneath” of another element may be placed “above” another element. Accordingly, the exemplary term “below” may include both directions below and above. The device may be oriented in other directions, and thus spatially relative terms may be interpreted according to the orientation.

The terms used in the present specification are for describing exemplary embodiments and are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used in the specification, “comprises” and/or “comprising” do not exclude the presence or addition of one or more other elements other than the mentioned elements.

Although the first, second, etc. are used to describe various devices or components, it is a matter of course that these devices or components are not limited by these terms. These terms are only used to distinguish one device or component from another device or component. Therefore, it goes without saying that the first device or component mentioned below may be a second device or component within the technical idea of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used as meanings that can be commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not interpreted ideally or excessively unless explicitly defined specifically.

Hereinafter, a data interface according to an embodiment of the present invention and an image pickup device including the same will be described with reference to FIGS. 1 to 6.

1 is a block diagram of an image capturing apparatus according to an embodiment of the present invention.

Referring to FIG. 1, an image sensor 10 according to an embodiment of the present invention includes an image sensor 11 (CIS), an image signal processor 13, and a data interface 1 to 3 ).

The image sensor 11 detects light and converts it into an electrical signal, converts the electrical signal into an analog signal or a digital signal, and performs a filtering function for basic image processing (for example, processing such as standard conversion of an image). I can.

The image sensor 11 may be variously changed according to the type of image sensor cells. For example, the image sensor 11 may include a Charge Coupled Device (CCD) image sensor or a Complementary Metal Semiconductor (CMOS) image sensor. The CMOS image sensor uses CMOS technology that can simultaneously integrate a control circuit and a signal processing circuit, which are peripheral circuits, to create MOS transistors as many as the number of pixels and detect output through it. A switching method can be adopted. The CMOS image sensor is composed of a photodiode including a plurality of image sensor cells and a plurality of MOS transistors. Basically, light incident from the front and rear of the image sensor chip, that is, visible light, is converted into electrical signals to be imaged I can.

The CCD image sensor is a recording device using the accumulation and transfer of electric charges. The CCD image sensor can sequentially transfer analog signal charges in a certain direction, and can convert an image into an electric signal using the transfer function. Since the CCD image sensor has a relatively simple structure in which a thin oxide film is attached to a silicon substrate and a plurality of electrodes are arranged thereon, high density integration is possible, and a volatile element with low power consumption can be included.

The image signal processing unit 13 processes the digital signal received from the image sensor 11, for example, by converting a color format, correcting deteriorated pixels, etc., into an electrical signal suitable for a controller (not shown) of the camera module. It can perform the function of converting and delivering. The image signal processing unit 13 may output the processed image data to the display unit through the interface device. The image signal processing unit 13 may correct a gain of the amount of light or adjust a white balance with respect to the electric signal output from the image sensor 11. The image signal processing unit 13 may output the processed image data to a control unit in an application processor.

The data interfaces 1 to 3 may include a transmitter 100 (Tx; transmitter), a receiver 200 (Rx; reciever), and a channel 300 (channel). The transmitter 100 may transmit a digital signal output from the image sensor 11 to the receiver 200 using a plurality of channels included in the channel 300. A detailed description of this will be described later.

2 is a block diagram of a data interface according to an embodiment of the present invention.

Referring to FIG. 2, a data interface 1 according to an embodiment of the present invention includes a transmitter 100, a receiver 200, and a channel 300. The transmission unit 100 includes a formatter 110, a serializer 121, 123, a data path 131, 133, and an output driver 141, 143. , A clock generator 180 (CLK_GEN), and a PLL (Phase Locked Loop) circuit 190 may be included.

The formatter 110 may change the format of the received bit set. Specifically, the formatter 110 receives a plurality of bit sets each including N bits (N is a natural number of 2 or more), and includes a least significant bit (LSB) of each of the plurality of bit sets. A second bit set including one bit set and a Most Significant Bit (MSB) of each of the plurality of bit sets may be generated.

For example, when the formatter 110 receives a bit set of a first pixel including N bits and an image signal of a second pixel, the lower N/2 bits of the bit set of the first and second pixels are A second bit set including the included first bit set and the higher N/2 bits of the bit set of the first and second pixels may be generated. However, the present invention is not limited thereto, and a first bit set including the least significant bit of each bit set and a second bit set including the most significant bit of each bit set by using the received three image signals , A third bit set including a bit positioned at the center of each bit set may be generated. A detailed description of this will be described later.

The first bit set generated by the formatter 110 may have a greater number of transitions than the second bit set. For example, the initial image may have a plurality of pixel data including RGB values that gradually change between adjacent pixels. Pixel data gradually changing may form relatively few transitions in MSB bits, and relatively many transitions in LSB bits. That is, when a bit changes from 1 to 0 or from 0 to 1, there may be more transitions in the first bit set than in the second bit set. Accordingly, a channel to which the first bit set moves may be a high density (HD) channel with many transitions, and a channel to which the second bit set moves may be a low density (LD) channel with relatively few transitions.

On the other hand, the transition pattern of LSB bits and MSB bits may be changed by initial image data. For example, the initial image may have a check board pattern having a large number of edges, and RGB data may change rapidly on the edges of the check board pattern. The abrupt change in RGB data on the edges can cause the transition of MSB bits to be more than the transition of LSB bits. Accordingly, in another embodiment of the present invention, the LD channel may transmit a bit set having a small transition among the first bit set and the second bit set, and the HD channel may transmit a bit set having a large number of transitions among the first bit set and the second bit set. Set can be transmitted.

The formatter 110 may be connected to the first serializer 121 and the second serializer 123. The first bit set including the LSB generated by the formatter 110 may be transmitted to the first serializer 121, and the second bit set including the MSB may be transmitted to the second serializer 123. have.

Based on the first bit set and the second bit set, in order to select a bit set with more or less transitions, a plurality of toggle counters that count the number of transitions included in the upper bit set and the lower bit set of image data (not shown) A), a comparator (not shown) that compares the number of transitions included in the upper bit set and the lower bit set, and the bit set with many transitions is allocated to the first bit set, and the bit set with less transition is assigned to the second bit set. Includes a plurality of multiplexers (not shown) for allocation, and a plurality of dummy bit generators (not shown) for generating dummy bits indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set. can do. However, the present invention is not limited thereto, and a detailed description thereof will be described later in FIG. 12.

Free logic (151 and 153 of FIG. 7) may exist between the formatter 110 and the first serializer 121 or between the formatter 110 and the second serializer 123. A detailed description of this will be described later.

The serializers 121 and 123 may include a first serializer 121 and a second serializer 123. The serializers 121 and 123 may convert signals input in parallel into serial signals. For example, the serializers 121 and 123 may convert a signal input in parallel through 10 lines into a serial signal output through two lines. That is, the serializers 121 and 123 can convert the ratio of the input and output into 10: 2. In this case, the two output signals may be divided into an even signal and an odd signal and converted. However, the present invention is not limited thereto, and the ratio of the input to the output may be variously changed. For example, it is possible to change the ratio of input and output to n: m (however, m is a natural number less than n).

The first and second serializers 121 and 123 may be connected to one clock generator 180. The first and second serializers 121 and 123 may receive a clock generated by one clock generator 180 and convert a parallel signal into a serial signal using the clock. The first serializer 121 may be connected to the first data path 131, and the second serializer 123 may be connected to the second data path 133.

The data paths 131 and 133 may include a first data path 131 and a second data path 133.

The data paths 131 and 133 may allocate serialized data and transfer the allocated serialized data to the output drivers 141 and 143. In addition, the data paths 131 and 133 may combine a plurality of signals received from the serializers 121 and 123 into one and transmit them to the output drivers 141 and 143. For example, before transmitting signals to the output drivers 141 and 143, the first and second serializers 121 and 123 may reduce the load caused by high-speed serial data transmission. By selecting an even signal and an even signal, each received bit set can be divided into an even signal and an odd signal. When the first data path 131 receives two signals including an even signal and an odd signal from the first serializer 121, the first data path 131 converts the even signal and the odd signal into one signal. After being combined with, it can be transmitted to the first output driver 141. However, the present invention is not limited thereto. The second data path 133 may operate substantially the same as the first data path 131.

The first and second data paths 133 may receive a clock generated by one clock generator 180 and operate using a corresponding clock. For example, the clock generator 180 may provide a clock having the same frequency to the first and second data paths 131 and 133. However, the present invention is not limited thereto.

The output drivers 141 and 143 amplify the data received in the first and second data paths 131 and 133 and then transmit the data through the channel 300. The output drivers 141 and 143 may include a first output driver 141 and a second output driver 143.

The first output driver 141 may be connected to the first data path 131 and the first channel 310 of the channel 300. The first output driver 141 may receive the first data (serialized first bit set) received from the first data path 131, amplify it, and transmit it to the first channel 310. Similarly, the second output driver 143 may be connected to the second data path 133 and the second channel 320 of the channel 300. The second output driver 143 may receive the second data (serialized second bit set) received from the second data path 133, amplify it, and transmit it to the second channel 320.

Although not clearly shown in the drawings, an error in determining whether or not the data output from the data paths 131 and 133 is deserialized again, and the deserialized signal is compared with the signal input to the serializers 121 and 123 It may further include a checker (not shown). The error checker (not shown) may be connected to the output terminals of the data paths 131 and 133 and the input terminals of the serializers 121 and 123. Also, an error checker (not shown) may be connected for each channel. However, the present invention is not limited thereto.

The first data may have a larger number of transitions than the second data. Accordingly, the first channel 310 of the channel 300 through which the first data is transmitted corresponds to the HD channel, and the second channel 320 of the channel 300 through which the second data is transmitted corresponds to the LD channel.

The PLL circuit 190 is a frequency negative feedback circuit configured to always keep the frequency of the output signal constant according to the reference signal. Specifically, the PLL circuit 190 is an electronic circuit that matches the input signal and the reference frequency, and the output signal and the frequency. By detecting the phase difference between the input signal and the output signal, and controlling a voltage controlled oscillator (VCO), an accurately fixed frequency signal can be transmitted. The PLL circuit 190 allows the signal to be maintained in a specific phase. That is, the PLL circuit 190 may serve to forcibly hold an accurate fixed point so that the phase of the periodic signal does not fluctuate. The PLL circuit 190 is a reference channel of the channel 300 that transmits the reference signal. It may be connected to 340. The PLL circuit 190 of the transmitter 100 may share a reference signal with the PLL circuit 290 of the receiver 200. The PLL circuit 190 is to the clock generator 180. It can provide a reference signal.

The clock generator 180 may transmit a clock signal to the serializers 121 and 123 and the data paths 131 and 133 based on the reference signal of the PLL circuit 190. Specifically, the clock generator 180 may receive a reference signal from the PLL circuit 190 and generate a clock for controlling the serializers 121 and 123 and the data paths 131 and 133. The generated clock may be transmitted to the first and second serializers 123 and the first and second data paths 133. However, the present invention is not limited thereto.

The channel 300 may include a first channel 310, a second channel 320, and a reference channel 340. The first channel 310 is connected to the first output driver 141 of the transmitting unit 100 and the first input driver 211 of the receiving unit 200 to transmit first data including a first bit set. . The second channel 320 is connected to the second output driver 143 of the transmitter 100 and the second input driver 213 of the receiver 200 to transmit second data including a second bit set. . The reference channel 340 may be connected to the PLL circuit 190 of the transmitter 100 and the PLL circuit 290 of the receiver 200 to transmit a reference signal.

The first data may have a larger number of transitions than the second data. Accordingly, the first channel 310 through which first data is transmitted may correspond to an HD channel, and the second channel 320 through which second data is transmitted may correspond to an LD channel.

The first channel 310 and the second channel 320 may be formed of a pair of lines. This is for the first channel 310 and the second channel 320 to use a differential channel transmission method. The differential channel transmission method generates a positive signal and a negative signal for one transmission signal, and then generates a positive signal to one of a pair of lines and a negative signal to the other. This is a method of transmitting signals. The input drivers 211 and 213 of the receiving end may recover the original transmission signal by using the difference between the two signals. Since the differential channel transmission method uses the difference between the two signals, it is more resistant to noise and interference than the case of transmitting a signal through a single line.

Accordingly, the output drivers 141 and 143 may generate a clock edge modulated signal for differential channel transmission. Specifically, a channel driver (not shown) may generate a positive signal and a negative signal for one transmission signal and supply it to the channel 300. For example, the first output driver 141 generates a positive signal and a negative signal for first data including a first bit set, and the positive signal refers to the HDa channel of the first channel 310. The negative signal may be transmitted through the HDb channel of the first channel 310. The second output driver 143 may also transmit to the second channel 320 in the same manner. However, the present invention is not limited thereto, and the first channel 310 and the second channel 320 may be formed as a single channel.

The receiving unit 200 includes input drivers 211 and 213 (reciever), samplers 221 and 223 (sampler), deserializers 231 and 233 (deserializer), and a clock data recovery circuit 240 (Clock Data Recovery circuit). ; CDR), a synchronization unit 250 (synchronizer; Sync), a reporter 260 (Re-formater), may include a PLL circuit 290.

The input drivers 211 and 213 may include a first input driver 211 connected to the first channel 310 and a second input driver 213 connected to the second channel 320. The input drivers 211 and 213 may be connected to the samplers 221 and 223. Specifically, the first input driver 211 receives the first differential signal transmitted through the first channel 310 and transmits it to the first sampler 221, and the second input driver 213 receives the second channel ( A second differential signal transmitted through 320 may be received and transmitted to the second sampler 223. The input drivers 211 and 213 can generate one signal by combining a pair of positive and negative signals transmitted according to a differential channel transmission method into one. have. Each of the first and second differential signals may include a pair of positive and negative signals. The input drivers 211 and 213 may convert the received differential signal into data for providing a bit set to the samplers 221 and 223.

Although not clearly shown in the drawings, the input drivers 211 and 213 may include a pre-amp (not shown) or an equalizer (not shown). A preamplifier (not shown) and an equalizer (not shown) compensate for the size and delay characteristics of the data of the serial data stream received through the channel 300 and transfer the compensated data to the first and second samplers 221 and 223. I can deliver. Specifically, the preamplifier (not shown) and the equalizer (not shown) receive a serialized data stream through a transmission line, amplify the voltage of the received data, and equalize the amplified data to make jitter of the received data, especially interference between signals. Data signal distortion due to (Inter Symbol Interference; ISI) can be compensated. However, the present invention is not limited thereto.

The samplers 221 and 223 may include a first sampler 221 and a second sampler 223. The samplers 221 and 223 may sample data received from the input drivers 211 and 213 based on a sampling clock provided by the clock generator 208. The first and second samplers 221 and 223 may obtain serialized data (eg, sampled data) through sampling from the received data. The first sampler 221 and the second sampler 223 may share one clock data recovery circuit 240.

The first sampler 221 may receive first received data from the first input driver 211. The first sampler 221 samples the first received data using a clock input from the clock generator 280 and outputs the first sampled data.

The second sampler 223 may receive second received data from the second input driver 213. The second sampler 223 may sample the second received data by using a clock input from the clock generator 280 and output second sampled data.

The deserializers 231 and 233 may include a first deserializer 231 and a second deserializer 233. The first deserializer 231 may convert the first sampled data generated by the first sampler 221 into first deserialized data. A ratio of conversion from the first sampled data to the first non-serialized data may be 1:n. The output terminal of the first sampler 221 may be connected to the first deserializer 231. The output signal of the first deserializer 231 may be transmitted to the clock data recovery circuit 240.

The second sampler 223 may be connected to the second deserializer 233. The second deserializer 233 may convert second sampled data generated by the second sampler 223 into second deserialized data. A ratio of conversion from the second sampled data to the second non-serialized data may be 1:n. The output terminal of the second sampler 223 may be connected to the synchronization unit 250. The output signal of the second deserializer 233 may be transmitted to the synchronization unit 250.

The clock data recovery circuit 240 determines the sampling clock phase of the first sampler 221 based on edge information included in the output signal of the first deserializer 231 and the output signal of the first deserializer 231. It can be received as a phase feedback to adjust. The first sampler 221 may sample the first received data while maintaining an appropriate sampling timing by repeating the series of feedback processes described above.

The second sampler 223 may share the first sampler 221 and the clock data recovery circuit 240. The sampling clock for determining the sampling timing of the second sampler 223 may be adjusted by phase feedback of the clock data recovery circuit 240 according to an output signal of the first deserializer 231.

The clock data recovery circuit 240 may provide the clock generator 280 with a first phase feedback based on edge information of the first deserialized data provided by the first deserializer 231. The clock generator 280 may adjust the sampling timing of the first sampler 221 and the second sampler 223 using the first phase feedback. The clock data recovery circuit 240 may provide a second phase feedback based on edge information of the second deserialized data provided by the second deserializer 233 or the synchronization unit 250 to the clock generator 280. I can. The clock generator 280 may adjust the sampling clock phases of the first sampler 221 and the second sampler 223 using the second phase feedback. However, the present invention is not limited thereto.

The clock generator 280 is based on a reference clock generated using a signal of the PLL circuit 290 of the receiving unit 200 and a feedback provided from the clock data recovery circuit 240, the first sampler ( A sampling clock provided to the 221 and the second sampler 223 may be generated. Also, the clock generator 280 may generate clocks provided to the first deserializer 231 and the second deserializer 233.

Although not clearly shown in the drawing, the clock generator 280 may include a phase detector (not shown), a PI controller (Phase Interpolator Controller; not shown), and a phase interpolator (not shown). However, the present invention is not limited thereto.

The phase interpolator (not shown) provides a multi-phase clock to the clock generator 280 to adjust the phase of the clock input to each of the samplers 221 and 223. For example, the phase interpolator (not shown) receives four clocks of 0 degrees / 90 degrees / 180 degrees / 270 degrees from the PLL circuit 290 and based on the digital code value from the PI controller (not shown). It is possible to increase or decrease the phases of the four clocks of 0°/90°/180°/270°. However, the present invention is not limited thereto.

The synchronization unit 250 may provide a phase feedback to the clock data recovery circuit 240 using an output signal of the second deserializer 233, and through this, the sampling timing of the second sampler 223 And, it is possible to adjust the skew of data restored from the second deserializer 233. The synchronization unit 250 may communicate with the clock data recovery circuit 240. That is, the synchronization unit 250 compares the output timing of the data restored from the clock data recovery circuit 240 and the second deserializer 233, and restores it from the synchronization unit 250 and the clock data recovery circuit 240. You can adjust the distortion of the output of the data. The clock data recovery circuit 240 may adjust the sampling clock by comparing output timings of the deserializers 231 and 233 based on the phase feedback of the first deserializer 231 and the synchronization unit 250.

As a result, the formatter 110 of the transmitter 100 of the data interface 1 according to an embodiment of the present invention receives the first and second image data from the image sensor 11, and receives the first and second image data. 2 The image data may be converted into a first or second bit set. Here, the first bit set includes a first bit that is a lower bit included in the first image data and a third bit that is a lower bit included in the second image data, and the second bit set is the A second bit included in the first image data and being an upper bit of the first bit, and a fourth bit included in the second image data and being an upper bit of the third bit.

Subsequently, the first serializer 121 serializes the first bit set received from the formatter 110, and the second serializer 123 serializes the second bit set received from the formatter 110 I can make it.

Subsequently, the first channel 310 of the channel 300 transmits the serialized first bit set to the first input driver 211 of the reception unit 200 using the differential channels 311 and 313, and the second The channel 320 may transmit the serialized second bit set to the second input driver 213 of the receiver 200 using the differential channels 321 and 323.

Subsequently, the first sampler 221 of the receiving unit 200 samples the first bit set received from the first input driver 211, and the second sampler 223 is input from the second input driver 213 The received second bit set may be sampled.

Subsequently, the first deserializer 231 parallelizes the first bit set sampled from the first sampler 221, and the second deserializer 233 parallelizes the first bit set sampled from the second sampler 223. The second bit set can be parallelized.

Subsequently, the clock data recovery circuit 240 and the clock generator 280 adjust the clocks input to the first and second samplers 221 and 223 using the output of the first deserializer 231, The sampling timing of the first and second bit sets may be adjusted. At the same time, the synchronization unit 250 provides a feedback to the clock data recovery circuit 240 based on the output of the second deserializer 233, thereby recovering the first and second image data. The distortion of the second bit set can be adjusted.

Subsequently, the reporter 260 may extract the first and second image data from the first and second bit sets. The reporter 260 may be connected to the synchronization unit 250 and the clock data recovery circuit 240. The reporter 260 receives the first bit set and the second bit set included in the outputs of the first and second samplers 221 and 223 from the synchronization unit 250 and the clock data recovery circuit 240, The first and second image data may be extracted by performing an operation performed by the formatter 110 in reverse order. That is, the formatter 110 and the reporter 260 may perform complementary functions.

Subsequently, the first and second image data output from the reporter 260 may be transmitted to the image processing apparatus 13. However, the present invention is not limited thereto.

The data interface 1 according to the present invention can be applied to a data communication system having a sampler and a clock data recovery circuit. However, the data interface 1 according to the present invention is not limited to a data communication system having a serializer-deserializer, and if it is a data communication system having samplers 221 and 223 and a clock data recovery circuit 240, serialization is performed. It goes without saying that it can be applied even when the groups 121 and 123 and/or the deserializers 121 and 123 are not included.

3 is a diagram for explaining the frequency of transitions of an input signal of a data interface according to some embodiments of the present invention.

Referring to FIG. 3, FIG. 3 is a graph showing the frequency of transitions of 10-bit input signals to the data interfaces 1 and 2 according to some embodiments of the present invention.

According to the graph, assuming that the frequency of the transition of the least significant bit of the input signal is 1, the frequency of the transition of the sixth bit of the input signal is about 0.031. That is, assuming that the number of transitions of the least significant bit is 100, the number of transitions of the 6th bit may occur about 3 times. The number of transitions may be exponentially decreased from a lower bit to an upper bit. For example, the initial image may have a plurality of pixel data including RGB values that gradually change between adjacent pixels. Pixel data gradually changing may form relatively few transitions in MSB bits, and relatively many transitions in LSB bits.

On the other hand, the transition pattern of LSB bits and MSB bits may be changed by initial image data. For example, the initial image may have a check board pattern having a large number of edges, and RGB data may change rapidly on the edges of the check board pattern. The abrupt change in RGB data on the edges can cause the transition of MSB bits to be more than the transition of LSB bits.

Therefore, the LD channel can transmit a bit set having a small transition among the first bit set and the second bit set, and the HD channel can transmit a bit set having a large transition among the first bit set and the second bit set. Based on the first bit set and the second bit set, in order to select a bit set with more or less transitions, the formatter 110 includes a plurality of registers (not shown), and the upper bit set and the lower bit set of the image data. A plurality of toggle counters (not shown) that count the number of included transitions, a comparator (not shown) that compares the number of transitions included in the upper bit set and the lower bit set, and the bit set with many transitions are added to the first bit set. And a plurality of multiplexers (not shown) for allocating and allocating a bit set with a small transition to a second bit set, and a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set. It may include a plurality of dummy bit generators (not shown) for generating. However, the present invention is not limited thereto, and a detailed description thereof will be described later in FIG. 12.

4 is a diagram illustrating a method of changing a data format of a data interface according to some embodiments of the present invention.

4, the formatter 110 converts the received first image data P1 and first image data P2 into a first bit set P1' and a second bit set P2'. Data formatting can be performed.

The first bit set (P1') includes a first bit included in the first image data P1 and a third bit included in the second image data P2, and the second bit set ( P2') is a second bit included in the first image data P1 and being an upper bit of the first bit, and a fourth bit included in the second image data P2 and being an upper bit of the third bit. It may include.

For example, when the first image data P1 and the second image data P2 are composed of 10 bits, the lower five bits of the first image data P1 and the lower five bits of the second image data P2 The bits may be combined to form the first bit set P1'. In the same manner, the second bit set P2' may be formed by combining the upper five bits of the first image data P1 and the upper five bits of the second image data P2.

Since the first bit set P1 ′ is composed of the lower five bits, it may include a larger number of transitions than the second bit set P2 ′. Accordingly, the first channel 310 transmits a first bit set P1' of high density (HD), and the second channel 320 is a second bit set P2' of high density (LD). Will be transmitted.

Since a sufficient transition is secured in the first bit set P1 ′, a separate line coding (lind-coding) may not be performed. In case of line coding, an additional bit for decoding is required. Accordingly, when line coding is not performed, a bandwidth as much as an additional bit necessary for line coding can be additionally secured. For example, when line coding a 10-bit input signal, an additional 2 bits are required. In this case, when line coding is eliminated, a bandwidth of about 20% can be additionally secured.

Since the second bit set P2' has a significantly lower transition frequency than that of the first bit set P1', even if a separate clock data recovery circuit 240 is not provided, the first bit set P1' After sampling is performed using the clock data recovery circuit 240 used, it may be sufficient to adjust the sync.

Through this, the clock data recovery circuit 240 is not used for each channel, and one clock data recovery circuit 240 can be shared and used in two channels. Accordingly, it is possible to reduce the size and complexity of the data interface. In addition, since the clock data recovery circuit 240 consumes a large amount of power, if the number of the clock data recovery circuit 240 used is reduced, the power and cost used in the clock data recovery circuit 240 can be reduced. I can.

In addition, in the case of devices such as the second serializer 123, the second deserializer 233, and the second sampler 223 connected to the channel through which the second bit set P2' passes, the amount of power used is determined. Can be reduced.

On the other hand, as mentioned above, the transition pattern of LSB bits and MSB bits can be changed by the initial image data. The LD channel may transmit a bit set having a small transition among the first bit set and the second bit set, and the HD channel may transmit a bit set having a large transition among the first bit set and the second bit set. Based on the first bit set and the second bit set, in order to select a bit set with more or less transitions, the formatter 110 includes a plurality of registers (not shown), and the upper bit set and the lower bit set of the image data. A plurality of toggle counters (not shown) that count the number of included transitions, a comparator (not shown) that compares the number of transitions included in the upper bit set and the lower bit set, and the bit set with many transitions are added to the first bit set. And a plurality of multiplexers (not shown) for allocating and allocating a bit set with a small transition to a second bit set, and a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set. It may include a plurality of dummy bit generators (not shown) for generating. A detailed description of this will be described later in FIG. 12.

5 is a conceptual diagram illustrating a function of a clock data recovery circuit of a data interface according to some embodiments of the present invention.

Referring to FIG. 5, the samplers 221 and 223 may sample input received data to obtain data at a specific moment. The sampling timing of the samplers 221 and 223 may be adjusted by a sampling clock input to the samplers 221 and 223. Arrows indicate sampling points of the samplers 221 and 223.

A plurality of transitions may occur in the input signal. The samplers 221 and 223 may perform a plurality of sampling times per period T according to an oversampling scheme. For example, the samplers 221 and 223 may perform eight sampling times based on the multi-phase clock provided by the clock generator 280. However, the present invention is not limited thereto.

The clock data recovery circuit 240 receives phase difference information from the samplers 221 and 223 and/or the deserializers 231 and 233, analyzes the phase difference information, and inputs a multi-phase clock. The phase of can be adjusted. The clock data recovery circuit 240 may transmit a feedback signal to the clock generator 280 so that the sampling timing of the samplers 221 and 223 comes to the center of one period. Q means the middle between the edges of both sides of the received data. The clock generator 280 may generate a multi-phase clock based on the received feedback signal. However, the present invention is not limited thereto.

6 is a timing diagram illustrating a sampling operation of a sampler according to some embodiments of the present invention.

Referring to FIG. 6, the clock data recovery circuit 240 synchronizes the output of data restored from the first channel 310 (for example, an HD channel) and the second channel 320 (for example, an LD channel). For this, timing feedback may be provided to the synchronization unit 250. In order to synchronize the output of the restored data, the synchronization unit 250 may adjust skew of the output of the second deserializer 233. In the process of reaching the reporter 260 through the clock data recovery circuit 240 at the output of the first deserializer 231, a circuit delay may occur. The synchronization unit 250 may adjust distortion from the second deserializer 231 to the reporter 260 based on timing feedback from the clock data recovery circuit 240.

7 is a block diagram of a data interface according to another embodiment of the present invention. 8 is a block diagram for explaining the structure of the pre-logic circuit of FIG. 7. 9 is a diagram for explaining the operation of the pre-logic circuit of FIG. 7. For convenience of description, hereinafter, redundant descriptions of the same matters as those of the above-described embodiment will be omitted, and differences will be mainly described.

Referring to FIG. 7, a data interface 2 according to another embodiment of the present invention includes a transmission unit 100, a reception unit 200, and a channel 300, and the transmission unit 100 includes free logics 151 and 153. ) May be further included. The receiving unit 200 may further include post logics 261 and 263. The data interface 2 according to another embodiment of the present invention may be formed substantially the same as the data interface 1 described with reference to FIG. 2.

The transmitter 100 may include a formatter 110, pre-logics 151 and 153, serializers 121 and 123, data paths 131 and 133, and output drivers 141 and 143. The formatter 110 may receive first and second image data from the image sensor 11 and convert the first and second image data into a first or second bit set. The first bit set may include a first bit included in the first image data and a third bit included in the second image data. The second bit set may include a second bit included in the first image data and being an upper bit of the first bit, and a fourth bit included in the second image data and being an upper bit of the third bit. have. For example, when the first and second image data have N bits (N is an even number), the first bit set includes the lower N/2 bits of the first and second image data, and the The second bit set may include higher N/2 bits of the first and second image data. However, the present invention is not limited thereto, and even when the first and second image data have an odd number of bits, it may be applied by dividing the upper bit and the lower bit in the same manner.

8 to 9, when there is no transition in the first or second bit set received from the formatter 110, the free logic 151 and 153 It can be converted to a bit set including a transition. The pre-logics 151 and 153 include a first pre-logic 151 that operates when there is no transition in the first bit set, and a second pre-logic 153 that operates when there is no transition in the second bit set. can do. The first pre-logic 151 and the second pre-logic 153 may be connected to the same formatter 110. The first pre-logic 151 may receive a first bit set from the formatter 110, and the second pre-logic 153 is a second bit set with a smaller transition than the first bit set from the formatter 110. Can be received. However, the present invention is not limited thereto.

The free logics 151 and 153 may include an inverter 1510 and NOR gates 1511 to 1519.

The inverter 1510 inverts the least significant bit D0 of the first bit set or the second bit set, and the NOR gates 1511 to 1519 receive two consecutive bits as inputs and receive the least significant bit D0. The result value can be output to the upper bits (D1-D9) of ). For example, referring to FIG. 8, in the case of the free logics 151 and 153 that receive 10 bits as inputs, one inverter 1510 and nine NOR gates 1511 to 1519 may be included. The inverter 1510 inverts the D0 bit, and the first NOR gates 1511 to 1519 receive the D0 bit and the D1 bit as inputs, and generate an output of the D1' bit. Similarly, the second NOR gate 1511 receives the D1 bit and the D2 bit as inputs and generates an output of the D2' bit.

Referring to FIG. 9, the pre-logics 151 and 153 monitor bitsets that come into the formatter 110. If an input without a transition is input to the Nth bit set (B1(N), B2(N)), the (N+1)th bit set (B1(N+1), B2(N+1)) is also When an input without a transition continuously comes in, the free logics 151 and 153 may operate. For example, '0000000000' or '1111111111' is input to the Nth bit set (B1(N), B2(N)), and the (N+1)th bit set (B1(N+1), B2) When an input of '0000000000' or '1111111111' which is the same as the Nth bit set (B1(N), B2(N)) is input to (N+1)), the pre-logics 151 and 153 may operate. In this case, the inverter 1510 of the pre-logics 151 and 153 inverts the least significant bit of the (N+1)th bit set (B1(N+1), B2(N+1)) to generate a transition. I can. If a signal without a transition is continuously supplied, when sampling is performed at the receiving end, a sampling timing may be shifted or an edge may be missed. The pre-logics 151 and 153 are devices for converting signals including transitions B1'(N+1) and B2'(N+1) to prevent this. The bit converted by the operation of the pre-logics 151 and 153 may be restored to the original signal through inverse transformation at the receiving end.

Referring back to FIG. 7, the first serializer 121 may be connected to the first free logic 151 and serialize the first bit set received from the first free logic 151. The second serializer 123 is connected to the second free logic 153 and serializes the second bit set received from the second free logic 153.

The data paths 131 and 133 may include a first data path 131 and a second data path 133. The data paths 131 and 133 may transmit the received serialized data to the driver. The first serializer 121 may be connected to the first data path 131, and the second serializer 123 may be connected to the second data path 133.

The first and second serializers 121 and 123 and the first and second data paths 131 and 133 may receive a clock generated by one clock generator 280 and operate using the corresponding clock. . For example, the clock generator 280 may provide clocks of the same frequency to the first and second data paths 133. However, the present invention is not limited thereto.

The output drivers 141 and 143 amplify the data received from the first and second data paths 131 and 133 and then transmit the data through the channel 300. The output drivers 141 and 143 may include a first output driver 141 and a second output driver 143. The first output driver 141 may be connected to the first data path 131 and the first channel 310 of the channel 300. The first output driver 141 may receive the first data (serialized first bit set) received from the first data path 131, amplify it, and transmit it to the first channel 310. Similarly, the second output driver 143 may be connected to the second data path 133 and the second channel 320 of the channel 300.

The data interface 2 further adds pre-logics 151 and 153 to the data interface 1 according to an embodiment of the present invention, so that the formatter 110 generates a first bit set and a second bit set. It is possible to solve the problem of continuously transmitting a signal without a transition during the transmission process.

The reporter 260 may be connected to the first and second post logics 261 and 263. In addition, the reporter 260 may be connected to the first and second synchronization units 251 and 253 (see FIG. 10), respectively. The post logics 261 and 263 may perform operations performed by the pre-logics 151 and 153 in reverse order to extract the first and second bit sets from the first to third bit sets. However, the present invention is not limited thereto.

Based on the first bit set and the second bit set, in order to select a bit set with more or less transitions, the formatter 110 includes a plurality of registers (not shown), and the upper bit set and the lower bit set of the image data. A plurality of toggle counters (not shown) that count the number of included transitions, a comparator (not shown) that compares the number of transitions included in the upper bit set and the lower bit set, and the bit set with many transitions are added to the first bit set. And a plurality of multiplexers (not shown) for allocating and allocating a bit set with a small transition to a second bit set, and a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set. It may include a plurality of dummy bit generators (not shown) for generating. A detailed description of this will be described later in FIG. 12.

10 is a block diagram of a data interface according to another embodiment of the present invention. 11 is a diagram illustrating a method of changing a data format of a data interface according to another embodiment of the present invention. For convenience of description, hereinafter, redundant descriptions of the same matters as those of the above-described embodiment will be omitted, and differences will be mainly described.

Referring to FIGS. 10 and 11, the data interface 3 according to another embodiment of the present invention may be formed substantially the same as the data interface 1 described with reference to FIG. 2. The data interface 3 according to another embodiment of the present invention includes a transmission unit 100, a reception unit 200, and a channel 300, and the transmission unit 100 includes a third serializer 125 and a third data. Paths 131 and 133 and third output drivers 141 and 143 may be further included.

The formatter 110 may convert the first and second image data into first to third bit sets. The first bit set may include a first bit included in the first image data and a third bit included in the second image data. The second bit set may include a second bit included in the first image data and being an upper bit of the first bit, and a fourth bit included in the second image data and being an upper bit of the third bit. have. The third bit set is a fifth bit included in the first image data and positioned between the first bit and the second bit, and a fifth bit included in the second image data and between the third bit and the fourth bit It may include a sixth bit positioned at. That is, the third bit set may consist of center bits of an input image signal.

This conversion may be performed by combining two or more input image signals. For example, referring to FIG. 11, when the first to third image signals P1 to P3 of 12 bits are input, the first bit set P1 is composed of a combination of the least significant four bits, and the second The bit set P2 may be formed of a combination of the most significant four bits. The third bit set P3 may be formed of a combination of the remaining four bits. The first bit set P1' may include the largest number of transitions among the set, and the second bit set P3' may include the smallest transition. The third bit set P2 ′ may have a transition intermediate between the first bit set P1 ′ and the second bit set P3 ′.

Referring back to FIG. 10, the first bit set generated by the formatter 110 is transmitted to the first serializer 121 and the second bit set is transmitted to the second serializer 123. The subsequent process is the same as the data interface 1 described with reference to FIG. 2. The third bit set is transmitted to the third serializer 125. After the third bit set undergoes a serialization process, the third bit set is transmitted to the third output driver 145 through the third data path 135. The third output driver 145 may transmit the third bit set to the receiver 200 through the channel 300.

Although not clearly shown in the drawing, when there is no transition in the third bit set received from the formatter 110, the transmission unit 100 converts the third bit set into a bit set including one or more transitions. A third free logic (not shown) may be further included.

The channel 300 may further include a third channel 330. The third channel 330 may be composed of a pair of differential channels 331 and 333.

The receiver 200 may further include a third input driver 215, a third sampler 225, a third deserializer 235, and a second synchronization unit 253. The third input driver 215 may receive a signal transmitted through the third channel 330 and transmit it to the third sampler 225. The third input driver 215 may generate one signal by combining a pair of positive and negative signals transmitted according to a differential channel transmission method into one.

The third sampler 225 may sample a signal received from the third input driver 215 according to a sampling timing. The third sampler 225 may obtain serialized data through sampling. The third sampler 225 may share a clock data recovery circuit 240 with the first and second samplers 221 and 223. The third sampler 225 may be connected to the third deserializer 235.

The third deserializer 235 may convert the serialized sampled data of the third sampler 225 into parallel data of a 1:n ratio and output deserialized data.

The third sampler 225 and the third deserializer 235 may operate by receiving a clock generated by the clock generator 280.

The synchronization unit 250 may include a first synchronization unit 251 and a second synchronization unit 253. The first synchronization unit 251 may be connected to the second deserializer 233, and the second synchronization unit 253 may be connected to the third deserializer 235.

The first synchronization unit 251 communicates with the clock data recovery circuit 240 and provides feedback to the clock data recovery circuit 240, thereby adjusting the sampling timing of the second sampler 223.

The second synchronization unit 253 communicates with the clock data recovery circuit 240 and provides feedback to the clock data recovery circuit 240 to adjust the sampling timing of the third sampler 225. That is, the sampling timing of the samplers 221, 223 and 225 is generated by the clock data recovery circuit 240 according to the feedback of the first deserializer 231 and the first and second synchronization units 251 and 253. It can be controlled by a clock. The first and second synchronization units 251 and 253 may have substantially the same structure and operate substantially the same as the synchronization unit 250 described with reference to FIG. 2.

The reporter 260 may be connected to the first and second synchronization units 251 and 253 and the clock data recovery circuit 240. The reporter 260 may extract first and second image data from the first to third bit sets by performing a task performed by the formatter 110 in reverse order.

The data interface 3 further increases the number of transmission channels by adding one additional channel sharing the clock data recovery circuit 240 to the data interface 1 according to the embodiment of the present invention of FIG. The bandwidth of 300 can be improved. In addition, since the number of the clock data recovery circuit 240 and the clock generator 280 can be reduced, power, complexity and size of the circuit can be further reduced.

Based on the first bit set and the second bit set, in order to select a bit set with more or less transitions, the formatter 110 includes a plurality of registers, the upper bit set and the lower bit set of the image data. A plurality of toggle counters that count the number, a comparator that compares the number of transitions included in the upper bit set and the lower bit set, and the bit set with many transitions are allocated to the first bit set, and the bit set with less transitions is the second bit. A plurality of multiplexers for allocation to the set, and a plurality of dummy bit generators for generating dummy bits indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set. I can. A detailed description of the formatter 110 according to an embodiment of the present invention will be described later in FIG. 12.

12 is a block diagram of a formatter according to some embodiments of the present invention.

Referring to FIG. 12, the formatter 110 includes a plurality of registers 101, a plurality of counters 103 and 104 that count the number of serial transitions included in the upper and lower bits of the image data, and the upper and lower bits. A comparator 105 for comparing the number of serial transitions included in the bit, and a plurality of multiplexers 108 and 109 for allocating bits with many transitions to the first bit set, and for allocating bits with few transitions to the second bit set. ), and a plurality of dummy bit generators 106 and 107 for generating dummy bits indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set.

Each of the first register 101 and the second register 102 may receive and store a high-order bit and a low-order bit from the first image data and the second image data, respectively. The first image data and the second image data may be RGB data of a pixel of an image sensor. Each of the counters 103 and 104 may be connected between the first and second registers 101 and 102 and the comparator 105, and the upper and lower bits stored in the first and second registers 101 and 102, respectively. You can count the number of serial transitions included in. The comparator 105 may receive a first counter value and a second counter value from the first counter 103 and the second counter 104, and compare the received first counter value and the second counter value. When the first counter value is greater than or equal to the second counter value, the comparator 105 may output a low logic signal to the multiplexers 108 and 109, and through this, the lower bit may be output to the LD channel. And the high-order bits can be output to the HD channel. The dummy bit generators 106 and 107 may add an additional bit 0'b to the lower bit and an additional bit 1'b to the upper bit in order to indicate which bit set is an upper bit or a lower bit. If the first image data and the second image data are 10-bit image data, the output of the HD channel and the LD channel image data may be 11-bit image data because of an additional dummy bit.

The reporter 260 may extract or remove dummy bits attached to the upper bit and the lower bit, respectively, based on the first image data and the second image data.

13 is a block diagram of an image capturing apparatus according to another exemplary embodiment of the present invention.

Referring to FIG. 13, an image capturing apparatus 800 according to another exemplary embodiment may include an image sensor 811 and an image signal processing unit 813. The image sensor 811 is an active pixel sensor (hereinafter, referred to as APS) array 810 in which pixels including photoelectric conversion elements are arranged two-dimensionally, a timing generator 820, and a row decoder. (row decoder) 830, row driver 840, correlated double sampler (CDS) 850, analog to digital converter (ADC) 860, latch unit ( latch 870, a column decoder 880, and the like.

The APS array 810 includes a plurality of unit pixels arranged in two dimensions. The plurality of unit pixels serves to convert an optical image into an electrical output signal. The APS array 810 may be driven by receiving a plurality of driving signals such as a row select signal, a reset signal, and a charge transfer signal from the row driver 840. In addition, the converted electrical output signal may be provided to the correlated double sampler 850 through a vertical signal line.

The APS array 810 may include CMOS type image pixels. Although not clearly shown in the drawing, pixels arranged in the APS array 810 may be arranged in a Bayer pattern or a chess mosaic form. When Bayer pattern technology is employed, pixels in the active APS array 810 may be arranged to receive red light, green light, and blue light, respectively. However, the inventive concept is not limited thereto, and the configuration of a plurality of active pixels arranged in the APS array 810 may be modified as much as possible. For example, in some other embodiments of the present invention, the plurality of active pixels disposed in the APS array 810 are magenta (Mg) light, yellow (Y) light, cyan (Cy) light, and/or white (W) light. It may be arranged to receive light.

The timing generator 820 may provide a timing signal and a control signal to the row decoder 830 and the column decoder 880.

The row driver 840 may provide a plurality of driving signals for driving a plurality of unit pixels to the active pixel sensor array 810 according to a result decoded by the row decoder 830. In general, when unit pixels are arranged in a matrix form, a driving signal may be provided for each row.

The correlated double sampler 850 may receive, hold, and sample an output signal formed in the active pixel sensor array 810 through a vertical signal line. That is, a specific noise level and a signal level generated by the output signal may be double-sampled to output a difference level corresponding to a difference between the noise level and the signal level.

The analog-to-digital converter 860 may convert an analog signal corresponding to a difference level into a digital signal and output it.

The latch unit 870 latches a digital signal, and the latched signal may be sequentially transmitted from the column decoder 880 to an image signal processor (ISP) 813 according to a decoding result.

The image signal processing unit 813 may be formed substantially the same as the image signal processing unit 13 described with reference to FIG. 1. The image signal processing unit 813 may correct a gain of an amount of light or adjust a white balance for the electric signal output from the image sensor 811. The image signal processing unit 813 may receive exposure data (ie, an image signal) of a captured image, and may remove noise included in the received image signal through correction.

The data interface 801 is located between the image sensor and the image signal processing unit, and may transmit the first and second image data received from the image sensor 811 to the image signal processing unit 813. The data interface 801 may operate substantially the same as the data interfaces 1 to 3 described above.

The first image data includes a first bit and a second bit that is an upper bit of the first bit, and the second image data includes a third bit and a fourth bit that is an upper bit of the third bit. can do.

The data interface 801 includes a transmitter for transmitting a first bit set including the first bit and the third bit, and a second bit set including the second bit and the fourth bit, and the first bit set. And a receiver including a clock data recovery circuit (CDR) that samples each of the second bit sets, and adjusts the sampling timing of the first and second bit sets by adjusting a clock used during the sampling.

In this case, the first and second image data may be input to a transmitting unit as a parallel signal, and the transmitting unit may convert the first and second bit sets into serial signals and transmit them to the receiving unit.

14 is a block diagram of an image pickup device according to another embodiment of the present invention.

Referring to FIG. 14, an image pickup apparatus 900 according to an embodiment of the present invention includes a zoom lens 902, an aperture 904, a focus lens 906, driving devices 902a, 904a, 906a, and CMOS ( Complementary Metal Oxide Semiconductor) element 908, CDS (Correlated Double Sampling) circuit 910 of an integrated amplifier, A/D converter 912, image input controller 914, image signal processing unit 916, compression processing unit 920 ), OSD(On Screen Display)(921), LCD(Liquid Crystal Display) Driver(922), LCD(924), Timing Generator(926), CPU(Central Processing Unit)(928), Control Panel(932), Shutter Button 933, memory 934, VRAM (Video Random Access Memory) 936, media controller 938, recording media 940, motor drivers 942a, 942b, 942c, flash 944. I can.

The zoom lens 902 is a lens whose focal length continuously changes by moving back and forth in the optical axis direction by the driving device 902a, and can take pictures by changing the size of the subject. The diaphragm 904 can adjust the amount of light entering the CMOS element 908 by the driving device 904a when taking an image. The focus lens 906 can be moved back and forth in the optical axis direction by the driving device 906a to adjust the focus of the subject.

Referring to FIG. 14, only one zoom lens 902 and focus lens 906 are shown, but the number of zoom lenses 902 may be two or more, and the number of focus lenses 906 may be two or more. I can.

The CMOS element 908 is an element for converting light incident from the zoom lens 902, the stop 904, and the focus lens 906 into electric signals. In the present embodiment, the time for extracting the electric signal by controlling the incident light by using the electronic shutter is controlled. However, the time for extracting the electric signal by controlling the incident light using the mechanical shutter can be adjusted. In an embodiment of the present invention, an image pickup unit may be configured with a zoom lens 902, an aperture stop 904, a focus lens 906, and a CCD device 910. In addition, the set of the imaging unit is not limited thereto, and may not include the zoom lens 902 or the aperture stop 904.

In some embodiments of the present invention, a CMOS device 908 is used, and the CDS circuit 910 includes a CDS circuit, which is a type of sampling circuit, which removes noise from an electrical signal output from the CMOS device 908, and noise. It is a circuit in which the amplifier that amplifies the electric signal after removing the is integrated. However, the present invention is not limited thereto, and in this embodiment, the digital photographing apparatus 900 is configured using a circuit in which a CDS circuit and an amplifier are integrated, but the CDS circuit and the amplifier may be configured as separate circuits. have.

The A/D converter 912 converts the electric signal generated by the CMOS device 908 into a digital signal, and can generate RAW data of an image.

The image input controller 914 can control input of RAW data of an image generated by the A/D converter into the memory 934.

The image signal processing unit 916 can correct the gain of the amount of light and adjust the white balance with respect to the electric signal output from the CMOS device 908. The image signal processing unit 916 acquires exposure data of a captured image. The exposure data may include an in-focus evaluation value (AF evaluation value) or an AE (auto exposure) evaluation value. The image signal processing unit 916 can calculate the in-focus evaluation value and the AE evaluation value.

Although not clearly shown in the drawings, the image signal processing unit 916 may receive the RAW of the image generated from the image input controller 914 using the data interfaces 1 to 3 according to some embodiments of the present invention. . However, the present invention is not limited thereto, and the data interfaces 1 to 3 may be used in communication between all modules in the image capturing apparatus 900.

The compression processing unit 920 may perform compression processing of compressing the image developed by the image signal processing unit 916 into image data in an appropriate format. The compression format of an image may include a reversible format or an irreversible format. Examples of suitable formats can be converted to JPEG (Joint Photographic Experts Group) format or JPEG 2000 format.

The OSD 921 may display a setting screen of the digital photographing apparatus 900 on the LCD 924. The LCD 924 can display a live view before performing a photographing operation, various setting screens of the imaging device 900, and a photographed image. However, the present invention is not limited thereto. Display of image data and various information of the imaging device 900 on the LCD 924 can be performed through the LCD driver 922.

The timing generator 926 inputs a timing signal to the CMOS device 908. The shutter speed is determined by the timing signal from the timing generator 926. That is, the driving of the CMOS device 908 is controlled by a timing signal from the timing generator 926, and the image light from the subject is incident within the time the CMOS device 908 is driven, thereby forming the basis of the image data. A signal can be generated.

The CPU 928 can issue a signal system command to the CMOS device 908, the CDS circuit 910, or the like, or can execute an operating system command for the operation of the operating unit 932. In the present embodiment, only one CPU is included, and a signal system command and an operation system command can be executed in separate CPUs.

The operation unit 932 may be provided with a member for operating the imaging device 900 or performing various settings at the time of photographing. In the member disposed on the operation unit 932, a power button (not shown), a cross key (not shown) for selecting a photographing mode or a photographing drive mode, and setting a soft focus effect, and a selection button (not shown) are arranged. I can. The shutter button 933 is for performing a photographing operation, and can focus on the subject in a half-pressed state, and capture an image of the subject in a fully-pressed state.

The memory 934 is an example of an image storage unit, and can temporarily store an image captured or an image synthesized by the image combining unit 918. The memory 934 may have a storage capacity sufficient to store a plurality of images. Reading and writing of images into the memory 934 can be controlled by the image input controller 914. In addition, data interfaces 1 to 3 according to some embodiments of the present invention may be used for data transmission to the memory 934.

The VRAM 936 holds the contents displayed on the LCD 924, and the resolution and the maximum number of colors of the LCD 924 depend on the capacity of the VRAM 936.

The recording medium 940 is an example of an image recording unit and can record a photographed image. Input/output to the recording medium 940 can be controlled by the media controller 938. As the recording medium 940, a memory card, which is a card-type storage device for recording data into a flash memory, can be used.

The motor drivers 942a, 942b, and 942c can control the driving devices 902a, 904a, 906a that operate the zoom lens 902, the stop 904, and the focus lens 906. By operating the zoom lens 902, the aperture stop 904, and the focus lens 906 using the motor drivers 942a, 942b, and 942c, the size, amount of light, and focus of the subject can be adjusted.

The flash 944 can brightly illuminate a subject when shooting outdoors at night or in a dark place. When flash photography is performed, a light emission command from the CPU 928 is issued to the flash device 944, and the flash 944 is emitted according to the light emission command from the CPU 928, according to the light emitted by the flash 944. The subject can be brightly lit.

15 is a block diagram illustrating an example of applying an imaging device according to embodiments of the present invention to a computing system.

Referring to FIG. 15, the computing system 1000 includes a processor 1010, a memory device 1020, a storage device 1030, an input/output device 1040, a power supply 1050, and an image sensor 1060. can do.

Here, as the image sensor 1060, the image sensor 811 according to embodiments of the present invention described above may be used.

Meanwhile, although not shown in FIG. 14, the computing system 1000 may communicate with a video card, a sound card, a memory card, a USB device, or the like or with other electronic devices. Data interfaces 1 to 3 according to some embodiments of the present invention may be used as such communication means.

The processor 1010 may perform specific calculations or tasks. Here, the processor 1010 may include the image signal processing unit 220 according to the embodiments of the present invention described above. Depending on the embodiment, the processor 1010 may be a micro-processor or a central processing unit (CPU).

The processor 1010 may communicate with the memory device 1020, the storage device 1030, and the input/output device 1040 through an address bus, a control bus, and a data bus. have.

Depending on the embodiment, the processor 1010 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

The memory device 1020 may store data necessary for the operation of the computing system 1000.

For example, the memory device 1020 may be implemented as DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and/or MRAM. The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), and a CD-ROM.

The input/output device 1040 may include an input means such as a keyboard, a keypad, and a mouse, and an output means such as a printer and a display. The power supply 1050 may supply an operating voltage required for the operation of the electronic device 1000.

The image sensor 1060 may be connected to the processor 1010 through buses or other communication links to perform communication. Data interfaces 1 to 3 according to some embodiments of the present invention may be used as such communication means. The image sensor 1060 may be integrated on one chip together with the processor 1010 or may be integrated on different chips.

Here, the computing system 1000 should be interpreted as any computing system using an image sensor. For example, the computing system 1000 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, a tablet PC, and the like.

In addition, in some embodiments of the present invention, the computing system 1000 includes an Ultra Mobile PC (UMPC), a workstation, a net-book, a portable computer, a wireless phone, and a mobile phone. mobile phone), e-book, portable game console, navigation device, black box, 3-dimensional television, digital audio recorder, digital voice A player (digital audio player), a digital picture recorder (digital picture recorder), a digital image player (digital picture player), a digital video recorder (digital video recorder), a digital video player (digital video player) may be included.

16 is a block diagram illustrating an example of an interface used in the computing system of FIG. 15.

Referring to FIG. 16, the computing system 1100 may be implemented as a data processing device capable of using or supporting an MIPI interface, and may include an application processor 1110, an image sensor 1140, a display 1150, and the like. have.

The CSI host 1112 of the application processor 1110 may perform serial communication with the CSI device 1141 of the image sensor 1140 through a camera serial interface (CSI). Data interfaces 1 to 3 according to some embodiments of the present invention may be used as the camera serial interface.

In some embodiments of the present invention, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). The DSI host 1111 of the application processor 1110 may perform serial communication with the DSI device 1151 of the display 1150 through a Display Serial Interface (DSI). Data interfaces 1 to 3 according to some embodiments of the present invention may be used as the display serial interface.

In some embodiments of the present invention, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). Furthermore, the computing system 1100 may further include a Radio Frequency (RF) chip 1160 capable of communicating with the application processor 1110. The PHY 1113 of the computing system 1100 and the PHY 1161 of the RF chip 1160 may perform data transmission/reception according to a Mobile Industry Processor Interface (MIPI) DigRF. In addition, the PHY 1113 of the computing system 1100 and the PHY 1161 of the RF chip 1160 may perform data transmission/reception using the data interfaces 1 to 3 according to some embodiments of the present invention.

In addition, the application processor 1110 may further include a DigRF MASTER 1114 that controls data transmission/reception of the PHY 1161 according to MIPI DigRF. Meanwhile, the computing system 1100 includes a Global Positioning System (GPS) 1120, a storage 1170, a microphone 1180, a dynamic random access memory (DRAM) 1185, and a speaker 1190. I can. In addition, the computing system 1100 uses an Ultra WideBand (UWB) 1210, a Wireless Local Area Network (WLAN) 1220, and a Worldwide Interoperability for Microwave Access (WIMAX) 1230. Communication can be performed. However, the structure and interface of the computing system 1100 are examples, and the present invention is not limited thereto.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those skilled in the art to which the present invention pertains. It will be understood that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting.

11: image sensor 13: image signal processing unit
100: transmitter 200: receiver
300: channel

Claims (10)

Generating a first bit set including a first bit included in the first image data and a third bit included in the second image data,
Generating a second bit set including a second bit included in the first image data and being an upper bit of the first bit, and a fourth bit included in the second image data and being an upper bit of the third bit, ,
A formater having a greater number of transitions in the first bit set than in the second bit set;
A first serializer serializing the first bit set;
A second serializer serializing the second bit set;
A first output driver for converting the serialized first bit set into a first differential signal;
A second output driver for converting the serialized second bit set into a second differential signal; And
A clock generator that generates a plurality of clock signals transmitted to the formatter, the first and second serializers, and the first and second output drivers based on sampling results of at least one of the first and second differential signals Data interface including (clock generator). The method of claim 1,
The first differential signal is transmitted through an HD (High Density) channel,
The second differential signal is a data interface transmitted through a light density (LD) channel. The method of claim 1,
When there is no transition in the first or second bit set received from the formatter, a pre-logic for converting the first or second bit set into a bit set including one or more transitions is further included. Data interface. The method of claim 1,
The first and second image data includes N bits (N is an even number),
The first bit set includes the lower N/2 bits of the first and second image data,
The second bit set includes high order N/2 bits of the first and second image data. The method of claim 1,
The formatter converts the first and second image data into a third bit set,
The third bit set is a fifth bit included in the first image data and positioned between the first bit and the second bit, and a fifth bit included in the second image data and between the third bit and the fourth bit A data interface comprising a sixth bit located at. The method of claim 5,
A third serializer serializing the third bit set,
The data interface further comprising a third output driver for converting the serialized third bit set into a third differential signal. The method of claim 1,
The formatter,
A plurality of toggle counters for counting the number of transitions included in upper and lower bits of the first and second image data;
A comparator for comparing the number of transitions included in the upper bit and the lower bit of the first and second image data,
The plurality of multiplexers for allocating a bit having a large transition among the upper bit and the lower bit to the first bit set, and allocating a bit with a small transition among the upper bit and the lower bit to the second bit set,
A data interface including a dummy bit generator for generating dummy bits indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set. The method of claim 7,
The first bit set and the second bit set further include a first dummy bit and a second dummy bit generated by the dummy bit generator, respectively. A first bit set including a first bit included in the first image data and a third bit included in the second image data is received through a first channel,
A second bit set including a second bit included in the first image data and being an upper bit of the first bit, and a fourth bit included in the second image data and being an upper bit of the third bit, Receive through the channel,
Sampling the first and second bit sets based on a clock signal provided by a clock generator,
The sampling timing of each of the first and second bit sets by adjusting the multi-phase clock signal provided by the clock data recovery circuit (CDR circuit) based on the sampled result of at least one of the first and second bit sets The data transmission method that regulates. The method of claim 9,
Generating a first bit set including a first bit included in the first image data and a third bit included in the second image data,
Generating a second bit set including a second bit included in the first image data and being an upper bit of the first bit, and a fourth bit included in the second image data and being an upper bit of the third bit, ,
Serialize the first bit set and the second bit set,
And converting the serialized first bit set and the second bit set into a first differential signal and a second differential signal.

Images