KR102168822B1 - Display Device - Google Patents

Abstract

In the present invention, in a GIP driving type display device using a clock signal including a dummy clock pulse synchronized with a start signal pulse for stabilization of a gate output signal, the polling timing of the dummy clock pulse is equal to or greater than the polling timing of the start signal. By generating and providing the dummy clock pulse to be faster, it is possible to prevent deterioration of image quality due to a mismatch in the polling timing of the start signal pulse VST and the dummy clock pulse DMY CLK.

Description

Display Device}

The present invention relates to a display device, and more particularly, to a display device having a gate-in-panel (GIP) structure, and a display device capable of stably driving a GIP start unit.

As the information society develops, demands for display devices for displaying images are increasing in various forms, and in recent years, liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting devices Various display devices such as OLED (Organic Light Emitting Diode Display Device) are used.

Among them, the liquid crystal display (LCD) displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal display panel.

A thin film transistor for driving the liquid crystal cell Clc at the intersection of a plurality of gate lines GL and data lines DL in the pixel array of the liquid crystal display panel and the intersection of the gate lines GL and data lines GL (Thin Film Transistor; hereinafter referred to as "TFT") is formed. In addition, a storage capacitor Cst for maintaining the voltage of the liquid crystal cell Clc is formed on the liquid crystal display panel. The liquid crystal cell Clc includes a pixel electrode, a common electrode, and a liquid crystal layer. An electric field is applied to the liquid crystal layers of the liquid crystal cells Clc by the data voltage applied to the pixel electrode and the common voltage Vcom applied to the common electrode. An image is realized by controlling the amount of light passing through the liquid crystal layer by this electric field.

The driving circuit includes a gate driving circuit for sequentially supplying a gate output signal to the gate lines, and a data driving circuit for supplying a video signal (ie, a data voltage) to the data lines. The data driving circuit drives the data lines to supply data voltages to the liquid crystal cells Clc. The gate driving circuit sequentially drives the gate lines to select liquid crystal cells Clc of the display panel to be supplied with the data voltage by one horizontal line.

The gate driving circuit includes a gate shift register composed of a plurality of stages in order to sequentially generate gate signals. Each stage of the shift register alternately performs charging and discharging to output a gate clock signal CLK and a gate output signal Vout composed of a low potential voltage Vss level. Each of the output terminals of the stages are connected one-to-one to the gate lines. The gate signals of the first level from the stages are sequentially generated once per frame and supplied to the corresponding gate line.

On the other hand, the structure in which the gate driving circuit is directly formed on the array substrate is expressed as a gate-in-panel (GIP) structure. In this GIP structure, a number of circuit blocks are used to provide a gate output signal (Vout) to each gate line. The GIP block of is formed directly on the panel.

Meanwhile, one or more start signals (VST) may be applied to each GIP block of such a gate driving circuit together with a plurality of clock signals (CLK), and an initial gate output signal (Vout1) may be stably applied to one of the clock signals. A dummy clock pulse (DMY CLK) to be maintained may be included, and this dummy clock pulse is usually formed of the same pulse as the start signal pulse.

However, since the start signal wiring for applying the start signal is directly input to the gate driving circuit without interference, there is no parasitic capacitance or capacitance, whereas the clock signal wiring for applying the clock signal is a number of overlapping metals such as the entry wiring to the GIP block. A wiring component is formed in the middle to generate a parasitic capacitance or capacitance of a certain size.

Due to the difference in the capacitance component of the start signal wiring and the clock signal wiring, the falling timing of the dummy clock pulse (DMY CLK) formed in the clock signal and the polling timing of the start signal pulse (VST) do not match. , As a result, charge leakage may occur in the driving transistor, resulting in poor image quality.

Against this background, an object of the present invention is to provide a display device having excellent image quality.

Another object of the present invention is to provide a display device capable of preventing deterioration of image quality due to a mismatch in polling timing between a start signal pulse VST and a dummy clock pulse DMY CLK.

Another object of the present invention is to provide a start signal pulse in which the polling start point of the start signal pulse VST is later than the polling start point of the dummy clock pulse DMY CLK, thereby providing a start signal pulse VST and a dummy clock pulse DMY. It is to provide a display device capable of preventing deterioration of image quality due to a mismatch in polling timing of CLK).

Another object of the present invention is to arrange a start signal capacitor Cvst in a part of the entry region of the start signal wiring input from the timing controller onto the array substrate, so that the polling timing of the start signal pulse VST is reduced by the dummy clock pulse DMY CLK. A display device capable of preventing deterioration of image quality due to a mismatch between the polling timing of the start signal pulse VST and the dummy clock pulse DMY CLK by matching the polling timing of) as much as possible.

In order to achieve the above object, a display area including a plurality of pixels defined as an intersection area of a gate line and a data line, and a non-display area in which a gate driver for providing a gate output signal is disposed to each of the gate lines is provided. A driving circuit board including a display panel, a timing controller for generating and outputting a start signal and a clock signal applied to the gate driver, and a data driver generating a driving signal of a data line and providing it to each data line, The first clock signal of the clock signals includes a dummy clock pulse that is synchronized with a start signal pulse, and has a start signal capacitance component in the gate driver connected to the start signal line of the display panel extending from the timing controller. A display device is provided, comprising arranging a signal capacitor element.

By the start signal capacitor element, the polling timing of the start signal pulse is equal to or later than the polling timing of the dummy clock pulse.

The starting signal capacitance component is proportional to a capacitance component generated in a clock wiring that provides the first clock signal arranged on the display panel.

By the start signal capacitor element, the polling start point of the start signal pulse is the same as the polling start point of the dummy clock pulse, but the polling delay amount of the start signal pulse is equal to or greater than the polling delay amount of the dummy clock pulse. It features.

The gate driver includes an odd gate driver and an even gate driver disposed on the left and right sides of the display area, and the first clock signal is a start signal pulse of a third start signal input to the odd gate driver side or input to the even gate driver side. It is characterized in that it is a seventh clock signal or an eighth clock signal including a dummy clock signal synchronized with the start signal pulse of the fourth start signal.

The dummy clock pulse is used to stabilize the gate output signal input to the first gate line.

In addition, a display panel having a display region including a plurality of pixels defined as an intersection region of a gate line and a data line, and a non-display region in which a gate driver for providing a gate output signal is disposed to each of the gate lines, and the data A data driver including a timing module that generates a driving signal of a line and provides it to each data line, and generates a start signal and a clock signal to be applied to the gate driver, and a first clock signal among the clock signals is synchronized with a start signal pulse. A dummy clock pulse, wherein the data driver controls the timing module to generate and output the dummy clock pulse so that a polling start time of the dummy clock pulse is faster than a polling start time of the start signal pulse. It provides a display device.

The difference between the polling start point of the start signal pulse and the polling start point of the dummy clock pulse is equal to or greater than the polling delay amount of the dummy clock pulse.

The gate driver includes an odd gate driver and an even gate driver disposed on the left and right sides of the display area, and the first clock signal is a start signal pulse of a third start signal input to the odd gate driver side or input to the even gate driver side. It is characterized in that it is a seventh clock signal or an eighth clock signal including a dummy clock signal synchronized with the start signal pulse of the fourth start signal.

According to the present invention, there is an effect of preventing deterioration in image quality due to a mismatch in polling timing between the start signal pulse VST and the dummy clock pulse DMY CLK in a GIP display device.

More specifically, in order to stabilize the gate output signal Vout, a dummy clock pulse DMY CLK that is synchronized with the start signal pulse VST is provided to the gate clock. Due to the capacitance generated in the clock signal wiring, the dummy clock pulse A phenomenon in which the polling timing is delayed than the polling timing of the start signal pulse occurs, and thus, charge leakage occurs in one of the thin film transistors T3C.

As a result, image quality may be deteriorated. According to the present invention, a start signal pulse having a polling timing of the start signal pulse equal to or later than that of the dummy clock pulse is generated. It is possible to solve the problem of quality defects caused by the difference in polling timing.

1 and 2 show a liquid crystal display device of a total driving type to which the present invention can be applied, FIG. 1 is a block diagram for each function of the entire display device, and FIG. 2 shows a structure in which gate driving circuits are formed on both sides of the panel. .
3 illustrates an arrangement of signal lines around a gate driving circuit according to an embodiment of the present invention.
4 is a signal timing diagram of the display device of FIG. 3.
5 shows a delay phenomenon of a dummy clock pulse due to a clock wiring capacitance and a charge leakage phenomenon due to the delay.
6 shows a display device according to a first embodiment of the present invention.
Fig. 7 shows a display device according to a second embodiment of the present invention, in which Fig. 7(a) is an enlarged plan view of the display device, and Fig. 7(b) shows signal timings.
Fig. 8 shows a display device according to a third embodiment of the present invention, in which Fig. 8(a) is an enlarged plan view of the display device, and Fig. 8(b) shows signal timing.
9 shows a display device according to a fourth embodiment of the present invention, in which FIG. 8A is an enlarged plan view of the display device, and FIG. 8B shows signal timings.
Fig. 10 shows a display device according to a fifth embodiment of the present invention, in which Fig. 10(a) is an enlarged plan view of the display device, and Fig. 10(b) shows signal timing.
11 is a view for explaining the effect of the second to fifth embodiments of FIGS. 7 to 10.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to elements of each drawing, the same elements may have the same numerals as possible even if they are indicated on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, a detailed description thereof may be omitted.

In addition, in describing the constituent elements of the present invention, terms such as first, second, A, B, (a), (b) may be used. These terms are only for distinguishing the component from other components, and the nature, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected or connected to that other component, but other components between each component It is to be understood that is "interposed", or that each component may be "connected", "coupled" or "connected" through other components.

1 and 2 show a liquid crystal display device of a total driving type to which the present invention can be applied, FIG. 1 is a block diagram for each function of the entire display device, and FIG. 2 shows a structure in which gate driving circuits are formed on both sides of the panel. .

Referring to FIG. 1, a typical liquid crystal display device controls display of a display panel 10 including an active area (AA) in which a plurality of pixels P are formed, and each pixel of the display panel. It may include a system board 20, which is a printed circuit board (PCB) including a driving circuit for this.

The display panel 10 generally includes an array substrate as a lower substrate on which a plurality of gate lines, data lines, and a plurality of thin film transistors are formed, and a color filter substrate as an upper substrate on which a color filter and a black matrix (BM), etc. are formed. It consists of a liquid crystal layer or the like injected into the.

A plurality of pixels defined as an intersection area between the gate line GL and the data line DL are formed on the display panel 10. That is, the data lines D1 to Dm and the gate lines G1 to Gn cross the lower array substrate, and m × n (m,n are positive integers) liquid crystal cells (Clc Pixels of) are formed in a matrix form, and k (k is a positive integer) dummy lines (not shown) may be further formed.

Each of the liquid crystal cells Clc includes a TFT, a pixel electrode 1 connected to the TFT, a storage capacitor Cst, and the like. The liquid crystal cell Clc is driven by a voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied to adjust the transmittance amount of incident light to provide image data. A display image corresponding to (DATA_RGB) is implemented.

Meanwhile, a black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as TN mode and VA mode, and on the lower glass substrate together with the pixel electrode 1 in a horizontal electric field driving method such as IPS mode and FFS mode. Can be formed.

Meanwhile, the gate driving circuit 13 for providing the gate output signal Vout to the gate line is a TFT array process according to a gate-in-panel (GIP) method. It may be formed directly on the lower substrate.

That is, the gate driving circuit 13 is formed in the non-display area (NAA) outside the display area 16 (AA) of the display panel 10, and is symmetrically formed on both left and right (or upper and lower) sides of the panel. It may be, but is not limited thereto.

Meanwhile, the gate driving circuit 13 may include a plurality of GIP blocks or GIP circuit blocks, and each GIP block is connected to each gate line to generate and provide a gate output signal Vouti to a corresponding gate line. In the specification, for convenience, the GIP block connected to the i-th gate line is denoted as “GIP block #i”.

FIG. 1 shows an example in which the gate driving circuit 13 is formed only on one side (left) of the display panel to provide the gate output signal through n gate lines, and in FIG. 2, gate driving circuits are formed on both sides of the display panel. It shows an example.

Among them, the embodiment of FIG. 2 in which gate driving circuits are formed on both sides of the display panel will be described in more detail as follows.

That is, as shown in FIG. 2, the gate driving circuit 13 is a first gate driver 13A for sequentially supplying gate signals to odd gate lines (G1, G3,..., Gn-3, Gn-1). ), and a second gate driver 13B for sequentially supplying a gate signal to the excellent gate lines G2, G4,...,Gn-2,Gn, and each gate driver Each line can include a GIP block.

The first gate driver 13A operates in response to the odd start signals VST1 and VST3 input from the timing controller 11 and the odd clocks CLK1, CLK3, CLK5, and CLK7. The odd clocks CLK1, CLK3, CLK5, and CLK7 may be input to the first gate driver 13A after the level is shifted through a level shifter (not shown) to suit the TFT driving of the liquid crystal cell.

The second gate driver 13B operates in response to the even start signals VST2 and VST4 input from the timing controller 11 and the even clocks CLK2, CLK4, CLK6, and CLK8. The excellent clocks CLK2, CLK4, CLK6, and CLK8 may be input to the second gate driver 13B after the level is shifted through a level shifter (not shown) to suit the TFT driving of the liquid crystal cell.

In addition, in the above-described example, it has been described that each of the gate drivers on one side uses two start signals, but in some cases, only one start signal may be used.

In this specification, the start signal (Start Pulse) will be indicated as VST.

In other words, it was described as a method in which VST1 and VST3 are input to the 1st and 3rd GIP blocks, respectively (the 5th and 7th GIP blocks use the outputs of the 1st and 3rd GIP blocks as a start signal, respectively), , VST1 is input only to the first GIP block (GIP block #1) (the third and lower GIP blocks use the output of the previous GIP block as a start signal).

In addition, when the gate driving circuit is formed only on one side of the display panel as shown in FIG. 1, the gate driving circuit 13 includes GIP blocks from GIP block #1 to GIP block #N, and one start signal VST May be input as the first GIP block (GIP block #1). In this embodiment, CLK1 to CLK8 having a total of 8 phases may be used, and these CLK1 to CLK8 may be sequentially input to the GIP blocks.

On the other hand, the system board 20 may be connected to the display panel 10 through a flexible circuit board (FPCB; 17) or a tape carrier package (TCP), and the system board 20 It may be implemented in the form of a printed circuit board (PCB) including a controller 11 and a data driving circuit 12.

The timing controller 11 may be expressed as a T-Con, and a data control signal for controlling the operation timing of the data driving circuit 12 using timing signals Vsync, Hsync, DE, DCLK input from the outside ( SDC) and a gate control signal (GDC) for controlling the operation timing of the gate driving circuit 13 is generated and provided to each driving circuit.

The data control signal (SDC) supplied from the timing controller 11 to the data driving circuit 12 is a source start signal (Source, Start Pulse, SSP), a source sampling clock (Source Sampling Clock, SSC), and a source output enable signal. (Source Output Enable, SOE), polarity control signal (POL), etc. may be included.

The gate control signal GDC supplied from the timing controller 11 to the gate driving circuit 13 includes at least one start signal VST and at least two clock signals.

In the case of a TFT liquid crystal display device using amorphous silicon as a material for a semiconductor layer, which is an active channel, a clock signal CLK is a pulse having an ON section width of 4 horizontal periods H, and 8 clock signals ( CLK1 ~ CLK8) are used.

Here, the horizontal period or the horizontal section period represented by "H" may be defined as an reciprocal of a value obtained by multiplying the frame frequency and the number of gate lines. For example, if the display panel has a resolution of 1920*1080, the horizontal section (H) period is 1/(60Hz*1080), which is 15.4μs.

Therefore, as described above, 8 clocks having an ON section width of 4 horizontal periods can be generally expressed as 4H 8-phase clocks, and these 8 clocks can be expressed as CLK1 to CLK8.

The data driving circuit 12 may be expressed as a D-IC, and includes a plurality of source drive ICs. Each of the source drive ICs samples and latches digital video data (DATA_RGB) input from the timing controller 11 in response to a data control signal (SDC) from the timing controller 11, and converts the data into parallel data system data, Using this, a data output signal is generated and supplied to the data lines D1 to Dm.

3 illustrates an arrangement of signal lines around a gate driving circuit according to an embodiment of the present invention.

As shown in FIG. 3, a signal input area (SIA) in which various signal wires are formed may be disposed on one side of the gate driving circuit 13, and signal wires included in the signal input part include a start signal (VST) wire. , Clock wiring (CLK1 to CLK8) for clocks.

For reference, FIG. 3 illustrates a type in which the gate driving circuit is formed on both sides of the display area as shown in FIG. 2. In FIG. 3, odd GIP blocks (GIP blocks #1, 3, 5, ... ) Shows the case where it is placed.

Accordingly, as shown in FIG. 3, a start signal (VST1, VST3) wiring 340 and four odd clocks CLK1, CLK3, CLK5, and CLK7 wiring 350 are formed on the left side of the display area.

These start signal wires 340 and clock wires 350 may be formed of the same material as the gate metal material in the process of patterning a gate metal pattern including a gate electrode and a gate line, and may be formed in a direction parallel to the data line. It can extend long over the top and bottom of the panel.

In addition, a clock connection line 352 for connecting each clock line to the corresponding GIP blocks is formed, and the clock connection line 352 is formed of a different layer from the clock line, for example, a source/drain metal layer. , At one end, it is electrically connected to the clock wiring.

At this time, the start signals VST1, VST3, etc. are formed on the outermost side of the signal input unit and are immediately input to the first GIP block (GIP block #1) through the start signal line 340 without interference with other lines. , The clock is input to the corresponding GIP block via the clock line 350 and the clock connection line 352.

However, as shown in the enlarged view of FIG. 3, dielectrics such as a gate insulator (GI) are formed between the upper and lower metal patterns in the crossing regions of each of the clock wirings 350 and the clock connection wirings 352. As a result, C _CLK , which is a parasitic capacitance component, is generated as a result.

Since each clock wiring has to be connected with hundreds to thousands of GIP blocks, the above parasitic capacitance components are continuously accumulated, resulting in a large clock wiring capacitance component.

4 is a signal timing diagram of the display device of FIG. 3.

As shown in FIG. 4, start signals VST1 and VST3 are generated and input to the corresponding GIP block, and odd clock signals CLK1, CLK3, CLK5, and CLK7 may be input to each corresponding GIP block.

At this time, in the 7th clock CLK7, in addition to the clock ON pulse section CLK7 on the right side, a dummy clock pulse DMY CLK7 synchronized with the start signal pulse of VST3 is formed prior to the stabilization of the first gate output signal.

That is, in order to set the reference of the first gate output signal, a dummy clock pulse (DMY CLK) having the same rising timing, pulse width, and falling timing as the start signal pulse that is the On pulse of the start signal VST3. Is formed on one of the clock signals.

In this specification, such a dummy clock pulse is expressed, and the dummy clock pulse is a VST3 pulse, which is a third start signal in a method in which the gate driver is divided into left and right (odd/excellent) and a method in which two start signals are used as shown in FIG. Synchronized with and can be formed in CLK7. (See Fig. 4(a))

Further, although not shown, in the even gate driving circuit area on the right side of the display area, the dummy clock pulse may be synchronized with the fourth start signal VST4 to be formed in the eighth clock CLK8.

On the other hand, as shown in (b) of FIG. 4, in a method in which the gate driver is disposed on one side of the display area and only one start signal is used, the dummy clock pulse may be synchronized with VST and formed on the fourth clock CLK4. .

As such, the "dummy clock pulse" as defined in the present specification means a dummy pulse formed in one of the clock signals to be synchronized with the start signal pulse to stabilize the gate output.

Such a dummy clock pulse (DMY CLK) is theoretically in the same pulse form as the corresponding start signal (VST) pulse, that is, the same rising timing, pulse width, and falling timing as the start signal pulse. Can have

5 shows a delay phenomenon of a dummy clock pulse due to a clock wiring capacitance and a charge leakage phenomenon due to the delay.

As described above with respect to FIG. 3, while parasitic capacitance components hardly occur in the start signal wiring, a significant amount of clock wiring capacitance (C _CLK ) components are generated in the clock wiring.

Accordingly, the start signal pulse may maintain a rectangular pulse shape, but a polling delay phenomenon of the pulse due to the clock wiring capacitance (C _CLK ) component occurs in the dummy clock pulse to be synchronized therewith.

That is, as shown in (a) of FIG. 5, when the dummy clock pulse DMY CLK7 generated and provided in the same form as the start signal pulse VST3 is actually input to the GIP block, a delay equal to the delay time d is It will happen.

As shown in (a) of FIG. 5, the start signal pulse VST3 drops to OFF immediately at the polling start time t0, but the dummy clock pulse DMY CLK7 to be synchronized therewith is delayed by a delay time d, t0 at the polling start time t0. Polling is completely completed at point +d.

At this time, in the T3C transistor, which is one of the transistors that drive the pixel, the Q-node on the source side is in a high state where electric charges are charged, a dummy clock pulse (DMY CLK) is applied to the gate, and a start signal is applied to the drain side. Pulse VST3 is applied.

In this state, theoretically, the start signal pulse VST3 on the drain side and the dummy clock pulse DMY CLK on the gate side should fall at the same time.

However, in reality, as shown in Fig. 5A, during the delay time d of the polling timing of the dummy clock pulse DMY CLK generated due to the clock wiring capacitance, the start signal pulse VST3, which is the drain side, falls to LOW, The dummy clock pulse DMY CLK, which is the gate side, maintains a constant voltage, and as a result, a channel between the source and the drain is opened.

Therefore, during this delay time, a phenomenon in which the charge in the Q-node flows to the drain side and leaks occurs.

That is, as shown in (c) of FIG. 5, charge leakage occurs in which the Q-node voltage decreases by a certain degree during the delay time d, and accordingly, the waveform of the corresponding gate output signal Vout1 is also an abnormal waveform delayed for a certain time Fd. Occurs.

Accordingly, a polling delay phenomenon of the gate output signal Vout occurs, and as a result, a phenomenon in which the corresponding pixel becomes dark occurs.

In particular, in the Z-Inversion type GIP panel, the data output signal and the gate output signal (Vout) are mismatched, causing two pixels to be turned on at the same time. Only pixels may appear dark.

In addition, when a high temperature of 60 degrees Celsius or higher or when the load of the signal wiring is increased, the discrepancy between the data output signal and the gate output signal Vout may become deeper, leading to a decisive adverse effect on image quality.

This phenomenon may be expressed as an abnormal driving of the GIP start unit.

Meanwhile, a display panel of a simple logic circuit (SLC) in which each GIP block is composed of 7 or less transistors has been developed for a small display such as a mobile device.

This SLC GIP method can be usefully used for a narrow bezel.In small display panels such as mobile phones, the signal wiring is not large and therefore the clock wiring capacitance is not large, so the GIP start unit abnormal driving phenomenon as described above. This doesn't happen much.

However, when the size of the display panel increases, such as a tablet PC, the load of the signal wiring and the corresponding parasitic capacitance also increase, and thus the abnormal driving phenomenon of the GIP start unit as described above may be a major cause of poor image quality.

In order to solve this problem, in an embodiment of the present invention, in the display device of the GIP driving type using a clock signal including a dummy clock pulse synchronized with a start signal pulse for stabilization of a gate output signal, the polling timing of the start signal is It is characterized in that the start signal is generated to be equal to or later than the polling timing of the dummy clock pulse and provided to the gate driver.

As a specific embodiment, in a so-called TMIC (Timing Module In Chip) display device in which a timing module that generates and provides a start signal and a clock signal is included in a data driver or a data driving circuit (D-IC), Since the circuit unit can arbitrarily generate the start signal pulse waveform, the start signal can be generated and provided so that the pulse width of the start signal is larger than the dummy clock pulse. That is, in the TMIC type embodiment, the start signal pulse is generated and provided so that the polling start time of the start signal is later than the start time of the dummy clock pulse.

In addition, in another embodiment, since it is difficult to adjust the waveform of the start signal in a display device having a timing controller directly provided to a display panel that generates and provides a start signal and a clock signal, the timing controller included in the driving circuit unit A start signal capacitor element having a predetermined capacitance component may be circuitly arranged in the middle of the extended start signal connection wiring.

In this embodiment, the waveform of the start signal is left as it is, but by placing an electrical capacitor element proportional to the parasitic capacitance of the corresponding clock signal line in the middle of the start signal connection wiring, the delay corresponding to the dummy clock pulse is intentionally prevented even in the start signal pulse. To create.

Hereinafter, various embodiments of the present invention will be described with reference to FIGS. 6 to 11.

<First Example>

6 shows a display device according to a first embodiment of the present invention.

The display device of FIG. 6 largely includes a driving circuit unit 620 connected to the display panel through a display panel 610 and a flexible circuit board (FPCB) to drive the display panel, and a first clock signal among clock signals May include a dummy clock pulse synchronized with the start signal pulse, and the driving circuit unit may generate and output the start signal so that the polling timing of the dummy clock pulse is equal to or later than the polling timing of the start signal.

In more detail, first, the display panel includes a display area 611 including a plurality of pixels P defined as an intersection area of a gate line GL and a data line DL, and a gate output signal to each of the gate lines. A non-display area in which the gate driver 613 for providing is formed is formed.

In addition, the driving circuit unit 620 is connected and mounted on the display panel through a flexible circuit board (FPCB) or a tape carrier package (TCP), and the polling timing of the dummy clock pulse is the same as the polling timing of the start signal. Or generating and outputting the start signal to be delayed.

On the other hand, the driving circuit unit 620 generates a GIP pulse such as a clock signal and provides a timing controller for providing various signal wiring of the display panel separately from the data driving circuit (D-IC). A timing module (TM) to be generated may be implemented in a second manner inside the data driving circuit chip.

In this case, in the first method, the data driving circuit (D-IC) can be arbitrarily optimized by the user through a software method, but it is difficult to arbitrarily change the GIP pulse generated and output by the timing controller.

Therefore, in the first method, the start signal pulse VST generated by the timing controller is left as it is, but by deliberately delaying the start signal pulse input to the gate driver by arranging a separate start signal capacitor element in a certain part of the driving circuit part. , Controlling so that the polling timing of the start signal pulse is the same as or later than that of the dummy clock pulse.

Meanwhile, the second method in which the timing module (TM) is inside the data driving circuit chip may be expressed as TMIC (Timing Module In Chip), and a timing module that generates GIP pulses inside the data driving circuit chip is included. Therefore, the shape of the start signal pulse can be arbitrarily adjusted by controlling the timing module.

Accordingly, in the second method, the data driver controls the timing module to generate the start signal pulse so that the polling start time of the dummy clock pulse is later than the polling start time of the start signal pulse.

Hereinafter, embodiments according to the first method and the second method will be described in more detail with reference to FIGS. 7 to 10, respectively.

<Second Example>

Fig. 7 shows a display device according to a second embodiment of the present invention, in which Fig. 7(a) is an enlarged plan view of the display device, and Fig. 7(b) shows signal timings.

The second embodiment of FIG. 7 corresponds to the above-described first method, and is a case where a timing controller for generating various signal pulses is formed separately from a data driver or a data driver circuit.

The display device according to the second embodiment of FIG. 7 is composed of a display panel 710 and a driving circuit part 720, and the driving circuit part 720 is mounted on the display panel through a flexible circuit board (FPCB) 760, etc. It functions to provide various signals (gate control signals, etc.) to the gate driver 713 of the panel and to provide data output signals to the data lines.

More specifically, the display panel 710 includes a display region 711 including a plurality of pixels P defined as an intersection region of a gate line GL and a data line DL, and a gate output signal to each of the gate lines. It includes a non-display area in which the gate driver 713 for providing is formed.

The driving circuit part 720 generates a timing controller 722 for generating and outputting various gate control signals applied to the gate driver, for example, a start signal VST and a clock signal CLK, and a data line driving signal. And a data driver 724 (D-IC) provided to each data line.

The driving circuit unit 720 may be implemented in the form of a printed circuit board (PCB) including various electrical elements in hardware.

In addition, in the display device of FIG. 7, a specific first clock signal among several clock signals provided to the gate driver may include a dummy clock pulse DMY CLK synchronized with a start signal pulse.

In this case, if the gate driver is formed only on one side of the display area and one start signal is used, the first clock signal may be CLK4, which is the fourth clock among the eight clocks CLK1 to 8.

In addition, when the gate driver includes an odd gate driver and an even gate driver disposed on the left and right of the display area, the first clock signal is synchronized with the start signal pulse VST3 of the third start signal input to the odd gate driver side. The dummy clock signal DMY CLK8 becomes a seventh clock signal CLK7 including the dummy clock signal DMY CLK7, or is synchronized with the start signal pulse VST4 of the fourth start signal input to the even gate driver side. It may be the included eighth clock signal CLK8.

These dummy clock pulses are used to stabilize the gate output signal input to the first gate line. In the case of a dummy clock pulse synchronized with the first start signal (VST or VST1) or the third start signal (VST3), the first In the case of a dummy clock pulse that is used to stabilize the gate output signal Vout1 and is synchronized with the fourth start signal VST4, it may be used to stabilize the second gate output signal Vout2.

On the other hand, a start signal connection line 730' extending from the timing controller 722 and connected to the start signal line 730 of the display panel is formed, and an electrical element in a part of the start signal connection line 730' The start signal capacitor element 735 as C _VST is disposed.

The start signal capacitor element 735 is a capacitor having a constant capacitance value, and the capacitance value may be expressed as a start signal capacitance component.

The start signal capacitance component may have a value proportional to the clock wiring capacitance component C _CLK generated in relation to the first clock signal formed on the display panel 710.

That is, a capacitor element having a capacitance value corresponding to the clock wiring capacitance component, which is a parasitic capacitance generated from the clock signal wiring including the dummy clock pulse, is placed on the start signal connection wiring 730', thereby being generated by the timing controller 722. The delayed start signal pulse is deliberately delayed, resulting in a polling timing equal to or later than the dummy clock pulse.

7B shows timings of a start signal pulse VST and a dummy clock pulse DMY CLK input to the gate driver 713 when the start signal capacitor element 735 C _VST is used.

In the second embodiment of FIG. 7, the start signal pulse VST input to the gate driver is the same as the polling start point Fst0 of the dummy clock pulse DMY CLK, and d'during the polling of the start signal. There is a delay of as much.

The polling delay amount d'of the start signal pulse may be equal to or greater than the polling delay amount d of the dummy clock pulse.

That is, by arranging the start signal capacitor element 735 on the start signal connection line 730', the polling timing of the start signal pulse output from the timing controller 722 is deliberately delayed so as to be equal to the polling timing of the dummy clock pulse. By making it later, the charge leakage phenomenon described above and the resulting image quality defect are prevented.

As described above, in the second embodiment of FIG. 7, it is possible to appropriately control the polling timing of the start signal pulse input to the gate driver only by the circuit design of the driving circuit unit 720 without changing the structure of the timing controller 722.

<Third Example>

Fig. 8 shows a display device according to a third embodiment of the present invention, in which Fig. 8(a) is an enlarged plan view of the display device, and Fig. 8(b) shows signal timing.

The third embodiment of FIG. 8 corresponds to the second method described above, and is a case in which a timing module for generating various signal pulses is formed in a chip of a data driver or a data driver circuit (D-IC).

The display device according to the third embodiment of FIG. 8 is composed of a display panel 810 and a driving circuit unit 820 as in the second embodiment of FIG. 7, and the driving circuit unit 820 is a flexible circuit board (FPCB) 860. ) Is mounted on the display panel, provides various signals (gate control signals, etc.) to the gate driver 813 of the display panel and provides a data output signal to a data line.

The structure of the display panel 810 is the same as that of the second embodiment of FIG. 7, and detailed descriptions are omitted to avoid redundancy.

The driving circuit unit 820 according to the third embodiment of FIG. 8 is a timing module 824 for generating and outputting various gate control signals applied to the gate driving unit, for example, a start signal VST and a clock signal CLK. ') includes a single-chip data driver 824 (D-IC).

The driving circuit unit 820 of FIG. 8 may be implemented in the form of a printed circuit board (PCB) including various electrical elements in hardware.

On the other hand, similar to the second embodiment of FIG. 7, in the third embodiment of FIG. 8, the first clock signal of several clock signals includes a dummy clock pulse synchronized with the start signal pulse, and the dummy clock pulse and the start signal pulse The configuration of is the same as that of the second embodiment of FIG. 7, so a detailed description is omitted.

The data driver 824 (D-IC) according to the third embodiment of FIG. 8 is a so-called TMIC type in which a timing module 824 is built-in. The timing module 824' is software-controlled to generate various signal pulses. Waveform (pulse width) can be arbitrarily adjusted.

Accordingly, in the third embodiment of FIG. 8, the data driver 824 controls the timing module 824' to generate the start signal pulse so that the polling start time of the start signal pulse is later than the polling start time of the dummy clock pulse. The output clock signal CLK and the start signal VST are respectively input to the gate driver 813 through the clock signal line 840 and the start signal line 830 of the display panel.

The start signal pulse VST in the third embodiment of FIG. 8 has a waveform in which the polling start point Fst1 is later than the polling start point Fst0 of the dummy clock pulse DMY CLK, as shown in FIG. 8B. In this case, a difference between the polling start point Fst1 of the start signal pulse and the polling start point Fst0 of the dummy clock pulse may be expressed as a deviation amount d" at the polling start point.

That is, the pulse width of the start signal pulse is greater than the dummy clock pulse by the amount of deviation d" at the start time of polling.

In this case, it is preferable that the amount of deviation d" at the starting point of polling is equal to or greater than the amount d of the polling delay of the dummy clock signal generated in the dummy clock signal by the clock signal capacitance component.

As described above, in the third embodiment of Fig. 8, when the timing module is built into the data driving circuit (D-IC) and various GIP pulse waveforms can be arbitrarily adjusted, the polling start point of the start signal pulse is determined by the dummy clock pulse. The pulse waveform (pulse width) of the start signal pulse is adjusted to be larger than the polling delay amount.

<Fourth Example>

Fig. 9 shows a display device according to a fourth embodiment of the present invention, in which Fig. 9(a) is an enlarged plan view of the display device, and Fig. 9(b) shows signal timing.

The fourth embodiment of FIG. 9 corresponds to the first method described above, and is a case in which a timing controller for generating various signal pulses is formed separately from a data driver or a data driver circuit.

The display device according to the fourth embodiment of FIG. 9 includes a display panel 910 and a driving circuit unit 920, and the driving circuit unit 920 is a gate driving unit 913 of the display panel 910 to provide various signals (gate control). Signal, etc.) and a data output signal to the data line.

More specifically, the display panel 910 includes a display area 911 including a plurality of pixels P defined as an intersection area of a gate line GL and a data line DL, and a gate output signal to each of the gate lines. It includes a non-display area in which the gate driver 913 for providing is formed.

The driving circuit unit 920 generates a timing controller 922 for generating and outputting various gate control signals applied to the gate driver, for example, a start signal VST and a clock signal CLK, and a data line driving signal. Thus, it includes a data driver 924 (D-IC) provided to each data line.

The driving circuit unit 920 may be implemented in the form of a printed circuit board (PCB) including various electrical elements in hardware.

In addition, in the display device of FIG. 9, a specific first clock signal among several clock signals provided to the gate driver 913 may include a dummy clock pulse DMY CLK synchronized with a start signal pulse.

In this case, if the gate driver is formed only on one side of the display area and one start signal is used, the first clock signal may be CLK4, which is the fourth clock among the eight clocks CLK1 to 8.

In addition, when the gate driver includes an odd gate driver and an even gate driver disposed on the left and right of the display area, the first clock signal is synchronized with the start signal pulse VST3 of the third start signal input to the odd gate driver side. The dummy clock signal DMY CLK8 becomes a seventh clock signal CLK7 including the dummy clock signal DMY CLK7, or is synchronized with the start signal pulse VST4 of the fourth start signal input to the even gate driver side. It may be the included eighth clock signal CLK8.

These dummy clock pulses are used to stabilize the gate output signal input to the first gate line. In the case of a dummy clock pulse synchronized with the first start signal (VST or VST1) or the third start signal (VST3), the first In the case of a dummy clock pulse that is used to stabilize the gate output signal Vout1 and is synchronized with the fourth start signal VST4, it may be used to stabilize the second gate output signal Vout2.

Meanwhile, a start signal line 930 of the display panel connected to the start signal connection line 930' extended from the timing controller 922 is formed, and the start signal line 930 is connected to the gate driver 913 A start signal VST is applied to the gate driver 913.

A start signal capacitor element 935 as an electrical element C _VST is disposed on a part of the gate driver 913 connected to the start signal line 930.

The start signal capacitor element 935 is a capacitor having a constant capacitance value, and the capacitance value may be expressed as a start signal capacitance component.

The start signal capacitance component may have a value proportional to the clock wiring capacitance component C _CLK generated in relation to the first clock signal formed on the display panel 910.

That is, by disposing a capacitor element having a capacitance value corresponding to a clock wiring capacitance component, which is a parasitic capacitance generated from a clock signal wiring including a dummy clock pulse, in the gate driver 913 connected to the start signal wiring 930, the timing controller The start signal pulse generated at (922) is intentionally delayed so as to have a polling timing equal to or later than that of the dummy clock pulse.

In the second embodiment of FIG. 7, in order to arrange the start signal capacitor element 735 C _VST on a part of the start signal connection line 730', a capacitor element 735 must be separately formed on the printed circuit board (PCB). , In the fourth embodiment of FIG. 9, in order to place the start signal capacitor element 935 C _VST on a part of the gate driver 913 connected to the start signal line 930, the thin film transistor of the gate driver 913 is patterned. When the capacitor element 935 can be additionally formed, the capacitor can be formed more easily than the second embodiment of FIG. 7, and manufacturing cost can be reduced.

9B shows timings of the start signal pulse VST and the dummy clock pulse DMY CLK input to the gate driver 913 when the start signal capacitor element 935 C _VST is used.

In the fourth embodiment of FIG. 9, the start signal pulse VST input to the gate driver is the same as the polling start point Fst0 of the dummy clock pulse DMY CLK, and d'during the polling of the start signal. There is a delay of as much.

The polling delay amount d'of the start signal pulse may be equal to or greater than the polling delay amount d of the dummy clock pulse.

That is, by arranging the start signal capacitor element 935 C _VST in a part of the gate driver 913 connected to the start signal wiring 930, the polling timing of the start signal pulse output from the timing controller 922 is intentionally delayed. By setting the dummy clock pulse polling timing to be equal to or later than that, the charge leakage phenomenon described above and the resulting image quality defect are prevented.

As described above, in the fourth embodiment of FIG. 9, it is possible to properly control the polling timing of the start signal pulse input to the gate driver 913 by only the circuit design of the gate driver 913 without changing the structure of the timing controller 922. I can.

<Fifth Example>

The fifth embodiment of FIG. 10 corresponds to the above-described second method, and is a case in which a timing module for generating various signal pulses is formed in a chip of a data driver or a data driver circuit (D-IC).

The display device according to the fifth embodiment of FIG. 10 includes a display panel 1010 and a driving circuit unit 1020 as in the second embodiment of FIG. 7, and the driving circuit unit 1020 is a flexible circuit board (FPCB) 1060. ) Is mounted on the display panel, provides various signals (gate control signals, etc.) to the gate driver 1013 of the display panel and provides a data output signal to a data line.

The structure of the display panel 1010 is the same as that of the second embodiment of FIG. 7, and detailed descriptions are omitted to avoid redundancy.

The driving circuit unit 1020 according to the fifth embodiment of FIG. 10 is a timing module 1024 for generating and outputting various gate control signals applied to the gate driving unit, for example, a start signal VST and a clock signal CLK. It includes a single-chip data driver 1024 (D-IC) with built-in').

The driving circuit unit 1020 of FIG. 10 may be implemented in the form of a printed circuit board (PCB) including various electrical elements in hardware.

Meanwhile, as in the second embodiment of FIG. 7, in the fifth embodiment of FIG. 10, the first clock signal among several clock signals includes a dummy clock pulse synchronized with the start signal pulse, and the dummy clock pulse and the start signal pulse The configuration of is the same as that of the second embodiment of FIG. 7, so a detailed description thereof will be omitted.

The data driver 1024 (D-IC) according to the fifth embodiment of FIG. 10 is a so-called TMIC type in which the timing module 1024 is built in. The timing module 1024' is software-controlled to generate various signal pulses. Waveform (pulse width) can be arbitrarily adjusted.

Therefore, in the fifth embodiment of FIG. 10, the data driver 1024 controls the timing module 1024', so that the dummy clock signal pulse is delayed so that the polling start time of the dummy clock signal pulse is later than the polling start time of the start signal pulse. Is generated and output, and the output clock signal CLK and start signal VST are input to the gate driver 1013 through the clock signal line 1040 and the start signal line 1030 of the display panel, respectively.

The start signal pulse VST in the fifth embodiment of FIG. 10 is a waveform in which the polling start point Fst'1 is later than the polling start point Fst'0 of the dummy clock pulse DMY CLK, as shown in FIG. 10B. Has. In this case, a difference between the polling start point Fst'1 of the start signal pulse and the polling start point Fst'0 of the dummy clock pulse may be expressed as a deviation amount dx at the polling start point.

That is, the dummy clock pulse has a pulse width smaller than the start signal pulse by the amount of deviation dx at the start of polling.

In this case, it is preferable that the amount of deviation dx at the starting point of polling is equal to or greater than the amount of polling delay d of the dummy clock signal generated in the dummy clock signal due to the clock signal capacitance component.

As described above, in the fifth embodiment of FIG. 10, when the timing module is built into the data driving circuit (D-IC) and various GIP pulse waveforms can be arbitrarily adjusted, the polling start point of the dummy clock pulse and the start signal polling start. The pulse waveform (pulse width) of the dummy clock signal pulse is adjusted so that the difference between the viewpoints is greater than the polling delay amount of the dummy clock pulse.

11 is a view for explaining the effect of the second to fifth embodiments of FIGS. 7 to 10.

Figure 11 (a) corresponds to the second and fourth embodiments of FIGS. 7 and 9, where the solid line is the gate output signal waveform when the start signal capacitor elements 735 and 935 are used, and the broken line is the start. The waveform of the gate output signal when the signal capacitor element C _VST is not used is shown.

That is, when the start signal capacitor element C _VST is not used, as described above, the dummy clock pulse delays the polling timing by the parasitic capacitor element C _CLK generated in the clock wiring, whereas the start signal pulse does not delay. As a result, charge leakage occurs during the delay time of the polling timing, and as a result, the gate output signal waveform Vout also has an abnormal shape as indicated by a broken line in FIG. 11A.

On the other hand, when the start signal capacitor element C _VST is used, the polling timing of the start signal pulse is the same as or later than the polling timing of the dummy clock pulse, so that the aforementioned charge leakage phenomenon does not occur, and the gate output signal waveform is also normal. Maintain shape. (A solid line portion of Fig. 11A)

Therefore, it is possible to solve the problem of image quality defects caused by abnormal driving of the GIP start unit.

11B and 11C correspond to the third and fifth embodiments of FIGS. 8 and 10, respectively, and the solid line is the waveform of the start signal pulse (pulse width) by the data driving circuit (D-IC). ) So that the polling start point of the start signal pulse is formed later than the polling delay point of the dummy clock pulse, or by changing the waveform (pulse width) of the dummy clock pulse, the polling point of the dummy clock signal pulse is It is the gate output signal waveform when it is formed later than the polling delay time point, and the broken line shows the gate output signal waveform when the start signal pulse waveform and the dummy clock signal pulse waveform are not changed.

That is, if the polling start point of the start signal pulse or the polling point of the dummy clock signal pulse is not delayed, the polling timing of the dummy clock pulse is delayed by the parasitic capacitor component C _CLK generated in the clock wiring, whereas the polling timing of the start signal pulse is delayed. There is no delay, and accordingly, charge leakage occurs during the delay time of the polling timing, and as a result, the gate output signal waveform Vout also has an abnormal shape as indicated by broken lines in FIGS. 11B and 11C. .

Meanwhile, the pulse width of the start signal pulse is changed so that the polling start time of the start signal pulse is formed later than the polling delay time of the dummy clock pulse, or the polling start time and the polling delay amount of the dummy clock pulse are greater than the polling time of the start signal pulse. If the pulse width of the dummy clock signal pulse is changed to be formed first, the polling timing of the start signal pulse is the same as or later than the polling timing of the dummy clock pulse, so that the above-described charge leakage phenomenon does not occur, and accordingly, the gate output signal waveform It also maintains its normal shape. (Parts of solid lines in Figs.

Therefore, it is possible to solve the problem of image quality defects caused by abnormal driving of the GIP start unit.

As described above, in a GIP-driven display device using a clock signal including a dummy clock pulse synchronized with a start signal pulse to stabilize the gate output signal, the polling timing of the start signal is the same as the polling timing of the dummy clock pulse. By generating and providing the start signal later than that, it is possible to prevent deterioration of image quality due to a mismatch in the polling timing of the start signal pulse VST and the dummy clock pulse DMY CLK.

In addition, by arranging a start signal capacitor (Cvst) element in the middle of the start signal connection wiring input from the timing controller to the array substrate, or by placing a start signal capacitor element C _VST on a part of the gate driver connected to the start signal wiring, the start signal By matching the polling timing of the pulse (VST) as much as possible with the polling timing of the dummy clock pulse (DMY CLK), it is possible to prevent degradation of image quality due to the inconsistency of the polling timing of the start signal pulse (VST) and the dummy clock pulse (DMY CLK). There is an effect.

The description above and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the technical field to which the present invention pertains, combinations of configurations without departing from the essential characteristics of the present invention Various modifications and variations, such as separation, substitution, and alteration, will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

610, 710, 810: display panel 611, 711, 811: display area
613, 713, 813: gate driving unit (GIP) 620, 720, 820: driving circuit unit (PCB)
722: timing controller 724, 824: date composition circuit (D-IC)
730: start signal wiring 730': start signal connection wiring
735: start signal capacitor (Cvst) 824': timing module

Claims (9)

A display panel having a display area including a plurality of pixels defined as an intersection area of a gate line and a data line, and a non-display area in which a gate driver for providing a gate output signal is disposed on each of the gate lines;
And a driving circuit board including a timing controller for generating and outputting a start signal and a clock signal applied to the gate driver, and a data driver generating a driving signal of a data line and providing it to each data line,
A first clock signal of the clock signals includes a dummy clock pulse synchronized with a start signal pulse,
And a start signal capacitor element having a start signal capacitance component is disposed in the gate driver connected to the start signal line of the display panel extending from the timing controller.
The method of claim 1,
And a polling timing of the start signal pulse is equal to or later than that of the dummy clock pulse by the start signal capacitor element.
The method of claim 2,
And the start signal capacitance component is proportional to a capacitance component generated in a clock wiring providing the first clock signal disposed on the display panel.
The method of claim 2,
By the start signal capacitor element, the polling start point of the start signal pulse is the same as the polling start point of the dummy clock pulse, but the polling delay amount of the start signal pulse is equal to or greater than the polling delay amount of the dummy clock pulse. A display device, characterized in that.
The method of claim 1,
The gate driver includes an odd-numbered gate driver and an even-numbered gate driver disposed on the left and right sides of the display area,
The first clock signal is a seventh clock signal including a start signal pulse of a third start signal input to an odd gate driver side or a dummy clock signal synchronized with a start signal pulse of a fourth start signal input to an even gate driver side Or an eighth clock signal.
The method of claim 1,
The dummy clock pulse is used to stabilize a gate output signal input to an initial gate line.
A display panel having a display area including a plurality of pixels defined as an intersection area of a gate line and a data line, and a non-display area in which a gate driver for providing a gate output signal is disposed on each of the gate lines;
A data driver including a timing module generating a driving signal of the data line and providing it to each data line, the timing module generating a start signal and a clock signal to be applied to the gate driver;
A first clock signal of the clock signals includes a dummy clock pulse synchronized with a start signal pulse,
And the data driver controls the timing module to generate and output the dummy clock pulse so that a polling start point of the dummy clock pulse is earlier than a polling start point of the start signal pulse.
The method of claim 7,
The display device according to claim 1, wherein the difference between the polling start point of the start signal pulse and the polling start point of the dummy clock pulse is equal to or greater than the polling delay amount of the dummy clock pulse.
The method of claim 7,
The gate driver includes an odd-numbered gate driver and an even-numbered gate driver disposed on the left and right sides of the display area,
The first clock signal is a seventh clock signal including a start signal pulse of a third start signal input to an odd gate driver side or a dummy clock signal synchronized with a start signal pulse of a fourth start signal input to an even gate driver side Or an eighth clock signal.

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