KR102166126B1 - Chip antenna module and electronic device including thereof - Google Patents

Abstract

According to one embodiment of the present invention, provided is a chip antenna module, which comprises: a first dielectric layer; a solder layer disposed on a lower surface of the first dielectric layer; a first patch antenna pattern disposed on an upper surface of the first dielectric layer and having a through hole; a second patch antenna pattern spaced apart from the top of the first patch antenna pattern and smaller than the first patch antenna pattern; a first feed via disposed to penetrate the first dielectric layer from the lower surface of the first dielectric layer and electrically connected to the first patch antenna pattern; a second feed via disposed from the lower surface of the first dielectric layer to penetrate the first dielectric layer and the through hole of the first patch antenna pattern and electrically connected to the second patch antenna pattern; and a plurality of shielding vias disposed from the lower surface of the first dielectric layer to penetrate the first dielectric layer, electrically connected to the first patch antenna pattern, and arranged to surround the second feed via.

Description

Chip antenna module and electronic device including the same

The present invention relates to a chip antenna module and an electronic device including the same.

The data traffic of mobile communication is increasing rapidly every year. Active technology development is underway to support such breakthrough data in real time in wireless networks. For example, contentization of IoT (Internet of Thing)-based data, AR (Augmented Reality), VR (Virtual Reality), live VR/AR combined with SNS, autonomous driving, Sync View, user's viewpoint using micro camera Applications such as real-time video transmission) require communication (e.g., 5G communication, mmWave communication, etc.) that supports sending and receiving large amounts of data.

Therefore, recently, millimeter wave (mmWave) communication including fifth generation (5G) communication has been actively researched, and research for commercialization/standardization of a chip antenna module that smoothly implements this is also actively being conducted.

Since RF signals in high frequency bands (eg, 24GHz, 28GHz, 36GHz, 39GHz, 60GHz, etc.) are easily absorbed and lead to loss in the process of being transmitted, the quality of communication can drop rapidly. Therefore, the antenna for high frequency band communication requires a different technical approach from the existing antenna technology, and separates for securing antenna gain, integration of antenna and RFIC, and securing Effective Isotropic Radiated Power (EIRP). Special technology development such as power amplifier may be required.

Registered Patent Publication No. 10-1572037

The present invention provides a chip antenna module capable of improving antenna performance or being easily miniaturized while providing transmission/reception means for a plurality of different frequency bands, and an electronic device including the same.

A chip antenna module according to an embodiment of the present invention includes: a first dielectric layer; A solder layer disposed on a lower surface of the first dielectric layer; A first patch antenna pattern disposed on an upper surface of the first dielectric layer and having a through hole; A second patch antenna pattern that is disposed above the first patch antenna pattern and is smaller than the first patch antenna pattern; A first feed via disposed to pass through the first dielectric layer from a lower surface of the first dielectric layer and electrically connected to the first patch antenna pattern; A second feed via disposed from a lower surface of the first dielectric layer to penetrate the through hole of the first dielectric layer and the first patch antenna pattern, and electrically connected to the second patch antenna pattern; And a plurality of shielding vias disposed from a lower surface of the first dielectric layer to pass through the first dielectric layer, electrically connected to the first patch antenna pattern, and arranged to surround the second feed via. Includes.

An electronic device according to an embodiment of the present invention, the chip antenna module; A connection member providing an upper surface to which the solder layer of the chip antenna module is electrically connected; And an IC electrically connected to a lower surface of the connection member. Includes.

The chip antenna module and the electronic device including the same according to an embodiment of the present invention, while providing transmission and reception means for a plurality of different frequency bands, antenna performance (eg, gain, bandwidth, directivity, transmission/reception rate, etc.) Can be improved or easily downsized.

1A and 1B are side views illustrating a chip antenna module according to an embodiment of the present invention.
2A and 2B are perspective views illustrating a chip antenna module according to an embodiment of the present invention.
3 is a perspective view illustrating a shielding via disposed in a chip antenna module according to an embodiment of the present invention.
4 is a plan view illustrating various types of solder layers 140a of a chip antenna module according to an embodiment of the present invention.
5A is a perspective view illustrating an arrangement of a plurality of chip antenna modules according to an embodiment of the present invention.
5B is a perspective view showing an integrated chip antenna module in which a plurality of chip antenna modules of FIG. 5A are integrated.
6A is a plan view illustrating an endfire antenna included in a connection member disposed under a chip antenna module according to an embodiment of the present invention.
6B is a plan view illustrating an endfire antenna disposed on a connection member disposed under a chip antenna module according to an embodiment of the present invention.
7A to 7C are diagrams illustrating a method of manufacturing a chip antenna module according to an embodiment of the present invention.
7D is a diagram illustrating a process of forming an arrangement space of a patch antenna pattern in a dielectric layer of a chip antenna module according to an embodiment of the present invention.
8A is a plan view illustrating a first ground plane of a connecting member included in an electronic device according to an exemplary embodiment.
8B is a plan view illustrating a feed line below the first ground plane of FIG. 8A.
8C is a plan view illustrating a wiring via and a second ground plane below the feed line of FIG. 8B.
FIG. 8D is a plan view illustrating an IC arrangement area and an endfire antenna under the second ground plane of FIG. 8C.
9A to 9B are side views illustrating a portion shown in FIGS. 8A to 8D and a structure of a lower side thereof.
10A and 10B are plan views illustrating an electronic device including a chip antenna module according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION The detailed description of the present invention to be described later refers to the accompanying drawings, which illustrate specific embodiments in which the present invention may be practiced. These embodiments are described in detail sufficient to enable a person skilled in the art to practice the present invention. It is to be understood that the various embodiments of the present invention are different from each other, but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention in relation to one embodiment. In addition, it is to be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the detailed description to be described below is not intended to be taken in a limiting sense, and the scope of the present invention is limited only by the appended claims, along with all scopes equivalent to those claimed by the claims. Like reference numerals in the drawings refer to the same or similar functions over several aspects.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to enable those of ordinary skill in the art to easily implement the present invention.

1A is a side view showing a chip antenna module according to an embodiment of the present invention, FIGS. 2A and 2B are perspective views showing a chip antenna module according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. Is a perspective view showing a shielding via disposed on a chip antenna module according to FIG.

1A, 2A, 2B, and 3, a chip antenna module 100a according to an embodiment of the present invention includes a first patch antenna pattern 111a and a second patch antenna pattern 112a. By doing so, it is possible to provide transmission/reception means for a plurality of different frequency bands, and by further including the coupling patch pattern 115a, the frequency bandwidth corresponding to the second patch antenna pattern 112a can be widened. Here, the coupling patch pattern 115a may be omitted depending on bandwidth design conditions.

In addition, the chip antenna module 100a according to an embodiment of the present invention includes first feed vias 121a and 121b and second feed vias 122a and 122b, and is formed on the first ground plane 201a. Can be placed.

The first patch antenna pattern 111a is electrically connected to one end of the first feed vias 121a and 121b. Accordingly, the first patch antenna pattern 111a receives and transmits a first radio frequency (RF) signal of a first frequency band (eg, 28 GHz) from the first feed vias 121a and 121b, or transmits the first RF signal. It may be received and provided to the first feed vias 121a and 121b.

The second patch antenna pattern 112a is electrically connected to one end of the second feed vias 122a and 122b. Accordingly, the second patch antenna pattern 112a receives and transmits a second radio frequency (RF) signal of a second frequency band (eg, 39 GHz) from the second feed vias 122a and 122b or transmits a second RF signal. It may be received and provided to the second feed vias 122a and 122b.

The first and second patch antenna patterns 111a and 112a may resonate with respect to the first and second frequency bands, respectively, intensively receive energy corresponding to the first and second signals, and radiate to the outside.

The first ground plane 201a is the first and second RF signals radiated toward the first ground plane 201a among the first and second RF signals radiated by the first and second patch antenna patterns 111a and 112a. Since can be reflected (reflect), the radiation patterns of the first and second patch antenna patterns 111a and 112a can be concentrated in a specific direction (eg, z direction). Accordingly, a gain of the first and second patch antenna patterns 111a and 112a may be improved.

The resonance of the first and second patch antenna patterns 111a and 112a is generated based on a resonance frequency according to a combination of inductance and capacitance corresponding to the first and second patch antenna patterns 111a and 112a and structures around the first and second patch antenna patterns 111a and 112a. I can.

The size of the upper and/or lower surfaces of each of the first and second patch antenna patterns 111a and 112a may affect the resonance frequency. That is, the size of the upper and/or lower surfaces of each of the first and second patch antenna patterns 111a and 112a may be dependent on the first and second wavelengths corresponding to the first and second frequencies, respectively. If the first frequency is lower than the second frequency, the first patch antenna pattern 111a may be larger than the second patch antenna pattern 112a.

In addition, at least a portion of the first and second patch antenna patterns 111a and 112a may overlap in a vertical direction (eg, z direction). Accordingly, the size of the chip antenna module 100a in the horizontal direction (eg, in the x direction and/or y direction) can be greatly reduced, so that the overall chip antenna module 100a can be easily downsized.

The first and second feed vias 121a, 121b, 122a, and 122b are disposed to pass through at least one through hole of the first ground plane 201a. Accordingly, one end of the first and second feed vias 121a, 121b, 122a, and 122b is positioned above the first ground plane 201a, and of the first and second feed vias 121a, 121b, 122a, and 122b. The other end is located under the first ground plane 201a. Here, the other ends of the first and second feed vias 121a, 121b, 122a, and 122b are electrically connected to an integrated circuit (IC) mounted on the component mounting surface, thereby providing the first and second RF signals to the IC. Or you can get it from IC. The electromagnetic isolation between the first and second patch antenna patterns 111a and 112a and the IC may be improved by the first ground plane 201a.

The first feed vias 121a and 121b may include a 1-1 feed via and a 1-2 feed via through which the 1-1 1st RF signal polarized and the 1st-2 RF signal respectively pass. The 2 feed vias 122a and 122b may include a 2-1 feed via and a 2-2 feed via through which the 2-1 RF signal and the 2-2 RF signal polarized to each other pass.

That is, each of the first and second patch antenna patterns 111a and 112a can transmit and receive a plurality of RF signals, and the plurality of RF signals may be a plurality of carrier signals carrying different data. Therefore, the first and second patches The data transmission/reception rate of each of the antenna patterns 111a and 112a may be doubled according to transmission/reception of a plurality of RF signals.

For example, the 1-1 RF signal and the 1-2 RF signal may have different phases (eg, 90 degrees or 180 degrees phase difference) to reduce interference with each other, and the 2-1 RF signal and the second RF signal 2-2 RF signals may have different phases (eg, 90 degrees or 180 degrees phase difference) to reduce interference with each other.

For example, the 1-1 RF signal and the 2-1 RF signal form an electric field and a magnetic field in the x-direction and y-direction, respectively, perpendicular to the propagation direction (eg, z direction) and perpendicular to each other, and The 2 RF signal and the 2-2 RF signal form a magnetic field and an electric field in the x direction and the y direction, respectively, thereby implementing polarization between the RF signals. Surface current corresponding to the 1-1 RF signal and the 2-1 RF signal, and the surface corresponding to the 1-2 RF signal and the 2-2 RF signal in the first and second patch antenna patterns 111a and 112a Currents can flow perpendicular to each other.

Accordingly, the 1-1 feed via and the 2-1 feed via may be connected adjacent to the edge in one direction (eg, x direction) in the first and second patch antenna patterns 111a and 112a, and The via and the 2-2 feed via may be connected adjacent to the edge in the other direction (eg, y direction) in the first and second patch antenna patterns 111a and 112a, but the specific connection point may vary according to design.

Energy loss of the first and second RF signals within the chip antenna module 100a may decrease as the electrical length from the first and second patch antenna patterns 111a and 112a to the IC decreases. Since the length between the first and second patch antenna patterns 111a and 112a and the IC in the vertical direction (eg, z direction) is relatively short, the first and second feed vias 121a, 121b, 122a, and 122b are The electrical distance between the first and second patch antenna patterns 111a and 112a and the IC can be easily reduced.

When at least a portion of the first and second patch antenna patterns 111a and 112a overlap, the second feed vias 122a and 122b are the first patch antenna pattern to be electrically connected to the second patch antenna pattern 112a. It may be arranged to penetrate through (111a).

Accordingly, loss of transmission energy in the chip antenna module 100a of the first and second RF signals may be reduced, and the first and second feeds in the first and second patch antenna patterns 111a and 112a Connection points of the vias 121a, 121b, 122a, and 122b can be designed more freely.

Here, the connection points of the first and second feed vias 121a, 121b, 122a, and 122b may affect the transmission line impedance in terms of the first and second RF signals. Since the transmission line impedance is more closely matched to a specific impedance (for example, 50 ohms), the reflection phenomenon in the process of providing the first and second RF signals can be reduced. When the design freedom of the connection point of) is high, the gain of the first and second patch antenna patterns 111a and 112a can be more easily improved.

However, since the second feed vias 122a and 122b are disposed to pass through the first patch antenna pattern 111a, the radiation of the first RF signal concentrated on the first patch antenna pattern 111a may be affected. Accordingly, the degree of electromagnetic isolation between the first and second RF signals may be deteriorated. The electromagnetic isolation may cause deterioration in gains of each of the first and second patch antenna patterns 111a and 112a.

Accordingly, the chip antenna module 100a according to an embodiment of the present invention includes a first patch antenna pattern 111a and a second patch antenna pattern 112a, and surrounds the second feed vias 122a and 122b. May further include a plurality of shielding vias 130a.

The plurality of shielding vias 130a may be disposed to electrically connect the first patch antenna pattern 111a and the first ground plane 201a. Accordingly, among the first RF signals radiated from the first patch antenna pattern 111a, the first RF signals radiated toward the second feed vias 122a and 122b may be reflected by the plurality of shielding vias 130a. , Electromagnetic isolation between the first and second RF signals may be improved, and gains of each of the first and second patch antenna patterns 111a and 112a may be improved.

Here, the number and width of the plurality of shielding vias 130a are not particularly limited. When the space between the plurality of shielding vias 130a is shorter than a specific length (for example, a length dependent on the first wavelength of the first RF signal), the first RF signal substantially fills the space between the plurality of shielding vias 130a. May not pass. Accordingly, the degree of electromagnetic isolation between the first and second RF signals may be further improved.

When the second feed vias 122a and 122b are composed of a plurality of second feed vias, the plurality of shielding vias 130a may be arranged to surround the plurality of second feed vias, respectively.

Accordingly, since the electromagnetic isolation between the second feed vias 122a and 122b may be further improved, electrons between the 2-1 RF signal and the 2-2 RF signal in the second patch antenna pattern 112a The degree of miracle isolation may be further improved, and the overall gain of the second patch antenna pattern 112a may be further improved.

The first feed vias 121a and 121b are located skewed from the center of the first patch antenna pattern 111a in the first direction, and the second feed vias 122a and 122b are larger than the first feed vias 121a and 121b. It may be located closer to the center of the 1-patch antenna pattern 111a.

Since the plurality of shielding vias 130a are electrically connected to the first patch antenna pattern 111a, the surface current of the first patch antenna pattern 111a is shielded from the connection point of the first feed vias 121a and 121b. It may flow to the connection point of the via 130a. Therefore, since the surface current of the first patch antenna pattern 111a may be more concentrated on the edge of the first patch antenna pattern 111a, the RF signal of the first patch antenna pattern 111a is applied to the second patch antenna pattern 112a. ) Can be better avoided, allowing remote transmission and reception in the z direction. That is, a phenomenon in which the second patch antenna pattern 112a interferes with radiation of the first patch antenna pattern 111a may be further reduced, and a gain of the first patch antenna pattern 111a may be further improved.

In addition, referring to FIG. 1A, the chip antenna module 100a according to an embodiment of the present invention further includes at least one of a first dielectric layer 151a and a third dielectric layer 151b, and a second dielectric layer 152a. And, it may be mounted on the connection member 200. For example, the connection member 200 may have a stacked structure including at least some of a first ground plane 201a, a wiring ground plane 202a, a second ground plane 203a, and an IC ground plane 204a. In addition, it may be implemented as a printed circuit board (PCB).

The chip antenna module 100a and the connection member 200 according to an exemplary embodiment of the present invention may be manufactured separately from each other, and may be physically coupled to each other after each manufacturing.

Therefore, the first dielectric layer 151a, the third dielectric layer 151b, and the second dielectric layer 152a more easily exhibit characteristics different from the characteristics of the insulating layer of the connection member 200 (eg, dielectric constant, dielectric loss tangent, durability, etc.). Can have. Accordingly, the chip antenna module 100a according to an embodiment of the present invention can easily have improved antenna characteristics (eg, gain, bandwidth, directivity, etc.) compared to the size, and the connection member 200 is It is easy to have the wiring performance of lines and feed vias (eg, warp strength compared to the number of stacks, low dielectric constant, etc.)

The first dielectric layer 151a and the third dielectric layer 151b may be formed of a material having a higher dielectric constant than the second dielectric layer 152a. For example, the first dielectric layer 151a and the third dielectric layer 151b may be relatively formed of a ceramic material such as a low temperature co-fired ceramic (LTCC) or a glass material. It can be composed of a material having a high dielectric constant, and by further containing at least one of magnesium (Mg), silicon (Si), aluminum (Al), calcium (Ca), and titanium (Ti), higher dielectric constant or stronger durability It can be configured to have. For example, the first dielectric layer 151a and the third dielectric layer 151b may include Mg2Si04, MgAlO4, and CaTiO3.

The lower surface of the first dielectric layer 151a may provide an arrangement space for the solder layer 140a. The solder layer 140a may be physically coupled to the connection member 200 by being mounted on the upper surface of the connection member 200.

For example, the chip antenna module 100a according to an embodiment of the present invention may be disposed so that the solder layer 140a overlaps the second solder layer 180a disposed on the upper surface of the connection member 200. The second solder layer 180a may have a strong bonding force to the connection member 200 by being connected to the peripheral via 185a of the connection member 200. For example, the peripheral via 185a may be configured to connect between the second solder layer 180a and the first ground plane.

The solder layer 140a and the second solder layer 180a may be combined by a solder paste based on a material having a low melting point such as tin (Sn). The solder paste may be inserted between the solder layer 140a and the second solder layer 180a at a temperature higher than the melting point of the solder paste, and may be constituted of an electrical connection structure 160a as the temperature decreases. That is, the electrical connection structure 160a may electrically connect the solder layer 140a and the second solder layer 180a.

For example, in order to improve the bonding efficiency between the solder layer 140a and the second solder layer 180a, the surface of the solder layer 140a and the second solder layer 180a is a laminated structure of a nickel plated layer and a tin plated layer. It can be achieved, but is not limited thereto. That is, at least a portion of the solder layer 140a and the second solder layer 180a may be formed by a plating process, and the first dielectric layer 151a has properties suitable for the plating process of the solder layer 140a (eg, high temperature Can be configured to have reliability).

In addition, the lower surface of the first dielectric layer 151a may provide a lead-out space for the first and second feed vias 121a, 121b, 122a, 122b and the plurality of shielding vias 130a.

Accordingly, an electrical connection structure 160a having a relatively low melting point or a relatively large horizontal width at the bottom of each of the first and second feed vias 121a, 121b, 122a, 122b and the plurality of shielding vias 130a ) Can be connected. For example, the first electrical connection structure may be composed of at least one of a solder ball, a pin, a land, and a pad, and may have a shape similar to that of the solder layer 140a according to the design. Can have.

The top surface of the first dielectric layer 151a may provide a space for placing the first patch antenna pattern 111a.

The lower surface of the third dielectric layer 151b may provide an arrangement space for the second patch antenna pattern 112a.

The upper surface of the third dielectric layer 151b may provide an arrangement space for the coupling patch pattern 115a, and may be sealed by an encapsulant according to design.

The second dielectric layer 152a may be disposed on the upper surface of the first dielectric layer 151a or the lower surface of the third dielectric layer 151b, and is lower than the dielectric constant of the first dielectric layer 151a or the dielectric constant of the third dielectric layer 151b. It can have a permittivity.

The second dielectric layer 152a may be configured to have a lower dielectric constant than the insulating layer of the connection member 200, such as a polymer, but is not limited thereto. For example, the second dielectric layer 152a is made of ceramic, or is composed of high flexibility such as liquid crystal polymer (LCP) or polyimide, or epoxy having high strength or high adhesion. It may be made of resin, may be configured to have high durability such as Teflon, or may be configured to have high compatibility with the connection member 200 such as a prepreg.

The RF signals transmitted and received by the chip antenna module 100a are transmitted through the first dielectric layer 151a, the third dielectric layer 151b, and the second dielectric layer 152a, the first dielectric layer 151a, the third dielectric layer 151b, and It may have a wavelength based on the dielectric constant of the second dielectric layer 152a. That is, the effective wavelength of the RF signal in the chip antenna module 100a may be shortened according to the high dielectric constants of the first dielectric layer 151a and the third dielectric layer 151b. Since the overall size of the chip antenna module 100a has a high correlation with the length of the effective wavelength of the RF signal, the chip antenna module 100a has a high dielectric constant first dielectric layer 151a and/or a third dielectric layer 151b. ), it is possible to have a reduced size without substantially deteriorating antenna performance.

The overall size of the chip antenna module 100a may correspond to the number of arrays of the chip antenna modules 100a per unit size of the first ground plane 201a. That is, the overall gain and/or directivity of the plurality of chip antenna modules 100a can be easily improved as the size of the chip antenna module 100a is smaller.

Meanwhile, since the second dielectric layer 152a has a relatively low dielectric constant, the wavelength of the RF signal in the second dielectric layer 152a may be long.

The first interface between the second dielectric layer 152a and the first dielectric layer 151a and the second interface between the second dielectric layer 152a and the third dielectric layer 151b are each a boundary condition for an RF signal. Can act as

Due to a difference in dielectric constant between the first dielectric layer 151a and/or the third dielectric layer 151b and the second dielectric layer 152a, the propagation direction of the RF signal passing through the boundary condition may be refracted. The degree of refraction of the RF signal may be greater as the difference in permittivity increases.

Since the second dielectric layer 152a having a low dielectric constant is disposed between the first dielectric layer 151a and the third dielectric layer 151b having a high dielectric constant, the transmission/reception direction of each of the first and second RF signals is further in the z direction. Can be focused.

Since the first RF signal radiated from the upper surface of the first patch antenna pattern 111a is directed from a medium having a low permittivity to a medium having a high permittivity, a vector component in the horizontal direction of the first RF signal may be shortened. Accordingly, the radiation direction of the first patch antenna pattern 111a may be more concentrated in the z direction. Accordingly, the gain of the first patch antenna pattern 111a may be improved.

In addition, since the first RF signal has a relatively longer horizontal vector component in the second dielectric layer 152a, it can be radiated in the z direction by better avoiding the second patch antenna pattern 112a. Accordingly, a phenomenon in which the second patch antenna pattern 112a interferes with the radiation of the first patch antenna pattern 111a may be further reduced, and the gain of the first patch antenna pattern 111a may be further improved.

The second RF signal radiated from the lower surface of the second patch antenna pattern 112a may be propagated in the z direction by reflection of the first ground plane 201a and/or the first patch antenna pattern 111a. , As the second RF signal is directed from a medium having a low dielectric constant to a medium having a high dielectric constant, the second RF signal may be further concentrated in the z direction. Accordingly, the gain of the second patch antenna pattern 112a may be improved.

As a result, the chip antenna module 100a according to an embodiment of the present invention may improve both the gain of the first RF signal and the gain of the second RF signal.

Meanwhile, the thickness of the second dielectric layer 152a may be thinner than that of the first dielectric layer 151a. Accordingly, the relatively low dielectric constant of the second dielectric layer 152a can further concentrate the remote transmission/reception directions of the first and second RF signals in the z direction.

The thickness of the third dielectric layer 151b may be thicker than that of the second dielectric layer 152a and thinner than the thickness of the first dielectric layer 151a. Accordingly, a phenomenon in which the second patch antenna pattern 112a causes electromagnetic interference to the first patch antenna pattern 111a via the coupling patch pattern 115a can be further suppressed.

1B is a side view showing a chip antenna module according to an embodiment of the present invention.

Referring to FIG. 1B, the chip antenna module according to an embodiment of the present invention may further include a second dielectric layer 152b and an air cavity 152c.

For example, the second dielectric layer 152b may be configured to surround the cavity 152c according to design, and may physically support between the first dielectric layer 151a and the third dielectric layer 151b.

Accordingly, the dielectric constant between the first and second patch antenna patterns 111a and 112a may be lower than the dielectric constant of the second dielectric layer 152b, and the first and second RF signals are formed with the first dielectric layer 151a and the cavity ( According to a greater difference in dielectric constant between 152c), it may be more efficiently refracted at the interface between the first dielectric layer 151a and the cavity 152c. Accordingly, the gain of the chip antenna module according to an embodiment of the present invention may be further improved.

4 is a plan view illustrating various types of solder layers 140a of a chip antenna module according to an embodiment of the present invention.

Referring to FIG. 4, the solder layer 140a of the chip antenna module 100e according to an embodiment of the present invention may have a straight bar shape, and a chip antenna module 100f according to an embodiment of the present invention. The solder layer 140a of may have a shape of a guide ring surrounding the outer periphery of the chip antenna module 100e.

The bonding force of the solder layer 140a to the connection member may be stronger as the size of the solder layer 140a increases. Therefore, the shape of the solder layer 140a is the characteristics of the chip antenna modules 100a, 100e, and 100f according to an embodiment of the present invention (eg, the total number of arrays, the total number of patch antenna patterns, the total number of vias, etc.) Can be determined based on

5A is a perspective view illustrating an arrangement of a plurality of chip antenna modules according to an embodiment of the present invention.

Referring to FIG. 5A, a plurality of chip antenna modules 100a, 100b, 100c, and 100d according to an embodiment of the present invention may be arranged in a [1 X n] structure. Where n is a natural number.

The space between the plurality of chip antenna modules 100a, 100b, 100c, and 100d may be composed of air having a dielectric constant lower than that of each of the plurality of chip antenna modules 100a, 100b, 100c, and 100d, or may be composed of a sealing material. have.

Each side of the plurality of chip antenna modules 100a, 100b, 100c, and 100d may serve as a boundary condition for an RF signal. Therefore, when the plurality of chip antenna modules 100a, 100b, 100c, and 100d are arranged to be spaced apart from each other, the degree of electromagnetic isolation of the plurality of chip antenna modules 100a, 100b, 100c, and 100d from each other can be improved. .

5B is a perspective view showing an integrated chip antenna module in which a plurality of chip antenna modules of FIG. 5A are integrated.

Referring to FIG. 5B, the integrated chip antenna module 100abcd according to an embodiment of the present invention may have a structure in which a plurality of chip antenna modules shown in FIGS. 1A to 5A are integrated.

That is, the first dielectric layer may be composed of a single first dielectric layer overlapping each of the plurality of first patch antenna patterns according to design. The plurality of first patch antenna patterns may be arranged side by side on the integrated chip antenna module 100abcd so as to overlap the plurality of coupling patch patterns 115a, 115b, 115c, and 115d in the z direction.

Accordingly, the overall size of the integrated chip antenna module 100abcd according to an embodiment of the present invention may be reduced.

The electromagnetic interference that the plurality of first feed vias may give to each other may be reduced by the plurality of shielding vias described above. Accordingly, the integrated chip antenna module 100abcd according to an embodiment of the present invention may have a further reduced size and may prevent deterioration of antenna performance due to the size reduction.

6A is a plan view illustrating an endfire antenna included in a connection member disposed under a chip antenna module according to an embodiment of the present invention.

Referring to FIG. 6A, the connection member 200 may include a plurality of endfire antennas ef1, ef2, ef3, and ef4 arranged in parallel to the plurality of chip antenna modules 100a, 100b, 100c, and 100d. , It is possible to form a radiation pattern of the RF signal in the horizontal direction (eg, x direction and/or y direction).

The plurality of endfire antennas ef1, ef2, ef3, and ef4 may each include a plurality of endfire antenna patterns 210a and feed lines 220a, and may further include a director pattern 215a.

Since the plurality of chip antenna modules 100a, 100b, 100c, and 100d include a plurality of shielding vias arranged to surround the first feed via, electromagnetic isolation of the endfire antennas ef1, ef2, ef3, and ef4 Can be improved. Accordingly, the gains of the plurality of chip antenna modules 100a, 100b, 100c, and 100d may be further improved.

6B is a plan view illustrating an endfire antenna disposed on a connection member disposed under a chip antenna module according to an embodiment of the present invention.

Referring to FIG. 6B, the connection member 200 may include a plurality of endfire antennas ef5, ef6, ef7, and ef8 arranged in parallel to the plurality of chip antenna modules 100a, 100b, 100c, and 100d. , It is possible to form a radiation pattern of the RF signal in the horizontal direction.

The plurality of endfire antennas ef5, ef6, ef7, and ef8 may include a radiator 431 and a dielectric 432, respectively.

7A to 7C are diagrams illustrating a method of manufacturing a chip antenna module according to an embodiment of the present invention.

Referring to FIG. 7A, a first dielectric layer 151a and a third dielectric layer 151b may be provided, a through hole TH may be formed in the first dielectric layer 151a, and a conductive paste may be formed of a through hole TH. ) By being applied or filled to the first and second feed vias 121a and 122a and a plurality of shielding vias 130a.

Referring to FIG. 7B, the first patch antenna pattern 111a may be formed by printing in a conductive paste state on the upper surface of the first dielectric layer 151a and drying it, and the second patch antenna pattern 112a is a third dielectric layer. Printed in the form of a conductive paste on the lower surface of 151b and dried, the coupling patch pattern 115a may be formed by printing in the form of a conductive paste on the upper surface of the third dielectric layer 151b and drying. , The solder layer 140a may be formed by printing a conductive paste on the lower surface of the first dielectric layer 151a and drying it. Thereafter, the second dielectric layer 152a may be formed on the upper surface of the first dielectric layer 151a, and the third dielectric layer 151b may be pressed onto the second dielectric layer 152a.

Referring to FIG. 7C, a plurality of first patch antenna patterns 111a and solder layers 140a may be formed on one first dielectric layer 151a, and the first dielectric layer 151a is cut (cut1, cut2). Can be. Accordingly, a plurality of chip antenna modules can be manufactured simultaneously.

7D is a diagram illustrating a process of forming an arrangement space of a patch antenna pattern in a dielectric layer of a chip antenna module according to an embodiment of the present invention.

Referring to FIG. 7D, an upper surface and/or a lower surface of the third dielectric layer 151b may have a groove. The groove may be formed by laser processing for precision, but is not limited thereto.

The second patch antenna pattern 112a and/or the coupling patch pattern 115a may be printed and dried in the groove of the third dielectric layer 151b. Depending on the design, the groove may also be formed in the first dielectric layer.

Accordingly, the process deviation of the first patch antenna pattern, the second patch antenna pattern 112a and/or the coupling patch pattern 115a may be further reduced, and the first patch antenna pattern and the second patch antenna pattern 112a ) And/or the separation distance between the coupling patch patterns 115a may be more precisely optimized, and thus the reliability of antenna performance (eg, gain, bandwidth) may be further increased.

FIG. 8A is a plan view showing a first ground plane of a connection member included in an electronic device according to an embodiment of the present invention, and FIG. 8B is a plan view showing a feed line below the first ground plane of FIG. 8A, and FIG. 8C 8B is a plan view showing a wiring via and a second ground plane below the feed line of FIG. 8B, and FIG. 8D is a plan view showing an IC arrangement region and an endfire antenna below the second ground plane of FIG. 8C.

8A to 8D, the feed via 120a comprehensively corresponds to the first and second feed vias described above, and the patch antenna pattern 110a comprehensively corresponds to the first and second patch antenna patterns. Correspondingly, a plurality of chip antenna modules according to an embodiment of the present invention may be arranged in a horizontal direction (eg, x direction and/or y direction).

Referring to FIG. 8A, the first ground plane 201a may have a through hole through which the feed via 120a passes, and may electromagnetically shield between the patch antenna pattern 110a and the feed line. The peripheral via 185a may extend upward (for example, in the z direction), and may be connected to the above-described second solder layer.

Referring to FIG. 8B, the wiring ground plane 202a may surround at least a portion of the endfire antenna feed line 220a and the feed line 221a, respectively. The end fire antenna feed line 220a may be electrically connected to the second wiring via 232a, and the feed line 221a may be electrically connected to the first wiring via 231a. The wiring ground plane 202a may electromagnetically shield between the endfire antenna feed line 220a and the feed line 221a. One end of the end fire antenna feed line 220a may be connected to the second feed via 211a.

Referring to FIG. 8C, the second ground plane 203a may have a plurality of through-holes through which the first wiring via 231a and the second wiring via 232a respectively pass, and may have a coupling ground pattern 235a. Can have. The second ground plane 203a may electromagnetically shield the feed line and the IC.

Referring to FIG. 8D, the IC ground plane 204a may have a plurality of through holes through which the first wiring via 231a and the second wiring via 232a respectively pass. The IC 310a may be disposed under the IC ground plane 204a and may be electrically connected to the first wiring via 231a and the second wiring via 232a. The endfire antenna pattern 210a and the director pattern 215a may be disposed at substantially the same height as the IC ground plane 204a.

The IC ground plane 204a may provide a ground used in the circuit and/or passive components of the IC 310a as the IC 310a and/or passive components. Depending on the design, the IC ground plane 204a may provide a transmission path for power and signals used in the IC 310a and/or passive components. Thus, the IC ground plane 204a may be electrically connected to the IC and/or passive components.

Meanwhile, the wiring ground plane 202a, the second ground plane 203a, and the IC ground plane 204a may have a recessed shape to provide a cavity. Accordingly, the endfire antenna pattern 210a may be further disposed closer to the IC ground plane 204a.

Meanwhile, the vertical relationship and shape of the wiring ground plane 202a, the second ground plane 203a, and the IC ground plane 204a may vary according to design.

9A to 9B are side views illustrating a portion shown in FIGS. 8A to 8D and a structure of a lower side thereof.

9A, a chip antenna module according to an embodiment of the present invention includes a connection member 200, an IC 310, an adhesive member 320, an electrical connection structure 330, a sealing material 340, a manual It may include at least some of the component 350 and the core member 410.

The connection member 200 may have a structure similar to the connection member described above with reference to FIGS. 1A to 7C.

The IC 310 is the same as the above-described IC, and may be disposed under the connection member 200. The IC 310 may be electrically connected to the wiring of the connection member 200 to transmit or receive an RF signal, and may be electrically connected to a ground plane of the connection member 200 to provide a ground. For example, the IC 310 may generate a converted signal by performing at least some of frequency conversion, amplification, filtering, phase control, and power generation.

The adhesive member 320 may adhere the IC 310 and the connection member 200 to each other.

The electrical connection structure 330 may electrically connect the IC 310 and the connection member 200. For example, the electrical connection structure 330 may have a structure such as a solder ball, a pin, a land, and a pad. The electrical connection structure 330 may have a melting point lower than that of the wiring of the connection member 200 and the ground plane, and thus may electrically connect the IC 310 and the connection member 200 through a predetermined process using the low melting point.

The encapsulant 340 may seal at least a portion of the IC 310, and improve heat dissipation performance and impact protection performance of the IC 310. For example, the encapsulant 340 may be implemented with a photo imageable encapsulant (PIE), an Ajinomoto build-up film (ABF), an epoxy molding compound (EMC), or the like.

The passive component 350 may be disposed on the lower surface of the connection member 200, and may be electrically connected to the wiring and/or the ground plane of the connection member 200 through the electrical connection structure 330. For example, the passive component 350 may include at least some of a capacitor (eg, Multi Layer Ceramic Capacitor (MLCC)), an inductor, and a chip resistor.

The core member 410 may be disposed under the connection member 200, and receives an intermediate frequency (IF) signal or a base band signal from the outside and transmits it to the IC 310 or from the IC 310. It may be electrically connected to the connection member 200 to receive the IF signal or the baseband signal and transmit it to the outside. Here, the frequency of the RF signal (eg, 24GHz, 28GHz, 36GHz, 39GHz, 60GHz) is greater than the frequency of the IF signal (eg, 2GHz, 5GHz, 10GHz, etc.).

For example, the core member 410 may transmit an IF signal or a baseband signal to the IC 310 or receive from the IC 310 through a wiring that may be included in the IC ground plane of the connection member 200. Since the first ground plane of the connection member 200 is disposed between the IC ground plane and the wiring, the IF signal or the baseband signal and the RF signal may be electrically isolated within the chip antenna module.

Referring to FIG. 9B, the chip antenna module according to an embodiment of the present invention may include at least a portion of a shield member 360, a connector 420, and a chip antenna 430.

The shielding member 360 may be disposed under the connection member 200 to confine the IC 310 together with the connection member 200. For example, the shielding member 360 may be disposed to cover the IC 310 and the passive component 350 together (eg, a conformal shield) or cover each (eg, a compartment shield). For example, the shield member 360 may have a shape of a hexahedron with an open surface, and may have a hexahedral accommodation space through coupling with the connection member 200. The shielding member 360 may have a short skin depth by being implemented with a material of high conductivity such as copper, and may be electrically connected to the ground plane of the connection member 200. Accordingly, the shielding member 360 may reduce electromagnetic noise that may be received by the IC 310 and the passive component 350.

The connector 420 may have a connection structure of a cable (eg, a coaxial cable, a flexible PCB), may be electrically connected to the IC ground plane of the connection member 200, and play a role similar to the above-described core member 410. Can be done. That is, the connector 420 may receive an IF signal, a baseband signal and/or power from a cable, or may provide an IF signal and/or a baseband signal through a cable.

The chip endfire antenna 430 may transmit or receive an RF signal in support of the chip antenna module according to an embodiment of the present invention. For example, the chip endfire antenna 430 may include a dielectric block having a dielectric constant greater than that of an insulating layer, and a plurality of electrodes disposed on both sides of the dielectric block. One of the plurality of electrodes may be electrically connected to the wiring of the connection member 200, and the other may be electrically connected to the ground plane of the connection member 200.

10A and 10B are plan views illustrating an electronic device including a chip antenna module according to an embodiment of the present invention.

Referring to FIG. 10A, a chip antenna module including a patch antenna pattern 100g may be disposed adjacent to a side boundary of the electronic device 700g on a set substrate 600g of the electronic device 700g.

The electronic device 700g includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer. ), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. Not limited.

A communication module 610g and a baseband circuit 620g may be further disposed on the set substrate 600g. The chip antenna module may be electrically connected to the communication module 610g and/or the baseband circuit 620g through a coaxial cable 630g.

The communication module 610g includes a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), and a flash memory to perform digital signal processing; Application processor chips such as a central processor (eg, a CPU), a graphics processor (eg, a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; It may include at least some of a logic chip such as an analog-to-digital converter and an application-specific IC (ASIC).

The baseband circuit 620g may generate a base signal by performing analog-to-digital conversion, amplification, filtering, and frequency conversion of the analog signal. The base signal input/output from the baseband circuit 620g may be transmitted to the chip antenna module through a cable.

For example, the base signal may be transmitted to the IC through an electrical connection structure, a core via, and a wiring. The IC may convert the base signal into a millimeter wave (mmWave) band RF signal.

Referring to FIG. 10B, a plurality of chip antenna modules and antenna modules each including a patch antenna pattern 100i are adjacent to the center of the side of the polygonal electronic device 700i on the set substrate 600i of the electronic device 700i. The communication module 610i and the baseband circuit 620i may be further disposed on the set substrate 600i. The chip antenna module and the antenna module may be electrically connected to the communication module 610i and/or the baseband circuit 620i through a coaxial cable 630i.

Meanwhile, referring to FIGS. 10A and 10B, the dielectric layer 1140g may be filled in a region in which a pattern, a via, a plane, a strip, a line, or an electrical connection structure is not disposed in the chip antenna module according to an embodiment of the present invention. have.

For example, the dielectric layer (1140g) is FR4, Liquid Crystal Polymer (LCP), Low Temperature Co-fired Ceramic (LTCC), thermosetting resin such as epoxy resin, thermoplastic resin such as polyimide, or these resins together with inorganic fillers. Resin impregnated into core materials such as glass fiber (Glass Fiber, Glass Cloth, Glass Fabric), prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), Photo Imagable Dielectric: PID) resin, a general copper clad laminate (CCL), or glass or ceramic (ceramic)-based insulating material can be implemented.

On the other hand, the patterns, vias, planes, strips, lines, and electrical connection structures disclosed herein are metal materials (e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn)), gold (Au ), nickel (Ni), lead (Pb), titanium (Ti), or a conductive material such as an alloy thereof), CVD (chemical vapor deposition), PVD (Physical Vapor Deposition), sputtering , Subtractive, Additive, SAP (Semi-Additive Process), MSAP (Modified Semi-Additive Process) may be formed according to a plating method, such as, but is not limited thereto.

Meanwhile, the RF signals disclosed herein are Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, It may have a format according to any other wireless and wired protocols designated as GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and later, but is not limited thereto.

In the above, the present invention has been described by specific matters such as specific elements and limited embodiments and drawings, but this is provided only to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments. , Anyone with ordinary knowledge in the technical field to which the present invention pertains can make various modifications and variations from these descriptions.

100a, 100b, 100c, 100d, 100e: chip antenna module
111a: first patch antenna pattern
112a: second patch antenna pattern
115a: coupling patch pattern
121a, 121b: first feed via
122a, 122b: second feed via
130a: multiple shielding vias
140a: solder layer
151a: first dielectric layer
151b: third dielectric layer
152a, 152b: second dielectric layer
152c: air cavity
160a: electrical connection structure
180a: second solder layer
185a: peripheral via
200: connection member
201a: first ground plane
202a: wiring ground plane
203a: second ground plane
204a: IC ground plane
221a: feed line
310: IC (Integrated Circuit)
ef1, ef2, ef3, ef4, ef5, ef6, ef7, ef8: endfire antenna

Claims (16)

A first dielectric layer;
A solder layer disposed on a lower surface of the first dielectric layer;
A first patch antenna pattern disposed on an upper surface of the first dielectric layer and having a through hole;
A second patch antenna pattern that is disposed above the first patch antenna pattern and is smaller than the first patch antenna pattern;
A first feed via disposed to pass through the first dielectric layer from a lower surface of the first dielectric layer and electrically connected to the first patch antenna pattern;
A second feed via disposed from a lower surface of the first dielectric layer to penetrate the through hole of the first dielectric layer and the first patch antenna pattern, and electrically connected to the second patch antenna pattern; And
A plurality of shielding vias disposed from a lower surface of the first dielectric layer to penetrate the first dielectric layer, electrically connected to the first patch antenna pattern, and arranged to surround the second feed via; Chip antenna module comprising a.
The method of claim 1,
The second feed via is composed of a plurality of second feed vias,
The plurality of shielding vias are arranged to surround each of the plurality of second feed vias.
The method of claim 1,
The first feed via is located in a first direction from the center of the first patch antenna pattern,
The second feed via is located closer to the center of the first patch antenna pattern than the first feed via.
The method of claim 1,
Further comprising a second dielectric layer disposed between the first and second patch antenna patterns,
A chip antenna module having a dielectric constant of the second dielectric layer lower than that of the first dielectric layer.
The method of claim 4,
A chip antenna module having a thickness of the second dielectric layer smaller than that of the first dielectric layer.
The method of claim 4,
The second dielectric layer includes a polymer,
The first dielectric layer is a chip antenna module comprising a ceramic (ceramic).
The method of claim 4,
Further comprising a third dielectric layer disposed on the upper side of the second dielectric layer,
A chip antenna module having a dielectric constant of the third dielectric layer higher than that of the second dielectric layer.
The method of claim 7,
The thickness of the third dielectric layer is thicker than that of the second dielectric layer and is thinner than the thickness of the first dielectric layer.
The method of claim 8,
A chip antenna module further comprising a coupling patch pattern disposed on an upper surface of the third dielectric layer.
The method of claim 1,
Further comprising a third dielectric layer disposed above the first dielectric layer,
A chip antenna module provided with a lower surface of the third dielectric layer providing a space for placing the second patch antenna pattern.
The method of claim 10,
A second dielectric layer disposed between the first and third dielectric layers; And
An air cavity surrounded by the second dielectric layer; Chip antenna module further comprising a.
The method of claim 1,
The first patch antenna pattern is a plurality of first patch antenna patterns,
The first dielectric layer is a single first dielectric layer overlapping each of the plurality of first patch antenna patterns.
A plurality of chip antenna modules;
A connection member providing an upper surface to which the solder layers of each of the chip antenna modules are electrically connected; And
An IC electrically connected to a lower surface of the connection member; Including,
At least one of the plurality of chip antenna modules,
A first dielectric layer;
A solder layer disposed on a lower surface of the first dielectric layer;
A first patch antenna pattern disposed on an upper surface of the first dielectric layer and having a through hole;
A second patch antenna pattern that is disposed above the first patch antenna pattern and is smaller than the first patch antenna pattern;
A first feed via disposed to pass through the first dielectric layer from a lower surface of the first dielectric layer and electrically connected to the first patch antenna pattern;
A second feed via disposed from a lower surface of the first dielectric layer to penetrate the through hole of the first dielectric layer and the first patch antenna pattern, and electrically connected to the second patch antenna pattern; And
A plurality of shielding vias disposed from a lower surface of the first dielectric layer to penetrate the first dielectric layer, electrically connected to the first patch antenna pattern, and arranged to surround the second feed via; Electronic device comprising a.
The method of claim 13, wherein the connection member,
A feed line electrically connecting the first feed via and the IC;
A wiring ground plane surrounding the feed line; And
A first ground plane disposed between the wiring ground plane and the plurality of chip antenna modules; Electronic device comprising a.
The method of claim 14, wherein the connection member,
A second solder layer disposed above the first ground plane and electrically connected to the solder layer; And
A peripheral via connecting the second solder layer and the first ground plane; Electronic device further comprising a.
The method of claim 13, wherein the connection member,
A first ground plane disposed below the plurality of chip antenna modules; And
A plurality of endfire antennas disposed below the first ground plane so that at least a portion thereof does not overlap with the first ground plane; Electronic device further comprising a.

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