KR102064229B1 - Control method of single-phase npc multilevel pwm converter - Google Patents

Abstract

The present invention relates to a single-phase NPC multilevel PWM converter control method. The method includes: a step in which a control part receives a voltage of each capacitor of an output terminal; a step in which the control part calculates a capacitor voltage deviation through the received voltage, and determines a clamping mode; a step in which the control part calculates a capacitor voltage deviation compensation value; a step in which the control part selects a reference vector in accordance with an area in which a command voltage vector is located, but selects at least three reference vectors from at least some areas; a step in which the control part calculates the duty of each of the reference vectors considering the determined clamping mode, the voltage deviation compensation value and the command voltage vector; and a step in which the control part controls the creation of a PWM signal in accordance with the calculated duty of each of the reference vectors.

Description

CONTROL METHOD OF SINGLE-PHASE NPC MULTILEVEL PWM CONVERTER}

The present invention relates to a single phase NPC multilevel PWM converter control method, and more particularly, to a single phase NPC multilevel PWM converter control method based on a discontinuous modulation technique.

In the case of a power converter that requires a high DC-link voltage such as a railroad car, there are problems of high voltage stress and high dv / dt of a switching element, and therefore, a large breakdown voltage IGBT is mainly used. However, a high breakdown voltage switching element has a high conduction voltage, resulting in high conduction loss, and also has a disadvantage in that dynamic characteristics are inferior to low breakdown voltage elements.

In order to solve this problem, research on the Neutral-Point-Clamped (NPC) three-level converter has been conducted. In the case of a three-level converter, the voltage stress is reduced by half due to the switching elements connected in series, and the harmonic content is lowered due to the stepped voltage characteristic, thereby having high power quality.

In addition, research on multi-level converters of four or more levels is being conducted. However, when the control technique used in the three-level converter is applied to four or more level converters, it is difficult to control the voltage variation of the DC-link capacitor connected in series at the output stage. There is a problem.

The research on hybrid type converters using additional compensation circuits or NPC structures and flying capacitors is ongoing. However, additional compensation circuits increase the complexity of the system, and hybrid type initial voltages of the flying capacitors. There is a problem that requires a separate DC power supply for setting the situation is not widely used in the industry.

Meanwhile, the background art of the present invention is disclosed in Korean Patent Laid-Open Publication No. 10-2017-0077339 (Jul. 06, 2017).

It is an object of the present invention to provide a discontinuous modulation technique (Discontinuous PWM) applicable to three-level or more single-phase NPC multilevel PWM converter.

In accordance with an aspect of the present invention, there is provided a method for controlling a single-phase NPC multilevel PWM converter, comprising: receiving, by a controller, a voltage of each capacitor of an output terminal; Calculating, by the controller, a capacitor voltage deviation based on the input voltage, and determining a clamping mode; Calculating, by the controller, a capacitor voltage deviation compensation value; Selecting a reference vector by the control unit, selecting a reference vector according to a region where a command voltage vector is located, and selecting three or more reference vectors in at least a portion of the region; Calculating, by the controller, the duty of each selected reference vector in consideration of the determined clamping mode, the voltage deviation compensation value, and the command voltage vector; And controlling the PWM signal generation according to the calculated duty of each reference vector.

In the present invention, the region in which the command voltage vector is located is divided into at least three sections, and the number of reference vectors selected from the outermost section is less than or equal to the number of reference vectors selected from the next section.

In the present invention, the control unit is configured to use only the clamped switching state of the U, V switching pair representing each reference vector.

In the present invention, the control unit determines the clamping mode by comparing the voltage of the capacitor connected in series with the reference value, in the case of an even level converter, compares the reference value with the remaining capacitors except the capacitor located in the center of the series connected capacitor, odd-numbered converter In this case, the clamping mode is determined by comparing all capacitors with a reference value.

In the present invention, the controller selects a voltage having a large difference from the reference value among the voltages of the capacitor compared with the reference value, and determines the clamping mode in consideration of the sign of the difference between the reference value and the selected voltage.

In the present invention, the control unit calculates (N-2) voltage deviation compensation values in the case of an N-level converter.

In the present invention, the control unit is at least a compensation value for compensating for the difference between the voltage of the capacitor of one end of the series-connected capacitor and the average voltage of the remaining capacitors, the voltage of the capacitor of the other end of the series-connected capacitor and the average voltage of the remaining capacitors It is characterized by calculating a compensation value to compensate for the difference.

In the present invention, when three or more reference vectors are selected, the controller first calculates the duty of the reference vector closest to zero other than zero among the selected reference vectors, and calculates the duty of the remaining reference vectors based on the reference vectors. Characterized in that.

In the present invention, the controller calculates the duty of the reference vector as a reference based on the voltage magnitude of each of the selected reference vectors, the magnitude of the command voltage vector, and the voltage deviation compensation value.

The single-phase NPC multilevel PWM converter control method according to the present invention has the effect of enabling the capacitor voltage deviation control by using the multiple adjacent reference vector method.

1 is a circuit diagram illustrating a four-level NPC converter according to an embodiment of the present invention.
2 is a circuit diagram illustrating a five-level NPC converter according to an embodiment of the present invention.
3 is an exemplary view showing the position of the command voltage of the four-level NPC converter according to an embodiment of the present invention and the charge and discharge state of the capacitor according to it.
4 is an exemplary diagram illustrating a change in (U, V) switching state and duty of a switching pair according to the command voltage in the first region.
FIG. 5 is an exemplary diagram illustrating a capacitor voltage deviation when a 4-level NPC converter is controlled according to a conventional control technique.
6 is a block diagram illustrating an apparatus in which a method of controlling a single-phase NPC multilevel PWM converter according to an embodiment of the present invention is performed.
7 is a flowchart illustrating a method of controlling a single-phase NPC multilevel PWM converter according to an embodiment of the present invention.
8 is a flowchart illustrating selection of a reference vector in a method of controlling a single-phase NPC multilevel PWM converter according to an embodiment of the present invention.
9 is a circuit diagram illustrating a single-phase NPC four-level PWM converter for dual-interlacing mode.
FIG. 10 is an exemplary diagram illustrating an operation performance when a single-phase NPC multilevel PWM converter control method according to an embodiment of the present invention is applied to a four-level NPC converter.
FIG. 11 is an exemplary diagram illustrating an operation performance when a single-phase NPC multilevel PWM converter control method according to an embodiment of the present invention is applied to a five-level NPC converter.

Hereinafter, an embodiment of a single phase NPC multilevel PWM converter control method according to the present invention will be described with reference to the accompanying drawings. In this process, the thickness of the lines or the size of the components shown in the drawings may be exaggerated for clarity and convenience of description. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or convention of a user or an operator. Therefore, definitions of these terms should be made based on the contents throughout the specification.

1 is a circuit diagram showing a four-level NPC converter according to an embodiment of the present invention, Figure 2 is a circuit diagram showing a five-level NPC converter according to an embodiment of the present invention.

That is, the single-phase NPC multilevel PWM converter control method according to the present invention can be applied to the existing simple and robust NPC converter circuit structure. As shown in FIGS. 1 and 2, the single-phase NPC multilevel PWM converter has a power source (Vs) and a boost inductor (L) at the input stage, a series connected switch (Ux, Vx) and a clamping diode (Dux, Dvx) at the switching stage. ) And DC-link capacitor (Cx) connected in series at the output stage. Where x represents the number of each element.

More specifically, an N-level NPC converter has 2 * (N-1) switches and (N-1) * (N-2) clamping diodes per unit switch leg and consists of N-1 output capacitors. do. For a four-level converter, U1 and U4, U2 and U5, U3 and U6 are complementary to each other. That is, when U1 (U2, U3) is turned on, U4 (U5, U6) is turned off and vice versa. The same applies to the V phase. Therefore, the possible voltages for Vu are Vdc, U1 when U1, U2 and U3 are all on, Vdc * 2/3, U1 and U2 when U2 and U3 are on and Vdc / 3, U1, when U3 is on and only U3 is on. When both U2 and U3 are off, it becomes 0V. The same applies to the voltage at Vv. Where Vdc is the DC-link voltage applied to the load R.

In such NPC multilevel converters, voltage compensation of series connected capacitors is one of the important design elements. If the DC-link voltage is not divided evenly among the capacitors connected in series due to inadequate switching technique or mismatching of the device, asymmetry occurs in the voltage applied to the switch device and voltage distortion causes the life of the switch device. Shorter and lower power quality. Therefore, in case of NPC multilevel converter, the neutral point compensation should be designed.

In the case of a three-level converter, the number of capacitors is two, and techniques for compensating for these voltage variations are well known. For example, in the case of the continuous switching technique, the neutral point voltage compensation can be performed by applying DC-Offset to the switch PWM duty, and in the case of the discontinuous switching technique, the clamping mode is alternated. However, in the case of four-level or higher NPC converters in which the number of capacitors increases to three or more, the voltage variation of the capacitors is not compensated by the conventional method.

3 is an exemplary view showing the position of the command voltage of the four-level NPC converter according to an embodiment of the present invention and the charge and discharge state of the capacitor according to the present invention. Same as

In FIG. 3, 3E, -2E, -E, 0, E, 2E, and 3E mean a reference vector, Vc * means a converter input voltage command vector, and the numbers in parentheses below the reference vector can represent the reference vector. (U, V) switching pairs, and C and D respectively represent the charge and discharge state of the capacitor.

For example, according to the conventional general control technique, when the reference vector is located in the region ② as shown in FIG. 3, the reference vectors are E and 2E, and the (U, V) switching pair representing E is ( There are three redundancies of 1,0), (2,1), and (3,2) .In the case of (1,0), the charge / discharge state of the capacitor is DDC, and capacitor 1 is discharged and capacitor 2 is Discharge, capacitor 3 means to charge.

Meanwhile, the conventional spatial vector modulation method selects two adjacent reference vectors according to the position of the command voltage to determine the switching pattern to follow the average of the command voltage during the switching period. For example, if the reference vector is located at ①, the reference vectors are 2E and 3E, and the switching pair of (U, V) representing this is (2,0), (3,0), (3,1) As shown in FIG. 4, the duty of each switching pair is adjusted during one switching period to follow the command voltage on average.

However, according to this control technique, when the (U, V) switching state is (2,0), (3,0), (3,1), the charge / discharge state of the capacitor becomes DCC, CCC, CCD, respectively. Therefore, capacitor 2 is always in a charged state.

Especially, in case of PWM converter controlling power factor to 1, the phase of command voltage and input current is similar, so when the command voltage is located at ①, the charge and discharge current of the input current and capacitor is the largest, and the command voltage is located in a different area. Even if capacitor 2 is discharged only (for example, when the reference voltage is located at ③), this deviation cannot be completely eliminated.

That is, due to the characteristics of the multilevel converter, when the reference vector is selected as two adjacent vectors according to the conventional spatial vector modulation method and the switching state is implemented, the voltage deviation of the capacitor cannot be removed.

Figure 5 shows the voltage deviation of the capacitor when operating in the conventional manner, Vs and Is represents the input voltage and input current, respectively, Vdc is the total voltage of the DC-link capacitor, Vdc1 ~ Vdc3 is capacitor 1 ~ The voltage aspect of 3 is shown. As shown in FIG. 5, as time passes, Vdc2 increases to increase the voltage deviation.

FIG. 6 is a block diagram illustrating an apparatus in which a method of controlling a single-phase NPC multilevel PWM converter according to an embodiment of the present invention is performed. The controller 100, the command voltage output unit 200, and PWM generation and dead time are shown. time) compensating unit 300.

The command voltage output unit 200 receives the input voltage, the input current and the total voltage of the DC-link capacitor and outputs the command voltage Vc *. The command voltage output unit 200 is a general dq synchronous coordinate system-based voltage / current controller, and can output the command voltage by performing a dq conversion, etc., since the conventional device and control method can be used as it is, the present invention The detailed description thereof will be omitted.

The control unit 100 calculates a reference vector duty according to the single-phase NPC multilevel PWM converter control method according to the present invention to be described later, and outputs a signal according to the PWM generation and dead time compensation unit 300. ) Can output a PWM signal.

The PWM generation and dead time compensator 300 may compensate for a dead time of each switching duty according to a signal input from the controller 100 and output a PWM signal. In the case of the PWM generation and dead time compensator 300, a conventional apparatus and a control method may be used as it is, and thus the detailed description thereof will be omitted.

7 is a flowchart illustrating a method for controlling a single-phase NPC multilevel PWM converter according to an embodiment of the present invention. A single-phase NPC multilevel PWM converter control method according to the present invention will be described in detail with reference to the following.

The controller 100 first receives a capacitor voltage (S10). That is, the control unit 100, in order to eliminate the voltage deviation between the capacitors, the voltage Vdc1. Input Vdc2, Vdc3. In this case, the voltage of each capacitor may be measured by a voltage measuring circuit (sensor) or the like.

Subsequently, the controller 100 calculates the capacitor voltage deviation, and accordingly determines the clamping mode (S20).

In detail, the controller 100 determines the clamping mode by comparing voltages of the plurality of capacitors with a reference value.

For example, in the case of a four-level converter, the control unit 100 selects a voltage having a large difference from the reference value (Vdc_ref / 3, in the case of N level, Vdc_ref / (N-1)) among Vdc1 and Vdc3. Where Vdc_ref is equal to Vdc.

The controller 100 selects the upper clamping mode when the selected voltage is Vdc1 and the difference between the reference value and Vdc1 (Vdc_ref / 3-Vdc1) is greater than zero. On the other hand, the control unit 100 selects the lower clamping mode when the difference is less than zero. In addition, the controller 100 selects the lower clamping mode when the selected voltage is Vdc3 and the difference between the reference value and Vdc3 (Vdc_ref / 3-Vdc3) is greater than zero, and selects the upper clamping mode when the difference is smaller than zero. When analyzing the charging and discharging pattern of the capacitor according to the clamping mode, the upper clamping mode tends to increase Vdc1 and decrease Vdc3, and the lower clamping mode tends to decrease Vdc1 and increase Vdc3.

In the case of N-level capacitors, when N is even, the clamping mode is determined by comparing all of the capacitors located above the capacitor and the capacitors located below the capacitor with the reference value when N is an even number. . When N is odd, all the capacitors are compared with the reference value to determine the clamping mode by dividing the upper and lower positions.

Select the voltage value that has the largest difference among the voltages of the capacitors compared to the reference value, and consider the capacitor's position according to the clamping mode according to the clamping mode. The clamping mode can be determined according to the sign of the difference of the values.

Thereafter, the controller 100 calculates a capacitor voltage deviation compensation value (S30). That is, the controller 100 performs compensation control proportional to the voltage deviation between the capacitors, and calculates the duty compensation value of the reference vector as the output.

For example, a four-level converter has three capacitors, requiring two compensation controls. There are various methods of implementing two voltage deviation compensation, but in this embodiment, a control to compensate for the difference between (Vdc1 + Vdc2) / 2 and Vdc3 and a control to compensate for the difference between Vdc1 and (Vdc2 + Vdc3) / 2. Do this. This is because only the intermediate vector (E, 2E) except the outer reference vector (0, 3E) among the reference vectors generates a voltage deviation between the capacitors. That is, it is more intuitive to compensate for the voltage deviation by using the capacitor charge / discharge mode corresponding to each intermediate vector, and it is also easy to expand to the general high-dimensional multilevel.

In other words, the controller 100 compensates for a difference between the voltage of the capacitor at one end of the capacitors connected in series and the average voltage of the remaining capacitors (ie, capacitors except the capacitor at one end), the other of the capacitors connected in series. A compensation value including a compensation value for compensating for the difference between the voltage of the capacitor at one end and the average voltage of the remaining capacitors (that is, capacitors except the capacitor at the other end) can be calculated.

However, as the level of the multilevel increases, additional compensation values other than these compensation values should be calculated. That is, in the case of the N-level converter (N-2) voltage deviation compensation parameters are required, a more detailed description thereof will be described later.

The voltage deviation compensation control may be performed by a proportional integral control method, and may be implemented through a software method performed by the controller 100 or a deviation compensator (proportional integral controller) included in the controller 100.

In this case, the compensation deviation parameter (capacitor voltage deviation compensation value) may be expressed as follows.

PI means the proportional integral controller and outputs the difference from the second value based on the first value in parentheses through the proportional integral calculation. In addition, dcomp12_3 is a control parameter to compensate for the difference between (Vdc1 + Vdc2) / 2 and Vdc3, and dcomp1_23 is a control parameter to compensate for the difference between Vdc1 and (Vdc2 + Vdc3) / 2.

Subsequently, the controller 100 calculates a reference vector duty according to the command voltage position (S40).

First, the control unit 100 is configured to select a reference vector according to the position of the command voltage vector. In the present invention, the control unit 100 does not select only two reference vectors adjacent to the position of the command voltage vector. It is configured to select a vector. This may be represented by a multi-neighboring reference vector (MNRV) method, and accordingly, the control unit 100 is configured to select three or more reference vectors in at least a portion of the region.

For example, when Vc * is located in the region ①, the controller 100 selects E, 2E, and 3E as reference vectors. When E is selected, (1,0) and (3,2) can be selected as the (U, V) switching pairs, and the switching vectors DDC and CDD may serve to discharge the capacitor 2. Therefore, when E is used as the reference vector together with 2E and 3E, the voltage of capacitor 2 can be suppressed from rising, and the vector of the E, 2E, and 3E can be properly adjusted to follow the magnitude of the command vector on average. .

In addition, the controller 100 may use the clamped switching state to reduce the number of switching duplications and minimize switching losses. This means that only (3, x), (x, 3), (0, x), and (x, 0) are used among (U, V) switching pairs that can represent reference vectors. (3, x) means that the U phase is clamped with a positive DC rail, and (x, 3) means that the V phase is clamped with a positive DC rail. Similarly, (0, x) and (x, 0) mean that the U and V phases are clamped to the negative DC rail, respectively.

In detail, the controller 100 may select a reference vector according to a table expressed below.

For example, when the upper clamping mode is selected, the reference vector when the command voltage is located in the region ② is selected as 0, E, 2E, 3E, and this is a switching pair (3,0), (3,1), (3 It can be expressed by a combination of (2), (3,3), (3,2), (3,1), and (3,0).

At this time, the regions ① and ⑥, the regions ② and ⑤, the regions ③ and ④ are symmetric with each other, and the charge and discharge modes are horizontally symmetric with respect to the upper clamping mode and the lower clamping mode. For example, (3,1) and (2,0) vectors are switching pairs representing 2E reference vectors in the upper clamping and lower clamping modes, respectively, but the charge and discharge patterns of the capacitors are horizontally symmetrical with the CCD and DCC.

The selection of the reference vector and the selection of the switching pair may be performed in such a manner that the controller 100 reads a table designed in advance and selects the reference vector and the corresponding switching pair according to the position of the command voltage vector.

Subsequently, the controller 100 calculates the duty of each reference vector based on one of the selected reference vectors. For example, when the command voltage is located in the region ①, the control unit 100 selects E, 2E, and 3E as reference vectors, and calculates the duty of the 2E and 3E vectors according to the following equation based on the E vector. do.

Where dE, d2E, and d3E are the duty of the E, 2E, and 3E vectors, respectively, and VE, V2E, and V3E are the voltage magnitudes of E, 2E, and 3E, respectively, equal to Vdc_ref / 3, Vdc_ref * 2/3, and Vdc_ref, respectively. .

That is, when three or more reference vectors are selected, the controller 100 first calculates the duty of the reference vector closest to zero other than zero among the selected reference vectors, and calculates the duty of the remaining reference vectors based on this. Can be.

The equation is applied according to the clamping mode determined in step S20, and the output of the PI control (dcomp12_3 or dcomp1_23) compensating for the voltage deviation is calculated while calculating the duty of the reference vectors satisfying the magnitude of the command voltage vector Vc *. By adjusting the duty of the reference vector 2E in the direction of reducing the voltage deviation of the entire capacitor. For example, when (Vdc1 + Vdc2) / 2> Vdc3 in the upper clamping mode, dcomp12_3 increases to decrease d2E. In the upper clamping mode, d2E is the duty of the switching pair (3,1), which charges Vdc1 and Vdc2 and discharges Vdc3. As a result of the reduced d2E, Vdc1 and Vdc2 decrease and Vdc3 increase. As a result of negative feedback, dcomp12_3 stabilizes and capacitor voltage deviation stabilizes. Control is performed in the same way in the lower clamping mode.

On the other hand, when the command voltage vector is located in the region ②, the controller 100 selects 0, E, 2E, and 3E as reference vectors. The reason why the reference vector range of the region ② is selected to be wider than that of the region ① is to increase the common reference vectors of the regions ① and ② to achieve a smooth transition when moving the region.

That is, the region where the command voltage vector is located is divided into at least three sections, and the number of reference vectors selected in the outermost section (area ① at 4 levels) is selected from the next section (area ② at 4 levels). It may be less than or equal to the number of reference vectors.

At this time, the duty of each reference vector is calculated according to the following equation.

That is, the controller 100 calculates the duty of the 0, 2E, and 3E vectors according to the above equation based on the E vector. Where d0, dE, d2E, and d3E are the duty of the vectors 0, E, 2E, and 3E, respectively, and V0, VE, V2E, and V3E are the voltage magnitudes of 0, E, 2E, and 3E, respectively, 0, Vdc_ref / 3, Vdc_ref * 2/3 means Vdc_ref.

Meanwhile, according to the symmetry described above, the reference vector and the duty of the reference vectors when the command vector corresponds to the regions ⑤ and ⑥ are determined to be the same as the regions ② and ①, respectively.

Finally, since regions ③ and ④ have relatively small amounts of current, they can be determined through DPWM (Discontinuous PWM) modulation using two neighboring reference vectors (TNRVs). The duty of the concrete reference vector is calculated according to the following equation.

Here, Vcu * and Vcv * refer to the command voltages on U and V divided by the command voltage Vc *, respectively.

Thereafter, the control unit 100 outputs a PWM signal through the PWM generation and dead time compensation unit 300 (S50).

That is, when the reference vector and its duty are determined according to the region where the command voltage is located, the controller 100 may generate a PWM signal. In this case, since the PWM signal generation can be performed as in the conventional method, after considering the dead-time as shown in FIG. 4, the PWM signal may be output to the gate as in the space vector modulation method in which the effective voltage is located.

8 is a flowchart illustrating selection of a reference vector in a method of controlling a single-phase NPC multilevel PWM converter according to an embodiment of the present invention.

The MNRV DPWM at four levels described above can be extended to a general N level NPC converter. That is, by analyzing the voltage variation of the DC-link capacitor for each multi-level, the MNRV range can be selected according to the position of the command voltage, and the capacitor voltage deviation compensation parameter can be designed.

FIG. 8 shows MNRVs selected according to the command voltage range to apply the proposed MNRV DPWM for the 3 level, 4 level, 5 level and 6 level NPC PWM converters.

However, at the 3rd level, it can be implemented by utilizing two adjacent reference vectors.For 5th level, for example, if the command voltage vector belongs to the areas ① and ②, the MNRV belongs to E to 4E and the area ③. MNRV may be 0 to 3E, 0 and E may be used as reference vectors for the region ④, and the remaining regions ⑤ to ⑧ may be determined by symmetry.

In case of the 6th level, when the command voltage vector belongs to the areas ① and ②, MNRV is from 2E to 5E, and if it belongs to the areas ③ and ④, MNRV is from 0 to 4E and 0 and E are used as reference vectors. The remaining area can be determined by symmetry.

Specifically, the general rule for selecting the MNRV for each command voltage position is as follows. Compensation parameters for controlling the capacitor voltage deviation require (N-2) N levels. These compensation parameters are determined from the charge / discharge state of the capacitor of the reference step voltage (reference vector), and MNRV should be selected to include all compensation parameters independent of each other so that the capacitor voltage deviation can be completely controlled regardless of the position of the command voltage vector. .

First, the charge and discharge states of the capacitor are analyzed according to the reference step voltage as follows. In the case of N level, the maximum step voltage is (N-1) * E, and the capacitor charge / discharge state at this time is CC… regardless of the clamping mode. CC charges all capacitors. The step voltage down one step is (N-2) * E and the capacitor charge / discharge state is CC… in the upper clamping mode. CD and DC in lower clamping mode. With CC, the outermost capacitor is put into discharge mode. In the upper clamping mode, the capacitor located at the bottom of the DC-link stage, and in the lower clamping mode, the capacitor located at the top of the DC-link stage changes from charging to discharging mode. The next step down voltage is (N-3) * E and the capacitor charge / discharge state is the upper clamping mode is CC…. CDD, DDC… in lower clamping mode. CC becomes. That is, whenever the stair voltage decreases one by one, the capacitor charge / discharge states change from charging to discharging one by one from the bottom of the DC-link stage in the upper clamping mode and one from the top of the DC-link stage in the lower clamping mode.

If this applies to all step voltages, there is a step voltage pair where the sum of the two step voltages is (N-1) * E, and the capacitor charge / discharge modes of the upper clamping mode and the lower clamping mode of these two stepping voltages are It is different but related to the same capacitor voltage compensation parameter.

That is, the two step voltages are cross oppositely coupled to each other, and there are (N-2) capacitor charge / discharge states that are independent of the entire step voltage. Since the capacitor charge / discharge states of voltage vectors horizontally symmetrical from left to right with respect to the center step voltage are related to each other, the independent charge / discharge state is the center reference step voltage ((N-1) / 2 * E, When N is even (N / 2-1) * E, N / 2 * E), only one region needs to be considered. Therefore, MNRV can be set to include independent duty compensation parameters (N-2) which are necessary to remove the voltage deviation of the capacitor for each region where the command voltage vector is located.

For example, in case of level 5, the capacitor charge / discharge states of the upper clamping mode of E and the lower clamping mode of 3E located at the symmetry point of 2E are CDDD and DCCC, respectively, except that the signs are different from each other, except that Vdc1 and (Vdc2 + Vdc3 + Vdc4) / It controls the voltage deviation of 3. Likewise, the charge and discharge states of the lower clamping mode of E and the upper clamping mode of 3E have different signs with DDDC and CCCD, respectively, to control the voltage deviation of (Vdc1 + Vdc2 + Vdc3) / 3 and Vdc4. In addition, the charge and discharge states of the upper clamping mode and the lower clamping mode of 2E are reversed by CCDD and DDCC, respectively, and thus the voltage deviations of (Vdc1 + Vdc2) / 2 and (Vdc3 + Vdc4) / 2 are related.

For level 5, three compensation parameters to control capacitor voltage deviation are required, and three independent compensation parameters are CDDD (DCCC) and (Vdc1 + Vdc2 + Vdc3) / of Vdc1 and (Vdc2 + Vdc3 + Vdc4) / 3. It is related to CCCD (DDDC) of 3 and Vdc4, CCDD (DDCC) of (Vdc1 + Vdc2) / 2 and (Vdc3 + Vdc4) / 2, and all of them must be used to ensure that the capacitor voltage deviation is completely maintained regardless of the position of the reference voltage vector. Can be controlled.

Therefore, if the command voltage vector belongs to the areas ① and ②, the reference vectors 2E and 3E must be included in order to use all three independent compensation parameters, so the MNRV must be in the range of E to 4E including 2E and 3E. On the other hand, if the command voltage vector is located in the region ③, E and 2E must be included in order to utilize all three compensation parameters independent of each other, so the total MNRV must be in the range of 0 to 3E including E and 2E.

Since the outermost vector (0, (N-1) * E) of the reference vectors does not affect the capacitor voltage deviation, the capacitor voltage deviation compensation parameter is independent of the capacitor charge / discharge states of the reference vectors located in the center except the outermost vector. Is determined from. In case of 5th level, there are three independent charge / discharge states: CDDD (DCCC), CCDD (DDCC), CCCD (DDDC), and similarly to equation (1), a compensation parameter proportional to voltage deviation can be designed through PI controller. Can be.

FIG. 9 is a circuit diagram illustrating a single-phase NPC four-level PWM converter for dual-interlacing mode, and FIG. 10 is an operating performance when a single-phase NPC multilevel PWM converter control method according to an embodiment of the present invention is applied to a four-level NPC converter. FIG. 11 is an exemplary diagram illustrating an operation performance when the single-phase NPC multilevel PWM converter control method according to an embodiment of the present invention is applied to a 5-level NPC converter.

The single-phase NPC PWM multilevel converter may be operated in a stand-alone mode, but may also be operated in a dual-interlacing mode as shown in FIG. 9. The dual-interlacing mode can reduce the ripple of the entire input current by dividing the input into two to control the current of each boost inductor by zigzag. However, since the details of the stand-alone mode and the dual-interlacing mode correspond to well-known technologies, detailed descriptions thereof will be omitted.

10 is applied to the control method according to the present invention to a four-level NPC converter, operating in a dual-interlacing mode, each waveform is Vs and Is; Vdc, Vdc1, Vdc2, Vdc3; Expanded Vdc1, Vdc2, Vdc3; Voltage deviation compensation outputs dcomp1_23 and dcomp12_3; Clamping modes 1 and 2; Carrier 1, 2, 3 (transmission wave 1, 2, 3), Vg_U1, Vg_U2, Vg_U3 (PWM command voltage corresponding to upper switch on U), Vg_V1, Vg_V2, Vg_V3 (PWM command corresponding to upper switch on V) Modulation voltage); Vuo, Vvo (U, V phase leg voltage); Corresponds to Vuv.

According to the simulation results, the power factor of Vs and Is is over 0.99, the THD of Is is about 8%, and according to the pattern of capacitor voltage deviation, the clamping mode is alternated every half of the power voltage so that only U phase is switched and V phase is switched. It can be confirmed that it is suppressed. The switching duty of the reference vectors for each region is corrected by the dcomp parameter determined as the voltage deviation compensation output value, thereby confirming that the expected converter command voltage and capacitor voltage deviation (about 12V) are maintained.

In addition, Figure 11 is applied to the control method according to the present invention to a five-level NPC converter, in the five-level capacitor is four DC-link capacitors, three voltage deviation compensator is required, three compensation parameters, the capacitor voltage deviation is approximately It is well controlled around 12V, and if you observe the converter input voltage Vuv, you can see that it is divided into 5 steps by 0, E, 2E, 3E, and 4E.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art to which the art belongs can make various modifications and other equivalent embodiments therefrom. Will understand. Therefore, the technical protection scope of the present invention will be defined by the claims below.

100: control unit
200: command voltage output unit
300: PWM generation and dead time compensation

Claims (9)

Receiving, by the controller, a voltage of each capacitor of the output terminal;
Calculating, by the controller, a capacitor voltage deviation based on the input voltage, and determining a clamping mode;
Calculating, by the control unit, a capacitor voltage deviation compensation value;
Selecting a reference vector by the controller, selecting a reference vector according to a region in which a command voltage vector is located, and selecting three or more reference vectors in at least a portion of the region;
Calculating, by the controller, the duty of each selected reference vector in consideration of the determined clamping mode, the voltage deviation compensation value, and the command voltage vector; And
And controlling the PWM signal generation according to the calculated duty of each reference vector by the controller.
And the control unit is configured to use only the clamped switching state among the U and V switching pairs representing each reference vector.
The method of claim 1,
The region in which the command voltage vector is located is divided into at least three sections, and the number of reference vectors selected in the outermost section is less than or equal to the number of reference vectors selected in the next section. .
delete The method of claim 1,
The control unit determines the clamping mode by comparing the voltage of the capacitor connected in series with a reference value, in the case of an even level converter, compares the reference value with the remaining capacitors except for the capacitor located in the center of the capacitor connected in the series, and in the case of an odd level converter A method of controlling a single-phase NPC multilevel PWM converter, characterized in that the clamping mode is determined by comparing a capacitor with a reference value.
The method of claim 4, wherein
The control unit selects a voltage having a large difference from the reference value among the voltages of the capacitor compared with the reference value, and determines the clamping mode in consideration of the sign of the difference between the reference value and the selected voltage. PWM converter control method.
The method of claim 1,
And the control unit calculates (N-2) voltage deviation compensation values in the case of an N-level converter.
The method of claim 6,
The control unit compensates for the difference between the voltage of the capacitor at one end of the capacitor connected in series and the average voltage of the remaining capacitors, and the difference between the voltage of the capacitor at the other end of the capacitor connected in series and the average voltage of the remaining capacitors. Single-phase NPC multi-level PWM converter control method characterized in that for calculating the compensation value.
The method of claim 1,
The controller, when selecting three or more reference vectors, first calculates the duty of the reference vector closest to zero other than zero among the selected reference vectors, and calculates the duty of the remaining reference vectors based on the reference vector. Single phase NPC multilevel PWM converter control method.
The method of claim 8,
The control unit calculates the duty of the reference vector as a reference based on the voltage magnitude of each of the selected reference vector, the magnitude of the command voltage vector, and the voltage deviation compensation value. .

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