KR101897389B1 - Content addressable memory having magnetoresistive memory - Google Patents

Abstract

A content addressable memory device using a magnetoresistive memory and a plurality of transistors is disclosed. The content addressable memory device includes magnetoresistive memories and a first transistor connecting between the sense amplifier and a node between the magnetoresistive memories. Here, a search line is connected to one end of one of the magnetoresistive memories, a search line bar is connected to one end of another magnetoresistive memory, and a voltage is applied to the search line and the search line bar during data search.

Description

{CONTENT ADDRESSABLE MEMORY HAVING MAGNETORESISTIVE MEMORY USING MAGNETIC RESISTANCE MEMORY}

The present invention relates to a content addressable memory device using a magnetoresistive memory, for example, an MTJ.

Conventional content addressable storage uses static storage (SRAM) to store data. Specifically, the content addressable storage device stores the address of the data in the static storage device, and determines whether the address of the externally input data matches the stored address.

However, when SRAM is used, data stored in the SRAM is erased when the external power supply is interrupted. As a result, it is necessary to restore the SRAM to the required data when the power is supplied again.

In addition, since the SRAM is composed of only a plurality of transistors, it is not suitable for an application requiring a highly integrated memory.

KR 10-0136480 B

The present invention provides a magnetoresistive memory and a content addressable memory device using a plurality of transistors.

According to an aspect of the present invention, there is provided a content addressable memory device including: magnetoresistive memories; And a first transistor connecting a node between the magnetoresistive memories and the sense amplifier. Here, a search line is connected to one end of one of the magnetoresistive memories, a search line bar is connected to one end of another magnetoresistive memory, and a voltage is applied to the search line and the search line bar during data search.

A content addressable memory device according to another embodiment of the present invention includes an array including a plurality of cells and a sense amplifier coupled to the cells. Each cell comprising magnetoresistive memories; And a first transistor connecting a node between the magnetoresistive memories and the sense amplifier. Here, a search line is connected to one end of one of the magnetoresistive memories, a search line bar is connected to one end of another magnetoresistive memory, and a voltage is applied to the search line and the search line bar during data search.

A content addressable memory device according to another embodiment of the present invention includes non-volatile resistance memories; And a first transistor coupled to the node between the non-volatile memories. Here, a search line is connected to one end of one of the nonvolatile memories, a search line bar is connected to one end of the other magnetoresistive memory, a voltage is applied to the search line and the search line bar during data search, Current flows through the transistor to the non-volatile resistive memories.

The content addressable memory device according to the present invention is implemented by a magnetoresistive memory, for example, an MTJ and transistors. As a result, there is no problem of storing data again in the magnetoresistive memory, It can be suitable for the applications that need it and it is possible to search fast.

In addition, the sources of the transistors are connected to the same node, which can reduce the size of the content addressable memory, and even if the voltage of the source node changes due to parasitic resistances and parasitic capacitors during the search, .

In addition, since the contents addressable memory device identifies a plurality of cells at the same time, it has a strong characteristic against process dispersion, that is, reliability can be improved.

1 is a circuit diagram schematically showing an array of contents addressable memory devices according to an embodiment of the present invention.
2 is a circuit diagram showing one cell according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating an operation of a content addressable memory device when do not care according to an embodiment of the present invention. FIG.
4 is a circuit diagram illustrating a content addressable memory device including a plurality of arrays.
5 is a timing diagram illustrating the flow of signals in a content addressable memory device in accordance with an embodiment of the present invention.
6 is a timing diagram showing the simulation result of the content addressable memory device.

As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. In this specification, the terms "comprising ", or" comprising "and the like should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps. Also, the terms "part," " module, "and the like described in the specification mean units for processing at least one function or operation, which may be implemented in hardware or software or a combination of hardware and software .

Field of the Invention The present invention relates to a content-addressable memory (CAM), particularly a tenary CAM (TCAM) used for fast speed searching, and a nonvolatile memory such as a magnetoresistive memory such as a magnetic tunnel junction Tunnel Junction, MTJ). In this case, the necessary information can be quickly searched by the write and fast read operations of the nonvolatile memory.

Thus, the content addressable memory of the present invention can be used in applications that require very high speeds, and can be particularly useful for searching memory addresses in a random access memory (RAM).

According to one embodiment, the content addressable memory device of the present invention may use a plurality of MTJs, and the sources of the MTJs may be connected to the same node to implement a smaller size. In addition, the sensing operation may not be affected even if the voltage of the source node is changed by parasitic resistance or parasitic capacitance during the search operation.

According to another embodiment, the content addressable memory device of the present invention identifies data of a plurality of cells at the same time as described later, and as a result, the content addressable memory device can have robust characteristics in the process spread, and reliability can be improved.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram schematically showing an array of contents addressable memory devices according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing one cell according to an embodiment of the present invention. FIG. 3 is a diagram illustrating operation of a content addressable memory device in a do not care state according to an embodiment of the present invention, and FIG. 4 is a circuit diagram illustrating a contents addressable memory device including a plurality of arrays . FIG. 5 is a timing diagram showing the flow of signals in the content addressable memory device according to an embodiment of the present invention, and FIG. 6 is a timing diagram showing a simulation result of the content addressable memory device.

Referring to Figures 1 and 4, a content addressable memory, in particular a TCAM, comprises a plurality of arrays 100.

Each array 100 includes a plurality of cells 102 and a sense amplifier 104.

The cells 102 all have the same structure, for example, the structure shown in Fig. Since the cells 102 all have the same structure, only one cell 102 will be described below.

2, a cell 102 includes a first MTJ 200, a second MTJ 202, and three transistors M1, M2, and M3.

One end of the first MTJ 200 is connected to a search line SL and one end of the second MTJ 200 is connected to a search line (SLB). For example, when one end of the first MTJ 200 is connected to the power supply voltage V _DD , one end of the second MTJ 202 is connected to the ground. When one end of the first MTJ 200 is connected to the ground, 2 One end of the MTJ 202 may be connected to the power supply voltage V _DD .

According to one embodiment, the search for data stored in the MTJs 202 and 202 may be accomplished by applying voltages to the search line SL and the search line bar SLB. A detailed description thereof will be described later.

The first transistor M1 is, for example, an NMOS transistor. The gate of the first transistor M1 is connected to the node n1 between the MTJs 200 and 202 and the drain thereof is connected to one input terminal (positive input terminal) of the sense amplifier 104, M2. ≪ / RTI >

The second transistor M2 is, for example, an NMOS transistor. The gate of the second transistor M2 is connected to a bit line BL and a reference voltage V _REF is input. The source of the second transistor M2 may be connected to the source of the first transistor M1 and the drain of the second transistor M2 may be connected to the other input terminal of the sense amplifier 104. [

The sources of the transistors M1 and M2 may be connected to the node n2 and the node n2 may be connected to the ground.

The gate of the third transistor M3 is connected to the word line WL, the source thereof is connected to the bit line BL, and the drain thereof is connected to the node n1.

The operation of the content addressable memory having the structure of the cell 102 will be described with reference to Table 1 and FIG.

Hereinafter, it is assumed that data stored in the MTJs 200 and 202 is '0'.

In order to search for data stored in the MTJs 200 and 202, a voltage application operation corresponding to data '1' and a voltage application operation corresponding to data '0' may be sequentially performed. In this case, the transistor M3 is turned off by the voltage of the word line WL.

First, a reference voltage V _REF is applied to the bit line BL, a power source voltage V _DD is applied to the search line SL, (SLB).

That is, the reference voltage V _REF is applied to the gate of the transistor M2, the power supply voltage V _DD is applied to one end of the first MTJ 200, and the ground voltage is applied to one end of the second MTJ 202 . As a result, as shown in FIG. 2, the first current i ₁ flows from the sense amplifier 104 to the MTJs 200 and 202 through the transistor M1, and the first current i ₁ flows from the sense amplifier 104 to the transistors M2 The second current i ₂ flows through the MTJs 200 and 202. [

In this case, the sense amplifier 104 may generate the output OUT corresponding to "mismatch (data discrepancy)" by comparing the first current i ₁ and the second current i ₂ . For example, if the first current i ₁ is less than the second current i ₂ , the sense amplifier 104 may generate an output OUT corresponding to "mismatch". That is, it is confirmed that the data stored in the MTJs 200 and 202 is not '1'.

Next, a reference voltage V _REF is applied to the bit line BL, a ground voltage is applied to the search line SL, and a voltage applied to the search line SLB is applied to the bit line BL. _{Apply the} power supply voltage (V _DD ).

That is, the reference voltage V _REF is applied to the gate of the transistor M2, the ground voltage is applied to one end of the first MTJ 200, and the power supply voltage V _DD is applied to the other end of the second MTJ 202 . As a result, as shown in FIG. 2, the first current i ₁ flows from the sense amplifier 104 to the MTJs 200 and 202 through the transistor M1, and the first current i ₁ flows from the sense amplifier 104 to the transistors M2 The second current i ₂ flows through the MTJs 200 and 202. [

In this case, the sense amplifier 104 may compare the first current i ₁ and the second current i ₂ to generate an output OUT corresponding to "match (data match)". For example, if the first current i ₁ is greater than the second current i ₂ , the sense amplifier 104 may generate an output OUT corresponding to "match". That is, it can be confirmed that the data stored in the MTJs 200 and 202 is '0'.

Next, it is assumed that the data stored in the MTJs 200 and 202 is '1'.

In order to search for data stored in the MTJs 200 and 202, a voltage application operation corresponding to data '1' and a voltage application operation corresponding to data '0' may be sequentially performed. In this case, the transistor M3 is turned off by the voltage of the word line WL.

First, a reference voltage V _REF is applied to the bit line BL, a power source voltage V _DD is applied to the search line SL, (SLB).

That is, the reference voltage V _REF is applied to the gate of the transistor M2, the power supply voltage V _DD is applied to one end of the first MTJ 200, and the ground voltage is applied to the other end of the second MTJ 202 . As a result, as shown in FIG. 2, the first current i ₁ flows from the sense amplifier 104 to the MTJs 200 and 202 through the transistor M1, and the first current i ₁ flows from the sense amplifier 104 to the transistors M2 The second current i ₂ flows through the MTJs 200 and 202. [

In this case, the sense amplifier 104 may compare the first current i ₁ and the second current i ₂ to generate an output OUT corresponding to "match". For example, if the first current i ₁ is less than the second current i ₂ , the sense amplifier 104 may generate an output OUT corresponding to "match". That is, it can be confirmed that the data stored in the MTJs 200 and 202 is '1'.

Next, a reference voltage V _REF is applied to the bit line BL, a ground voltage is applied to the search line SL, and a voltage applied to the search line SLB is applied to the bit line BL. _{Apply the} power supply voltage (V _DD ).

That is, the reference voltage V _REF is applied to the gate of the transistor M2, the ground voltage is applied to one end of the first MTJ 200, and the power supply voltage V _DD is applied to the other end of the second MTJ 202 . As a result, as shown in FIG. 2, the first current i ₁ flows from the sense amplifier 104 to the MTJs 200 and 202 through the transistor M1, and the first current i ₁ flows from the sense amplifier 104 to the transistors M2 The second current i ₂ flows through the MTJs 200 and 202. [

In this case, the sense amplifier 104 may generate the output OUT corresponding to "mismatch " by comparing the first current i ₁ and the second current i ₂ . For example, if the first current i ₁ is greater than the second current i ₂ , the sense amplifier 104 may generate an output OUT corresponding to "mismatch". That is, it can be confirmed that the data stored in the MTJs 200 and 202 is not '0'.

In summary, the content addressable memory device of the present invention can search for data stored in one cell 102 by applying a voltage to the search line SL and the search line bar SLB. At this time, the contents addressable memory device can apply a voltage corresponding to data '1' and sequentially apply a voltage corresponding to data '0'. Of course, the contents addressable memory device may apply a voltage corresponding to data '0' and sequentially apply a voltage corresponding to data '1'.

According to another embodiment, if it is determined that the data match according to the application of the voltage corresponding to the specific data, the voltage corresponding to the other data may not be applied.

Hereinafter, the data search process in the TCAM will be described. TCAM requires 'do not care' as well as data '1' and '0'. Since the data '1' and '0' are described above, only the operation of the cell 102 in the case of 'do not care' will be described in detail with reference to Table 1 and FIG.

In the case of 'do not care', the ground voltage is applied to the bit line BL as shown in Table 3 and FIG. 3, and the ground voltage is applied to both the search line SL and the search line bar SLB. In this case, the sense amplifier 104 may generate an output (OUT) corresponding to 'match' regardless of the data stored in the MTJs 200 and 202. That is, it is determined that the data always coincides.

In the meantime, although the data search in one cell 102 has been described above, the actual circuit will be implemented in the array 100 as shown in FIG. Let's look at the operation of searching for data when the TCAM has an array structure. In FIG. 4, one array 100 includes eight cells 102.

Referring to FIG. 5, after a precharge operation is performed, a data search operation is performed.

The reference voltage V _REF is applied to the bit line BL and the ground voltage is applied to the word line WL to turn off the transistor M3 of the cells 102 and the search line SL The power supply voltage V _DD and the ground voltage are sequentially applied.

In the array structure, eight bits of operation are performed in eight cells 102 at a time. For example, it is assumed that data '11110000' is stored in the MTJs of eight cells 102. In this case, voltages corresponding to data '11111111' may be applied to eight cells 102, and voltages corresponding to data '11111110' may be applied to eight cells 102. This sequential voltage application process can be performed until voltages corresponding to data '00000000' are applied to the eight cells 102. Of course, in the case of TCAM, the operation corresponding to 'do not care' is also performed.

For example, when the data corresponds to the data '11110000', the power source voltage V _DD is applied to the search line SL of the first cell, the ground voltage is applied to the search line bar SLB, The power source voltage V _DD is applied to the search line SL and the ground voltage is applied to the search line bar SLB and the power source voltage V _DD is applied to the search line SL of the third cell, The power source voltage V _DD is applied to the search line SL of the fourth cell and the ground voltage is applied to the search line bar SLB. When the ground voltage is applied to the search line SL of the fifth cell and the power supply voltage V _DD is applied to the search line bar SLB and the ground voltage is applied to the search line SL of the sixth cell, applying the power supply voltage (V _DD) to the line bar (SLB), and, the seventh and the power supply voltage (V _DD) to search line (SL) is the ground voltage and the search line bar (SLB) to the application of the cell, the eighth The ground voltage is applied to the search line SL of the cell and the power supply voltage V _DD is applied to the search line bar SLB. As a result, a first current and a second current corresponding to data '11110000' flow from the sense amplifier 104 to the MTJs 200 and 202 of the eight cells 102.

The sense amplifier 104 may compare the first current and the second current to output a comparison result OUT. In this case, it is determined whether the data match through the voltage of the node ML. The output terminal of the sense amplifier 104 is connected to the gate of the transistor M4 and the drain of the transistor M4 is connected to the transistor through which the clock CLK is inputted as the control signal. ) May be connected to the source of the detection signal SEN as a control signal. During the data search operation, the clock (CLK) has a high logic, and the detection signal (SEN) can have a high logic only in a part of the search interval.

In summary, in the data search operation of the TCAM of the present invention, the TCAM simultaneously applies voltages to all the cells 102, not to apply voltages to the cells 102 of one array 100, It is possible to judge whether or not the data on the data is consistent. That is, the TCAM searches data of all the cells included in one array 100 at a time, and as a result, the search speed can be fast.

Of course, in the case of 'do not care', a ground voltage may be applied to both the search line SL and the search line bar SLB of all the cells 102.

Referring to FIG. 6, an operation of sequentially searching '11111111', 'x1111111' and '00000000' in the respective arrays 100 stored in the data '11111111' and '0111111' is performed. As a result, only the ML value of the array 100 in which '11111111' is stored in the first operation is maintained at 1, and the ML values of both arrays in which '11111111' and '01111111' are stored in the second result are maintained at 1 . In the last operation, the ML values of both arrays 100 were changed to zero.

On the other hand, the components of the above-described embodiment can be easily grasped from a process viewpoint. That is, each component can be identified as a respective process. Further, the process of the above-described embodiment can be easily grasped from the viewpoint of the components of the apparatus.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention as defined by the appended claims. Should be regarded as belonging to the following claims.

100: cell 102: array
104: sense amplifier 200, 202: MTJ

Claims (12)

Magnetoresistive memories;
A first transistor connecting a node between the magnetoresistive memories and a sense amplifier; And
And a second transistor connected between the node and the sense amplifier,
A search line is connected to one end of one of the magnetoresistive memories and a search line bar is connected to one end of the other magnetoresistive memories and a voltage is applied to the search line and the search line bar during data search,
Wherein the first transistor is coupled to the positive input of the sense amplifier and the second transistor is coupled to the negative input of the sense amplifier. The memory of claim 1, wherein the magnetoresistive memory is a magnetic tunnel junction (MTJ). delete 2. The method of claim 1, wherein the node is connected to the gate of the first transistor, a reference voltage is input to the gate of the second transistor through a bit line, and the sources of the transistors are interconnected. Memory. 2. The method of claim 1, wherein when a data '1' is searched, a power supply voltage is applied to the search line, a ground voltage is applied to the search line bar, the ground voltage is applied to the search line during data '0' Wherein the power supply voltage is applied to the bar and the ground voltage is applied to both the search line and the search line bar during a 'do not care' search. An array comprising a plurality of cells and a sense amplifier coupled to the cells,
Each cell comprising magnetoresistive memories;
A first transistor connecting a node between the magnetoresistive memories and a sense amplifier; And
And a second transistor connected between the node and the sense amplifier,
A search line is connected to one end of one of the magnetoresistive memories and a search line bar is connected to one end of the other magnetoresistive memories and a voltage is applied to the search line and the search line bar during data search,
Wherein the first transistor is coupled to the positive input of the sense amplifier and the second transistor is coupled to the negative input of the sense amplifier. delete delete 7. The method of claim 6, wherein the node is coupled to the gate of the first transistor, a reference voltage is input to the gate of the second transistor through a bit line, and the sources of the transistors are interconnected. Memory. The content addressable memory device according to claim 6, wherein voltages are applied to search lines and search line bars of all cells during data search. 11. The method of claim 10, wherein in a particular cell, a power supply voltage is applied to the search line and a ground voltage is applied to the search line during a bit '1' search and the ground voltage is applied to the search line Wherein the power supply voltage is applied to the search line bar and the ground voltage is applied to both the search line and the search line bar during a 'do not care' search.






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