KR101833849B1 - Semiconductor devices and methods of fabricating the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided. Forming a gate pattern on a substrate including an emmos region and a PMOS region, forming a spacer structure on a sidewall of the gate pattern, and forming a recess in the exposed substrate of the PMOS region exposed by the gate pattern and the spacer structure Regions can be formed. A compressive stress pattern in which a part of the side wall is exposed above the substrate in the recess region can be formed and a mask oxide film can be formed on the side wall of the spacer structure. A mask oxide film may be formed on the exposed sidewalls of the compressive stress pattern.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

The present invention relates to a semiconductor device and a manufacturing method thereof.

Due to their small size, versatility and / or low manufacturing cost, semiconductor devices are becoming an important element in the electronics industry. Semiconductor devices can be classified into a semiconductor memory element for storing logic data, a semiconductor logic element for processing logic data, and a hybrid semiconductor element including a memory element and a logic element. As the electronics industry develops, there is a growing demand for properties of semiconductor devices. For example, there is an increasing demand for high reliability, high speed and / or multifunctionality for semiconductor devices. In order to meet these requirements, structures in semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming more and more highly integrated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having improved electrical characteristics and a method of manufacturing the same.

It is another object of the present invention to provide a semiconductor device optimized for high integration and a manufacturing method thereof.

A method of manufacturing a semiconductor device to solve the above-described technical problems is provided. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate pattern on a substrate including an emmos region and a pmos region, forming a spacer structure on a sidewall of the gate pattern, Forming a recessed region in a substrate and an exposed substrate of the pmos region exposed by the spacer structure; forming a compressive stress pattern in the recessed region in which a portion of the sidewall is exposed above the substrate; Forming a mask oxide film on the sidewalls of the spacer structure, the mask oxide film being formed on the exposed sidewalls of the compressive stress pattern.

In one embodiment, the top surface of the compressive stress pattern is higher than the top surface of the substrate, and the sidewall of the compressive stress pattern may be shaped to be declined from the top surface of the compressive stress pattern toward the gate structure.

In one embodiment, the method further comprises forming a metal-semiconductor compound layer on the substrate exposed by the mask oxide layer, and removing the mask oxide layer, wherein removing the mask oxide layer comprises removing the mask oxide layer 1 silicon fluoride ammonium film, and sublimating and removing the first silicon fluoride ammonium film.

In one embodiment, changing the mask oxide film to the first ammonium fluoride ammonium film is performed by a source gas comprising NH ₃ , and the source gas may include at least one of HF or NF ₃ gas .

In one embodiment, the sublimation and removal of the first ammonium fluoride ammonium layer may include a heat treatment at 100 to 200 ° C. The sublimation process may be performed in-situ.

In one embodiment, the spacer structure includes a first nitride film and a first oxide film which are sequentially stacked on a sidewall of the gate pattern, the first nitride film includes a side wall portion extending along a sidewall of the first oxide film, And a bottom portion extending along the lower surface of the first oxide film.

In one embodiment, at the time of forming the first silicon fluoride ammonium film, at least a portion of the first oxide film may be changed to a second ammonium fluoride ammonium film.

In one embodiment, at least a portion of the second ammonium fluoride ammonium film may be removed together with removal of the first ammonium fluoride ammonium film.

In one embodiment, a portion of the second ammonium fluoride ammonium film may remain on the first nitride film.

In one embodiment, the formation of the spacer structure may include forming a second nitride film between the gate pattern and the first nitride film, and forming a second oxide film between the first nitride film and the second nitride film Quot;

In one embodiment, the method may further comprise forming a tensile stress pattern on the substrate.

In one embodiment, the tensile stress pattern may be formed in the emmos region and the impurity region.

A semiconductor device for solving the above-mentioned technical problems is provided. Wherein the semiconductor element comprises a substrate including an emmos region and a pmos region, a gate pattern on the substrate, a spacer structure on a sidewall of the gate pattern, a tensile stress pattern covering the gate pattern and the spacer structure in the emmos region, And a compressive stress pattern provided in the substrate of the pmos region, wherein the spacer structure includes a first nitride film, and the first nitride film can contact the compressive stress pattern.

In one embodiment, the spacer structure may comprise a silicon fluoride ammonium film on the first nitride film.

In one embodiment, the first nitride film includes a sidewall portion extending along a sidewall of the gate pattern and a bottom portion extending along an upper surface of the substrate, and the silicon fluoride ammonium film is formed at an intersection point of the sidewall portion and the bottom portion As shown in FIG.

In one embodiment, the first nitride layer comprises fluorine atoms, and the concentration of the fluorine atoms may decrease as the distance from the tensile stress pattern increases.

In one embodiment, the semiconductor device further comprises a channel region under the gate pattern and a metal-semiconductor compound layer on the substrate, wherein a distance from the channel region to the metal-semiconductor compound layer is greater than a distance from the channel region to the compressive stress pattern It can be big.

In one embodiment, in the impurity region, the bottom surface of the first nitride film and the metal-semiconductor compound layer may be spaced horizontally and vertically.

In one embodiment, the tensile stress pattern may be provided in the pmos region.

According to an embodiment of the present invention, the mask oxide film and a part of the spacer can be removed without damaging the silicide layer. When the silicide layer is formed in the pmos region, the leakage current can be reduced. The distance between the tensile stress pattern and the channel is reduced, so that the electrical characteristics of the semiconductor device can be improved. An interlayer insulating film can be formed without voids between adjacent transistors.

1 to 12 are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention.
13 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention.
FIG. 14 is a flowchart illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention.
15 is a block diagram of an electronic system including a semiconductor memory device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate, or a third film (Or layer) may be interposed. In the drawings, the sizes and thicknesses of the structures and the like are exaggerated for the sake of clarity. It should also be understood that although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Like numbers refer to like elements throughout the specification.

1 to 12 are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention. FIG. 14 is a flowchart illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 1, a substrate 100 including a first transistor region 10 and a second transistor region 20 may be provided. The substrate 100 may be a substrate including a semiconductor material. The substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or the like. The first transistor region 10 may be an NMOS region and the second transistor region 20 may be a PMOS region. A device isolation pattern 110 is formed on the substrate 100 to form a first active portion 105a in the first transistor region 10 and a second active portion 105b in the second transistor region 20, Can be defined. The device isolation pattern 110 may be formed by a trench isolation method. For example, the device isolation pattern 110 may fill a trench formed in the substrate 100. The first active portion 105a may be doped with a first conductive impurity and the second active portion 105b may be doped with a second conductive impurity. For example, the first conductivity type impurity may be a p-type impurity, and the second conductivity type impurity may be an n-type impurity.

Dummy gate patterns may be formed on the substrate 100. A first dummy gate pattern 129a may be formed in the first transistor region 10 and a second dummy gate pattern 129b may be formed in the second transistor region 20. [ The first dummy gate pattern 129a includes a first gate insulation pattern 111a, a first dummy gate electrode 120a on the first gate insulation pattern 111a, a first dummy gate electrode 120a on the first dummy gate electrode 120a, And a dummy hard mask pattern 127a. The second dummy gate pattern 129b has a second gate insulation pattern 111b, a second dummy gate electrode 120b on the second gate insulation pattern 111b, a second dummy gate electrode 120b on the second dummy gate electrode 120b, And a dummy hard mask pattern 127b. The first and second dummy gate patterns 129a and 129b may be formed at the same time. For example, a gate insulating layer (not shown) and a dummy gate electrode layer (not shown) are sequentially formed on the substrate 100, and then the first and second dummy hard mask patterns 127a and 127b are etched using an etch mask The gate insulating layer and the dummy gate electrode layer can be patterned. The gate insulating layer may include a plurality of insulating layers. For example, the gate insulating layer may include at least one of a hafnium oxide film (HfOx), a tantalum oxide film (TaOx), and a silicon oxide film (SiO ₂ ) having a high dielectric constant. The gate insulating layer may be formed by at least one of chemical vapor deposition (CVD), atomic layer deposition (ALD), or rapid thermal processing (RTP). The dummy gate electrode layer may include polysilicon. The dummy gate electrode layer may be formed by chemical vapor deposition.

A first spacer 131 and a second spacer 132 may be sequentially formed on the sidewalls of the first and second dummy gate patterns 129a and 129b. The first spacer 131 may be a silicon nitride film. The second spacer 132 may be a silicon oxide film. The first spacers 131 may be formed by dry etching using a plasma having a strong directivity after forming a silicon nitride film on the first and second dummy gate patterns 129a and 129b. A portion of the silicon nitride film may remain on the sidewalls of the first and second dummy gate patterns 129a and 129b by the dry etching process. The second spacers 132 may be formed by dry etching using plasma as in the first spacers 131 after forming a silicon oxide film on the first spacers 131. Alternatively, the second spacers 132 may be formed by an ashing process after the first spacers 131 are formed.

A first source / drain extension part 101 is formed in the first active part 105a using the first and second spacers 131 and 132 as ion implantation masks and the first source / drain extension part 101 is formed in the second active part 105b. 2 source / drain extensions 102 can be formed. The first and second source / drain extensions 101 and 102 may be impurity regions having different conductivity types. For example, when the first transistor region 10 is an emmos region, the first source / drain extension portion 101 is a region doped with an n-type impurity, and the second transistor region 20 is a p- Region, the second source / drain extension 102 may be a region doped with a p-type impurity.

Referring to FIGS. 2 and 3, a third spacer 143 and a fourth spacer 144 may be formed on the substrate 100. The third spacer 143 may include an etch selectivity material for the fourth spacer 144. For example, the third spacer 143 and the fourth spacer 144 may be silicon nitride films and silicon oxide films, respectively. The third and fourth spacers 143 and 144 may be formed by sequentially forming a silicon nitride film 141 and a first silicon oxide film 142 covering the substrate 100 and then dry etching the resultant plasma with a strong direct- . The third spacers 143 and the fourth spacers 144 may be formed on the second spacers 132 by the etching process. The first to fourth spacers 131, 132, 143 and 144 constitute a spacer structure 145. The third spacer 143 may include a sidewall 143a extending along the sidewalls of the dummy gate patterns 129a and 129b and a bottom 143b extending along the upper surface of the substrate 100 have. That is, the third spacer 143 may have an L-shaped cross section. The third spacer 143 may extend along the side wall and the bottom surface of the fourth spacer 144. The third spacer 143 can protect the active portions 105a and 105b when the contact holes are misaligned as described below. The first source / drain region 103 may be formed in the first active portion 105a using the first through fourth spacers 131, 132, 143, and 144 as ion implantation masks. The first source / drain region 103 may be formed by implanting a second conductivity type impurity at a higher dose than that of forming the one source / drain extension portion 101.

Referring to FIG. 4, after the epitaxial growth prevention film 155 is formed on the front surface of the substrate 100, the epitaxial growth prevention film 155 is patterned to expose the second transistor region 20 . The recessed region 151 may be formed by etching the exposed second active portion 105b. The recessed region 151 may be formed by a directional wet etching process. The directional wet etching process may use the crystal planes selected from the crystal planes of the substrate 100 as an etch stop plane. For example, the directional wet etching process may use {111} planes of the crystal planes of the substrate 100 as an etch stop plane. Accordingly, the longitudinal section of the recess region 151 may be pointed toward the channel region below the second dummy gate pattern 129b. That is, the lower sidewall and the upper sidewall of the substrate 100 defining the recess region 151 may be inclined toward the channel region under the second dummy gate pattern 129b. When the substrate 100 is a silicon substrate, the directional wet etching process may use a directional etching solution containing ammonia and / or tetramethyl ammonium hydroxide (TMAH).

Unlike the above, the recessed region 151 may be formed by an anisotropic dry etching process using an etching gas having a straightness in a specific direction. For example, the anisotropic dry etching process may include etching the substrate 100 with an etching gas having a straight line in a direction perpendicular to the upper surface of the substrate 100. In this case, the device isolation pattern 110 and the spacer structure 145 may be used as an etching mask. The recess region formed by the dry etching process as described above may be different from the recess region 151 shown in FIG. For example, the recess region formed by the dry etching process may not have a pointed sidewall such as the sidewall of the recess region 151.

5 and 6, a compressive stress pattern 170 filling the recessed region 151 may be formed. The compressive stress pattern 170 may be formed by performing a selective epitaxial growth process on the recess region 151. The first transistor region 10 is covered with the epitaxial growth prevention film 155 shown in FIG. 4, so that the compressive stress pattern 170 may not be formed on the first active portion 105a. If the substrate 100 is silicon, the compressive stress pattern 170 may be formed of silicon-germanium. The compressive stress pattern 170 may be in a crystalline state. In one example, the compressive stress pattern 170 may be substantially single crystal.

The compressive stress pattern 170 may be doped with an impurity of the first conductivity type in an in-situ manner. Alternatively, the compressive stress pattern 170 may be doped with the impurity of the first conductivity type in an ion implantation method after forming the compressive stress pattern 170. After forming the compressive stress pattern 170, the epitaxial growth prevention film 155 may be removed. The compressive stress pattern 170 may increase the degree of mobility of carriers in the second transistor region 20. [

The compressive stress patterns 170 may be grown above the upper surface of the substrate 100. That is, the upper surface of the compressive stress pattern 170 may be higher than the upper surface of the substrate 100. Accordingly, a part of the sidewall of the compressive stress pattern 170 is exposed on the substrate 100. A portion of the sidewall of the compressive stress pattern 170 exposed above the substrate 100 may extend substantially parallel to the sidewall of the substrate 100 defining the recessed area 151. This is because the compressive stress pattern 170 maintains crystal orientation while growing from the bottom of the recess region 151 to the top. 5, the longitudinal section of the compressive stress pattern 170 is shown as pentagonal by the element isolation pattern 110. However, when there is no interference of the element isolation pattern 110, as shown in FIG. 13 The compressive stress pattern 170 may have a hexagonal shape. When the compressive stress pattern 170 has the shape as described above, a gap region G may be formed between the upper portion of the compressive stress pattern 170 and the spacer structure 145. This is because the sidewall of the compressive stress pattern 170 exposed on the substrate 100 has an inclined surface. The inclined surface may be a structure that is declined from the upper surface of the compressive stress pattern 170 to the second gate pattern 129b. When the metal-semiconductor compound layer to be described below is formed in the gap between the compressive stress pattern 170 and the spacer structure 145, the leakage current can be increased. A mask oxide film 161 filling the gap may be formed to prevent an increase in leakage current. That is, the mask oxide layer 161 may be provided on the inclined surface of the compressive stress pattern 170 exposed on the substrate 100. The mask oxide film 161 is formed by forming a second silicon oxide film 160 covering the sidewall of the spacer structure 145 after the compressive stress pattern 170 is formed and forming the second silicon oxide film 160 by dry etching using plasma .

After forming the mask oxide layer 161, first and second metal-semiconductor compound layers 175a and 175b are formed on the upper surface of the substrate 100 exposed by the mask oxide layer 161 and the upper surface of the compressive stress pattern 170, respectively. , 175b may be formed. In the case where the substrate 100 is a silicon substrate, the first metal-semiconductor compound layer 175a formed in the first transistor region 10 may be a metal silicide. When the compressive stress pattern 170 is formed of silicon-germanium, the second metal-semiconductor compound layer 175b formed in the second transistor region 20 may be a metal-silicon-germanium compound. The first and second metal-semiconductor compound layers 175a and 175b may be spaced apart from the spacer structure 145 by the mask oxide layer 161. For example, in the first transistor region 10, the distance from the channel region to the first metal-semiconductor compound layer 175a may be d1. Which may be a distance greater than the distance d2 between the sidewalls of the spacer structure 145 from the channel region. Hereinafter, the distance may refer to a distance in a direction parallel to the upper surface of the substrate 100, unless otherwise specified herein. The bottom of the third spacer 143 and the second metal-semiconductor compound layer 175b may be spaced horizontally and vertically. A cleaning process may be performed before forming the metal-semiconductor compound layers 175a and 175b, and a part of the mask oxide film 161 is removed together with the cleaning process, 4 spacers 144, as shown in FIG. After the metal-semiconductor compound layers 175a and 175b are formed, a native oxide film 176 may be formed on the metal-semiconductor compound layers 175a and 175b.

Referring to FIGS. 7 and 14, the mask oxide film 161 may be converted into a silicon fluoride film by a predetermined source gas injection (S1) (S2). The silicon fluoride film may be a first silicon fluoride ammonium film ((NH ₄ ) _X SiF _y ) (162). For example, the mask oxide film 161 may be a first silicon fluoride ammonium film 162 by a source gas containing NH ₃ . The source gas may include HF and / or NF ₃ . More specifically, the process can be described by the following chemical reaction using source gases including NH ₃ and HF.

[Chemical Formula 1]

SiO ₂ + 4HF? SiF ₄ + 2H ₂ O ????? (1)

SiF ₄ + 2 NH ₃ + 2HF? (NH ₄ ) ₂ SiF ₆ -------------------------------(2)

Alternatively, the process can be illustrated by the following chemical reaction by a source gas comprising NH ₃ and NF ₃ .

(2)

NF ₃ + NH _{3 -} > NH ₄ F + NH ₄ F. HF ----------------------------------- - (3)

NH ₄ F + SiO ₂ → (NH ₄ ) ₂ SiF ₆ + H ₂ O -------------------------------- - (4-1)

NH ₄ F.HF + SiO ₂ → (NH ₄ ) ₂ SiF ₆ + H ₂ O ------------------------------ (4-2)

The reaction (3) may be a reaction using source gases in a plasma state. Alternatively, the source gases of reaction (1) may not be in a plasma state. In the reactions (4-1) and (4-2), only one of the two reactions may be selectively performed or may occur together. The reaction (4-1) and / or (4-2) may be carried out at about 50 ° C or lower.

If the fourth spacer 144 is a silicon oxide film, at least a part of the fourth spacer 144 may be changed together with the mask oxide film 161. In this case, the fourth spacer 144 may be a second silicon fluoride ammonium film 146. Also, the natural oxidation film 176 may be subjected to a fluorination process.

Referring to FIGS. 8 and 14, the first and second silicon fluoride ammonium films 162 and 146 may be removed. The removing process may include sublimating the first and second silicon fluoride ammonium films 162 and 146 at a high temperature (S3). For example, sublimating and removing the first and second silicon fluoride ammonium films 162 and 146 may include heat treating at 100 to 200 ° C. The heat treatment may be performed in situ. The sublimation process can be described by the following chemical formula.

(3)

(NH ₄ ) ₂ SiF ₆ (s) SiF ₄ (g) + NH ₃ (g) + HF (g)

The natural oxide film 176 may also be removed together with the processes. Although not shown, other silicon oxide films exposed on the substrate 100 may also be partially removed by the fluorination and removal processes.

The removal process may remove the mask oxide film 161 and the fourth spacer 144 without damaging the metal-semiconductor compound layers 175a and 175b, unlike a conventional etching process. Typical wet etching can cause etch damage to the metal-semiconductor compound layers 175a and 175b due to the chemical reaction between the etchant and the metal-semiconductor compound layers 175a and 175b. Typical dry etching has a low selectivity, A mask process is required and a subsequent ashing process is required. In the removing step of the present invention, oxide films are selectively changed to fluoride films and then removed by sublimation. Therefore, the mask oxide film 161 and the fourth spacers 144 can be removed without damaging the metal-semiconductor compound layers 175a and 175b.

Referring to FIG. 9, a tensile stress pattern 180 may be formed in the first transistor region 10. The tensile stress pattern 180 may comprise a silicon nitride film having a lower density than a typical silicon nitride film. For example, the tensile stress pattern 180 may generate a tensile stress by forming a silicon nitride film on the first transistor region 10 and then subjecting the silicon nitride film to ultraviolet treatment to change the density of the surface region of the film. Alternatively, the tensile stress pattern 180 may be formed by a surface treatment using a gas that substitutes nitrogen of the silicon nitride film with oxygen. The tensile stress pattern 180 may not be provided in the second transistor region 20 as shown. For example, the tensile stress pattern 180 may be formed on the entirety of the first and second transistor regions 10 and 20, and then portions provided on the second transistor region 20 may be removed.

 As the tensile stress pattern 180 is closer to the channel region, the effect of increasing the carrier mobility can be increased. The distance d3 from the tensile stress pattern 180 to the channel region may be greater than the distance d3 from the channel region when the mask oxide film 161 is not removed, (D 1 in FIG. 6) to the tensile stress pattern 180. In addition, the fourth spacers 144 of FIG. 6 may be removed together so that the tensile stress patterns 180 and the third spacers 143 may be in direct contact with each other. The third spacer 143 is L-shaped in shape and has a relatively narrower width than the fourth spacer 144. The tensile stress pattern 180 formed on the sidewalls of the first gate pattern 129a may approach the channel region as a whole. Therefore, the carrier mobility by the tensile stress pattern 180 is further increased, and the electrical characteristics of the semiconductor device can be improved.

Referring to FIG. 10, the first and second dummy gate electrodes 120a and 120b and the first and second dummy hard mask patterns 127a and 127b may be removed. The first and second dummy gate electrodes 120a and 120b and the first and second dummy hard mask patterns 127a and 127b may be removed by forming an interlayer insulating film 185 covering the substrate 100, And exposing the first and second dummy hard mask patterns 127a and 127b by a planarization process. The exposed dummy hard mask patterns 127a and 127b and the dummy gate electrodes 120a and 120b below the exposed dummy hard mask patterns 127a and 127b may be removed to form the opening 186. [

Referring to FIG. 11, the first and second barrier patterns 192a and 192b and the first and second gate electrodes 191a and 191b may be formed in the opening 186. The barrier patterns 192a and 192b and the gate electrodes 191a and 191b are formed by successively forming a barrier film (not shown) and a gate electrode film (not shown) on the substrate 100, The planarization process may be performed until the planarization layer 185 is exposed. The barrier film may include a diffusion barrier film. In one example, the diffusion barrier film may be formed of a conductive metal nitride film. For example, the diffusion barrier layer may be at least one of a titanium nitride layer, a tantalum nitride layer, and a tungsten nitride layer. The gate electrode film may be a metal film. In one example, the gate electrode film may be aluminum or copper.

Referring to FIG. 12, a contact plug 193 electrically connected to the metal-semiconductor compound layers 175a and 175b may be formed. The contact plug 193 may be formed by forming a contact hole (not shown) exposing the metal-semiconductor compound layers 175a and 175b and then filling the contact hole with a conductive material. The contact plug 193 may include at least one of tungsten, aluminum, and copper. The third spacers 143 may protect the active portions 105a and 105b when the contact holes are misaligned. The tensile stress pattern 180 may serve as an etch stop layer when the contact hole is formed.

According to an embodiment of the present invention, the mask oxide film 161 and the fourth spacer 144 can be removed without damaging the metal-semiconductor compound layer. Also, the distance between the tensile stress pattern 180 and the channel region is reduced, and the mobility of carriers can be further increased.

Referring to FIG. 13, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention are provided. For the sake of simplicity, the technical structure and description overlapping with the first embodiment may be omitted.

In the semiconductor device according to the second embodiment of the present invention, a plurality of transistors may be provided in each of the first and second transistor regions 10 and 20. The plurality of transistors may share a source / drain region. For example, the semiconductor device of the second embodiment may be an esram. When a plurality of transistors share a source / drain, a void may be formed in the interlayer insulating layer 185 when the interlayer insulating layer 185 is formed between the plurality of transistors. Such a phenomenon can be further increased, especially as the degree of integration of the semiconductor device is increased. Further, when a tensile stress pattern is provided between a plurality of transistors, the probability of occurrence of the void can be further increased. According to embodiments of the present invention, some of the spacers formed between the plurality of transistors may be further removed to form the interlayer insulating film 185 without voids between the transistors.

A compressive stress pattern 170 may be provided in a region between the plurality of gates of the second transistor region 20. The compressive stress pattern 170 may be substantially hexagonal in longitudinal section through the process as described above. 13, all the sides of the hexagonal shape do not overlap with the bottom of the first spacer 131, but unlike the illustrated example, some of the sides of the hexagonal shape overlap with the bottom of the first spacer 131 Lt; / RTI >

Unlike the first embodiment, the tensile stress pattern 180 may also be formed in the second transistor region 20. The tensile stress pattern 180 formed in the second transistor region 20 may serve as an etch stop layer when forming a contact hole for forming the contact plug 193. Since the second transistor region 20 is provided with the compressive stress pattern 170, the tensile stress pattern 180 does not hinder the increase in carrier mobility.

The first spacer 131 may be L-shaped, having a side wall and a bottom, unlike the first embodiment. The second embodiment of the present invention may not be provided with the second and third spacers 132 and 143 of the first embodiment, and a fourth spacer (not shown) which is a silicon oxide film may be formed directly on the first spacer 131 . The mask spacer (not shown) and the fourth spacer can be removed by the process according to FIG. During the removal process, a part of the second ammonium fluoride ammonium film 146 may remain on the first spacer 131. In particular, the second silicon fluoride ammonium layer 146 may remain at a point where the side wall portion and the bottom portion of the first spacer 131 meet.

Alternatively, a part of the fourth spacer may remain as an oxide film without being changed to the second ammonium fluoride ammonium film 146. [ In this case, the silicon oxide film may remain on the first spacer 131 after the removing step (S3).

During the fluorination process, fluorine atoms can penetrate into a part of the first spacer 131 by diffusion. In this case, the concentration of fluorine atoms in the first spacer 131 may decrease as the distance from the tensile stress pattern 180 increases.

The semiconductor devices disclosed in the above-described embodiments can be implemented in various types of semiconductor packages. For example, the semiconductor devices according to embodiments of the present invention may be used in a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

The package in which the semiconductor element is mounted according to the embodiments of the present invention may further include at least one other semiconductor element (ex, controller, storage element, and / or hybrid element, etc.) performing other functions.

15 is a block diagram of an electronic system including a semiconductor memory device according to embodiments of the present invention.

15, an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input / output (I / O) device 1120, a memory device 1130, an interface 1140, 1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The storage device 1130 may include at least one of the semiconductor storage elements disclosed in the first and second embodiments described above. Further, the storage device 1130 may further include other types of semiconductor storage elements (ex, flash storage elements, DRAM elements, and / or Slam elements). The interface 1140 may perform functions to transmit data to or receive data from the communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 is an operation memory for improving the operation of the controller 1110, and may further include a high-speed DRAM and / or an esram.

The electronic system 1100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative and non-restrictive in every respect.

10, 20:
105a, 105b: active part 110: element isolation pattern
111a, 111b: gate insulating pattern 131, 132, 143, 144:
120a, 120b: dummy gate electrode 151: recess region
155: epitaxial barrier layer 161: mask oxide film
162: Silicon fluoride ammonium film 170: Compressive stress pattern
175a, 175b: metal-semiconductor compound layer

Claims (10)

Forming a gate pattern on a substrate comprising an emmos region and a pmos region;
Forming a spacer structure on a sidewall of the gate pattern;
Forming a recessed region in the exposed substrate of the emissive region exposed by the gate pattern and the spacer structure;
Forming a compressive stress pattern in the recessed region, wherein a portion of the sidewall is exposed above the substrate;
Forming a mask oxide film on the sidewalls of the spacer structure, the mask oxide film being formed on the exposed sidewalls of the compressive stress pattern;
Forming a metal-semiconductor compound layer on the compressive stress pattern; And
And removing the mask oxide film from the side wall of the spacer structure after forming the metal-semiconductor compound layer. The method according to claim 1,
The upper surface of the compressive stress pattern is higher than the upper surface of the substrate,
And the sidewall of the compressive stress pattern is declined from the upper surface of the compressive stress pattern toward the gate pattern direction. The method according to claim 1,
The mask oxide film is removed by:
Changing the mask oxide film to a first silicon fluoride ammonium film; And
And removing the first silicon fluoride ammonium film by sublimation. The method of claim 3,
Wherein the step of changing the mask oxide film into the first ammonium fluoride ammonium film is performed by a source gas containing NH ₃ , and the source gas further comprises at least one of HF and NF ₃ gas. The method of claim 3,
Wherein the first silicon fluoride ammonium film is sublimated and removed by heat treatment at 100 to 200 ° C. 6. The method of claim 5,
Wherein the sublimation process is performed in-situ. The method of claim 3,
Wherein the spacer structure includes a first nitride layer and a first oxide layer which are sequentially stacked on a sidewall of the gate pattern, the first nitride layer includes a side wall portion extending along a sidewall of the first oxide layer, And a bottom portion extending along the bottom portion. 8. The method of claim 7,
Further comprising changing at least a part of the first oxide film to a second ammonium fluoride ammonium film when the first ammonium fluoride ammonium film is formed. 9. The method of claim 8,
And at least a part of the second ammonium fluoride ammonium film is removed together with removal of the first ammonium fluoride ammonium film. The method according to claim 1,
And forming a tensile stress pattern on the substrate.

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