KR101772577B1 - Data storage system having multi-bit memory device and operating method thereof - Google Patents

Abstract

Comprising: a nonvolatile memory device having a memory cell array; And a memory controller having a buffer memory and controlling the non-volatile memory device. A method of operating a data storage device stores data entered in response to an external request into the buffer memory; Determining whether data stored in the buffer memory is data accompanying a buffer program operation for the memory cell array; Determining whether a main program operation for the memory cell array is required when the data stored in the buffer memory is data accompanied by a buffer program operation; Determining a pattern of a main program operation for the memory cell array when a main program operation for the memory cell array is required; And outputting a series of instructions for a main program operation to the multi-bit memory device for the memory cell array based on the determined pattern.

Description

TECHNICAL FIELD [0001] The present invention relates to a data storage system including a multi-bit memory device and a method of operating the same.

The present invention relates to storage, and more particularly, to a data storage system.

Semiconductor memory is typically the most essential microelectronic component of digital logic design such as microprocessor-based applications and computers that range from satellite to consumer electronics. Advances in semiconductor memory fabrication techniques, including process improvements and technology development, resulting from scaling for high densities and high speeds, can help establish performance criteria for other digital logic families.
Semiconductor memory devices are roughly divided into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. In a volatile semiconductor memory device, the logic information is stored by setting the logic state of the bistable flip-flop in the case of a static random access memory or by charging a capacitor in the case of a dynamic random access memory. In the case of a volatile semiconductor memory device, data is stored and read while power is applied, and data is lost when the power is turned off.
Nonvolatile semiconductor memory devices such as MROM, PROM, EPROM, EEPROM, PRAM, and the like can store data even when power is turned off. The state of the nonvolatile memory data storage is either permanent or reprogrammable, depending on the manufacturing technology used. Nonvolatile semiconductor memory devices are used for storage of programs and microcode in a wide range of applications such as computers, avionics, communications, and consumer electronics technology industries. The combination of volatile and nonvolatile memory storage modes on a single chip is also usable in devices such as nonvolatile RAM (nvRAM) in systems requiring fast and reprogrammable nonvolatile memory. In addition, specific memory structures have been developed that include some additional logic circuitry to optimize performance for application-oriented tasks.
In the nonvolatile semiconductor memory device, the MROM, the PROM, and the EPROM are not freely erased and written by the system itself, so that it is not easy for ordinary users to refresh the memory contents. On the other hand, since nonvolatile semiconductor memory devices such as EEPROM, PRAM, and the like can be electrically erased and written, application to system programming and an auxiliary memory device which are required to be continuously updated are expanding.

It is an object of the present invention to provide a data storage system capable of minimizing the buffer size of a memory controller and a method of operation thereof.

One feature of the present invention is a non-volatile memory device having a memory cell array; And a memory controller having a buffer memory and controlling the nonvolatile memory device. The method of operating a data storage device includes storing data input according to an external request in the buffer memory and; Determining whether data stored in the buffer memory is data accompanying a buffer program operation for the memory cell array; Determining whether a main program operation for the memory cell array is required when the data stored in the buffer memory is data accompanied by a buffer program operation; Determining a pattern of a main program operation for the memory cell array when a main program operation for the memory cell array is required; And outputting a series of instructions for a main program operation to the multi-bit memory device for the memory cell array based on the determined pattern.
Another aspect of the present invention is a nonvolatile memory device including a memory cell array having a first area and a second area; And a memory controller having a buffer memory and configured to control the nonvolatile memory device. When data of a minimum program unit for the first area is stored in the buffer memory, the memory controller stores data stored in the buffer memory The nonvolatile memory device controlling the nonvolatile memory device to be stored in the first area.

According to exemplary embodiments of the present invention, it is possible to minimize the buffer size of the memory controller.

FIG. 1A is a diagram illustrating an example of an address scrambling scheme applied to a multi-level memory device according to an exemplary embodiment of the present invention.
1B is a diagram showing threshold voltage distributions that are varied when each memory cell stores 4-bit data and a program operation is performed according to a 3-step programming method.
1C is a diagram showing threshold voltage distributions that are varied when each memory cell stores 3-bit data and a program operation is performed according to a 3-step programming method.
2 is a block diagram that schematically illustrates a data storage system in accordance with exemplary embodiments of the present invention.
3 is a diagram illustrating an exemplary address scrambling scheme for a multi-bit memory device in which four-bit per cell data is stored and a three-step reprogramming method is applied.
FIG. 4 is a schematic diagram illustrating data flow during program operation of the data storage system shown in FIG. 2. FIG.
5 is a diagram schematically illustrating a data flow according to the series of single-bit program operations and the one-step program operation described in FIG.
FIG. 6 is a schematic diagram illustrating a data flow according to a series of single-bit program operations and coarse / fine program operations illustrated in FIG.
FIG. 7 is a schematic diagram illustrating a data flow according to the series of single-bit program operations, coarse program operations, and sophisticated program operations described in FIG.
8 is a flowchart for explaining a read operation of the memory system shown in FIG.
9 is a diagram illustrating an exemplary address scrambling scheme of a multi-bit memory device in which 3-bit data per cell is stored and a three-step reprogramming method is applied.
FIG. 10 is a schematic diagram of data flow during a program operation of the data storage system shown in FIG. 2. FIG.
11 schematically illustrates a page interleaving method according to an exemplary embodiment of the present invention.
FIG. 12 is a diagram schematically illustrating a data flow during a program operation of a data storage system to which the page interleaving method illustrated in FIG. 11 is applied.
13 is a diagram illustrating another exemplary address scrambling scheme of a multi-bit memory device in which 3-bit data per cell is stored and a reprogramming method is applied.
FIG. 14 is a diagram schematically illustrating a data flow during a program operation performed according to the address scrambling method shown in FIG. 13; FIG.
15 is a schematic diagram illustrating a page buffer structure of a multi-bit memory device according to an exemplary embodiment of the present invention.
FIG. 16 is a diagram showing a command sequence for the one-step program operation described in FIGS. 13 and 14. FIG.
FIG. 17 is a view showing a data flow according to the one-step program command sequence shown in FIG.
18 is a diagram showing a command sequence for the coarse program operation described in Figs. 13 and 14. Fig.
19 is a view showing a data flow according to the coarse program command sequence shown in FIG.
FIG. 20 is a diagram schematically showing a data flow during a page interleaving method illustrated in FIG. 11 and a program operation of a data storage system to which the address scramble method described in FIG. 13 is applied.
Figure 21 is a diagram illustrating another exemplary address scrambling scheme of a multi-bit memory device in which 4-bit data per cell is stored and a reprogramming method is applied.
Figures 22A-22D are diagrams illustrating various combinations of first and second regions of a multi-bit memory device in accordance with an exemplary embodiment of the present invention.
23 to 25 are flowcharts for explaining the operation of the memory controller according to the exemplary embodiments of the present invention.
26 is a diagram showing an example of configuring a memory cell array as memory blocks for an all-bit line memory structure or an odd-even memory structure.
Figure 27 is a block diagram that schematically illustrates a computing system in accordance with an exemplary embodiment of the present invention.
28 is a block diagram that schematically illustrates a memory controller in accordance with an exemplary embodiment of the present invention.
29 is a block diagram schematically illustrating a semiconductor drive according to an exemplary embodiment of the present invention.
30 is a block diagram schematically showing the storage using the semiconductor drive shown in FIG.
31 is a block diagram schematically showing a storage server using the semiconductor drive shown in FIG.
32 to 34 are diagrams schematically showing systems to which a data storage device according to exemplary embodiments of the present invention is applied.
35 is a block diagram schematically illustrating a memory card according to an embodiment of the present invention.
36 is a block diagram schematically showing a digital still camera according to an embodiment of the present invention.
37 is an exemplary diagram illustrating various systems in which the memory card of Fig. 35 is used.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.
In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Also, the same reference numerals denote the same components throughout the specification.
The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / connected " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, components, steps, operations and elements referred to in the specification as " comprises " or " comprising " mean the presence or addition of one or more other components, steps, operations, elements and devices.
As the number of data bits stored in each memory cell increases, it becomes increasingly difficult to secure the reliability of a memory device storing multi-bit (or multi-level) data (hereinafter referred to as a multi-level memory device) ought. One of the factors that reduces reliability is a change in threshold voltages due to coupling between adjacent memory cells. For example, the threshold voltage of a previously programmed memory cell may change due to the coupling that occurs when a memory cell adjacent to the programmed memory cell is programmed. One example of an address scrambling scheme applied to a multi-level memory device to efficiently manage such coupling is shown in FIG.
The address scrambling scheme will be described under the assumption that 4-bit data is stored in one memory cell. For convenience of illustration, only four word lines (WL0 to WL3) are shown in FIG. A plurality of memory cells MC will be connected to each of the word lines WL0 to WL3. First, a one-step programming operation in which the lower 2-bit data is stored in each of the memory cells connected to the first word line WL0 will be performed. That is, during one-step program operation, the two-page data will be stored in the memory cells connected to the first word line WL0. This is indicated by? In Fig. 1A. Then, a one-step program operation will be performed on the memory cells connected to the second word line WL1. This is indicated by? In Fig. 1A. After the one-step programming operation for the second word line WL1 is performed, the memory cells connected to the first word line WL0, which are located below the second word line WL1 and the lower 2-bit data is programmed, A coarse program operation (also referred to as a 2-step programming) in which upper 2-bit data is stored will be performed. This is indicated by? In Fig. 1A. After a coarse programming operation is performed on the memory cells connected to the first word line WL0, a one-step programming operation is performed on the third word line WL2, which is indicated by? In Fig. 1A. After the one-step program operation for the third word line WL2, a coarse program operation is performed in which the upper two-bit data is stored in the memory cells connected to the second word line WL1 in which the lower 2-bit data is programmed will be. This is indicated by? In Fig. 1a. Thereafter, a fine program operation for the first word line WL0 will be performed. This is indicated by ⑥ in FIG. Thereafter, one-step, coarse, and sophisticated program operations will be performed sequentially in accordance with the program sequence (see FIG. 1A) described above. The manner in which the word lines are selected in accordance with the program sequence described in FIG. 1A is referred to as an address scramble method.
When the one-step program operation and coarse program operation are completed, threshold voltage distributions corresponding to M-bit data (M is 2 or larger integer) (e.g., 2 ^M Threshold voltage distributions) will all be formed. Although all the threshold voltage distributions are formed as the rough program operation is completed, the margin between the threshold voltage distributions will not be sufficient to clearly distinguish the threshold voltage distributions. A sophisticated program operation will be performed to ensure a margin sufficient to clearly distinguish the threshold voltage distributions. The sophisticated program operation is performed to narrow the width of each threshold voltage distribution and will be done using verify voltages that are each higher than the verify voltages of the threshold voltage distributions used in coarse program operation by a predetermined voltage. Through this programming scheme it is possible to reduce the coupling between adjacent memory cells. This program method / algorithm is referred to as a reprogram method / algorithm.
It will be appreciated that in the exemplary embodiment, the reprogramming method for 4-bit data, that is, one-step programming, coarse programming, and sophisticated programming, applies to both 2-bit data and 3-bit data reprogramming methods will be.
With this reprogramming method, it is necessary to maintain the data stored in the memory cells of any word line until the sophisticated program operation for any word line is terminated. For example, the one-step program operation is performed based on data provided to the multi-bit memory device in the memory controller, and the rough program operation is performed based on the data stored in the one-step program operation and the data provided in the memory controller . The sophisticated program operation will be performed based on the stored data through one-step program operation and coarse program operation. However, as described above, it is difficult to accurately read stored data through one-step program operation and coarse program operation. This means that the data required for sophisticated program operation must be provided to the multi-bit memory device in the memory controller. Hence, the data stored in the memory cells of any word line will be held by the memory controller until the sophisticated program operation for any word line is terminated. This means that a large amount of buffer memory is provided to the memory controller to hold the data necessary for sophisticated program operation.
1B is a diagram showing threshold voltage distributions that are varied when each memory cell stores 4-bit data and a program operation is performed according to a 3-step programming method. Hereinafter, the programming method according to the three-step programming method will be described based on the reference drawings.
First, two-page data (i.e., first and second page data) will be stored in the memory cells of the selected word line (e.g., WL0, see FIG. At this time, the memory cells belonging to the threshold voltage distribution corresponding to the erase state E correspond to the program states (Q1, Q2, Q3), respectively, according to the data to be programmed, Will be programmed to have threshold voltages belonging to threshold voltage distributions.
As described above, the coarse programming operation of one-step programmed memory cells belonging to a word line (e.g., WL0) is performed after one-step programming operation of memory cells belonging to an adjacent word line (e.g., WL1) Lt; / RTI > At this time, as shown in box 22 of FIG. 1B, the distributions of the one-step programmed memory cells belonging to the word line (for example, WL0) are stored in memory cells (for example, Lt; / RTI > will be widened by the coupling that occurs when they are programmed.
Next, the memory cells of the selected word line WL0 will be stored with 2-page data, i.e., third and fourth page data. At this time, as shown in box 23 of FIG. 1B, the memory cells belonging to the threshold voltage distribution corresponding to each state will be programmed to have threshold voltages belonging to corresponding threshold voltage distributions. For example, the memory cells belonging to the threshold voltage distribution corresponding to the erase state E are programmed to have threshold voltages belonging to the threshold voltage distributions respectively corresponding to program states P1 'to P3' Will be. The memory cells belonging to the threshold voltage distribution corresponding to the program state Q1 will be programmed to have threshold voltages belonging to the threshold voltage distributions respectively corresponding to the program states P4 'to P7' according to the data to be programmed. The memory cells belonging to the threshold voltage distribution corresponding to program state Q2 will be programmed to have threshold voltages belonging to the threshold voltage distributions respectively corresponding to program states P8'-P11 'according to the data to be programmed. The memory cells belonging to the threshold voltage distribution corresponding to the program state Q3 will be programmed to have threshold voltages belonging to the threshold voltage distributions respectively corresponding to the program states P12 'to P15' according to the data to be programmed.
As described above, the sophisticated program operation of coarse programmed memory cells belonging to a word line (e.g., WL0) is performed by a one-step program operation for adjacent word lines (e.g., WL2, WLl) It will be done after operation. At this point, as shown in box 24 of FIG. 1B, distributions of coarse programmed memory cells belonging to a word line (e.g., WL0) are stored in memories belonging to adjacent word lines (e.g., WL2, WL1) Will be widened by the coupling that occurs when the cells are programmed. For this reason, it is difficult to accurately read data from roughly programmed memory cells.
The memory cells belonging to the word line WL0 will be programmed to have the final threshold voltage distributions P1 to P15 as shown in box 25 of FIG. 1B. This operation is called sophisticated program operation. As described above, the sophisticated program operation requires previously programmed data (e.g., first through fourth page data), which may include previously programmed data from memory cells belonging to word line WL0 (Or data maintained by the memory device) provided by the memory controller because it is difficult to read accurately. As shown in box 26 of FIG. 1B, distributions of sophisticated programmed memory cells may also be widened due to coupling occurring when memory cells belonging to adjacent word lines are programmed.
Thereafter, a one-step program operation, a coarse program operation, and a sophisticated program operation for each word line are performed in accordance with the program sequence described in FIG. 1A, which will be performed in the same manner as described in FIG. 1B.
1C is a diagram showing threshold voltage distributions that are varied when each memory cell stores 3-bit data and a program operation is performed according to a 3-step programming method. Hereinafter, the programming method according to the three-step programming method will be described based on the reference drawings.
First, two-page data (i.e., first and second page data) will be stored in the memory cells of the selected word line (e.g., WL0, see FIG. At this time, the memory cells belonging to the threshold voltage distribution corresponding to the erase state E correspond to the program states (Q1, Q2, Q3), respectively, according to the data to be programmed Will be programmed to have threshold voltages belonging to threshold voltage distributions.
As described above, the coarse programming operation of one-step programmed memory cells belonging to a word line (e.g., WL0) is performed after one-step programming operation of memory cells belonging to an adjacent word line (e.g., WL1) Lt; / RTI > At this time, the scattering of the one-step programmed memory cells belonging to the word line (for example, WL0), as shown by the solid line of the box 31 in Fig. 1C, Lt; / RTI > will be widened by the coupling that occurs when they are programmed.
Then, one-page data will be stored in the memory cells of the selected word line WL0. At this time, as shown in box 32 of FIG. 1C, the memory cells belonging to the threshold voltage distribution corresponding to each state will be programmed to have threshold voltages belonging to the corresponding threshold voltage distributions. For example, the memory cells belonging to the threshold voltage distribution corresponding to the erase state E will be programmed to have threshold voltages belonging to the threshold voltage distribution corresponding to the program state P1 in accordance with the data to be programmed. The memory cells belonging to the threshold voltage distribution corresponding to program state Q1 will be programmed to have threshold voltages belonging to threshold voltage distributions respectively corresponding to program states P2 and P3 according to the data to be programmed. The memory cells belonging to the threshold voltage distribution corresponding to program state Q2 will be programmed to have threshold voltages belonging to the threshold voltage distributions respectively corresponding to program states P4 and P5 according to the data to be programmed. The memory cells belonging to the threshold voltage distribution corresponding to program state Q3 will be programmed to have threshold voltages belonging to the threshold voltage distributions respectively corresponding to program states P6 and P7 according to the data to be programmed.
As described above, the sophisticated program operation of coarse programmed memory cells belonging to a word line (e.g., WL0) is performed by a one-step program operation for adjacent word lines (e.g., WL2, WLl) It will be done after operation. At this point, as shown by the solid line in box 32 of FIG. 1C, distributions of coarse programmed memory cells belonging to a word line (e.g., WL0) are applied to adjacent word lines (e.g., WL2, WL1) Will be widened by the coupling that occurs when the memory cells to which they belong are programmed. For this reason, it is difficult to accurately read data from roughly programmed memory cells.
The memory cells belonging to the word line WL0 will be programmed to have the final threshold voltage distributions P1 to P7 as shown in box 33 of FIG. 1C. This operation is called sophisticated program operation. As described above, the sophisticated program operation requires previously programmed data (e.g., first through third page data), which may include previously programmed data from memory cells belonging to word line WL0 (Or data maintained by the memory device) provided by the memory controller because it is difficult to read accurately. As shown by the solid line in box 33 of Fig. 1 (c), the sophisticated programmed memory cells can also be widened due to coupling occurring when the distributions of memory cells belonging to adjacent word lines are programmed.
Thereafter, a one-step program operation, a coarse program operation, and a sophisticated program operation for each word line are performed in accordance with the program sequence described in FIG. 1A, which will be performed in the same manner as described in FIG. 1C.
2 is a block diagram that schematically illustrates a data storage system in accordance with exemplary embodiments of the present invention.
Referring to FIG. 2, a data storage system 1000 will include a multi-bit memory device 100, a memory controller 200, and a host 300 as non-volatile memory devices. The multi-bit memory device 100 may be comprised of one or more memory chips. The multi-bit memory device 100 and the memory controller 200 will constitute a data storage device, such as a memory card, a solid state drive (SSD), a memory stick, or the like. The multi-bit memory device 100 includes a plurality of memory blocks (sectors / banks), each memory block including memory cells arranged in rows and columns. Each of the memory cells will store multi-bit (or multi-level) data. The memory cells may be arranged to have a two-dimensional array structure or a three-dimensional / vertical array structure. An exemplary three-dimensional array structure is disclosed in U.S. Patent Application Publication No. 20080/0023747 entitled " SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS ON MULTIPLE LAYERS " and US Patent Publication No. 2008/0084729 entitled "SEMICONDUCTOR DEVICE WITH THREE- DIMENSIONAL ARRAY STRUCTURE ", each of which is incorporated by reference in this application.
The memory blocks of the multi-bit memory device 100 according to the exemplary embodiment of the present invention may be divided into at least a first area 101 and a second area 102. [ Here, it will be well understood that the division of the first and second regions 101 and 102 is performed not logically but physically. The distinction of the first and second regions 101 and 102 is logically variable. The memory blocks belonging to the first area 101 will be programmed in a manner different from the memory blocks belonging to the second area 102. [ For example, the memory blocks belonging to the first area 101 are programmed according to the single-bit programming scheme (hereinafter referred to as SLC programming scheme), the memory blocks belonging to the second area 102 are programmed according to the multi- (Hereinafter referred to as the MLC program method) (for example, the N-step reprogramming method described above). In other words, each of the memory cells in the first area 101 stores 1-bit data, and each of the memory cells in the second area 102 stores M-bit data (M is an integer of 3 or greater) . In addition, each of the memory cells in the first region 101 stores a smaller number of data bits than the M-bit data (M is an integer greater than or equal to 3) stored in each of the memory cells in the second region 102 will be.
2, the memory controller 200 will be configured to control the multi-bit memory device 100 in response to a request from the host 300. [ The memory controller 200 will include a buffer memory 201. The buffer memory 201 will be used to temporarily store the data transferred from the host 300 and to temporarily store the data read from the multi-bit memory device 100. The memory controller 200 will control the program operation of the memory device 100 in a static scheduling manner. For example, when data of the minimum program unit for the first area 101 is stored in the buffer memory 201, the memory controller 200 controls the multi- The bit memory device 100 will be controlled. This is referred to as buffer program operation. If the minimum program unit data for the second area 102 is collected in the first area 101, the memory controller 200 determines that the minimum program unit data for the second area 102 is the second area 102, Bit memory device 100 to be stored in the multi-bit memory device 100. This is referred to as main program operation. The buffer program operation and the main program operation will be described later in detail.
In the exemplary embodiment, the minimum program unit for the first area 101 and the minimum program unit for the second area 102 will be variously determined according to the programming scheme, number of bits per cell, and so on. The minimum program unit for the first area 101 is different from the minimum program unit for the second area 102. [
The buffer memory 201 of the memory controller 200 stores data in the first area 101 through the buffer program operation and stores data in the second area 102 through the main program operation Can be minimized. In other words, there is no need to hold data for the sophisticated program operation in the buffer memory 201. [ Therefore, the size of the buffer memory 201 of the memory controller 200 can be minimized.
FIG. 3 is a diagram illustrating an exemplary address scrambling scheme of a multi-bit memory device in which 4-bit data per cell is stored and a reprogramming method is applied, and FIG. 4 illustrates data Fig. The operation of a data storage system according to an exemplary embodiment of the present invention will now be described in detail with reference to the drawings.
For convenience of description, it is assumed that each memory block includes 64 word lines (WL0 to WL63), and each memory cell stores 4-bit data, as shown in Fig. According to this assumption, 256 pages will be stored in each memory block. Here, the term "page" will be used to denote the page data.
If the data D0 of the minimum program unit for the first area 101 is transferred from the host 300 to the buffer memory 201 of the memory controller 200 and the data D0 stored in the buffer memory 201, Bit memory device 100 will be programmed into the first area 101 of the multi-bit memory device 100 under the control of the memory controller 200. As described above, the data D0 will be programmed in the first area 101 through the SLC program operation. The memory controller 200 determines whether or not the data of the minimum program unit for the second area 102 is collected in the first area 101 and controls the main program operation according to the determination result. Whether data of the minimum program unit for the second area 102 is collected in the first area 101 or not will be determined based on the page address. Since only one page D0 is stored in the first area 101, the main program operation will not be performed. When the data D1 of the minimum program unit for the first area 101 is transferred from the host 300 to the buffer memory 201 of the memory controller 200, Bit memory device 100 will be programmed into the first area 101 of the multi-bit memory device 100 under the control of the controller 200. [ Since the data of the minimum program unit for the second area 102 (for example, two pages required for the one-step program operation) are collected in the first area 101, the memory controller 200 controls the first area Bit memory device 100 so that the data D0 and D1 stored in the first area 102 and the data D0 and D1 stored in the second area 102 are stored in the second area 102. [ That is, the one-step program operation for the word line WL0 will be performed based on the data D0 and D1 stored in the first area 101. [
As described above, when data of the minimum program unit for the first area 101 is stored in the buffer memory 201, the data stored in the buffer memory 201 is stored in the multi-bit memory 201 under the control of the memory controller 200. [ Will be programmed into the first area 101 of the device 100. [ Data will be stored in the first area 101 through the SLC program operation. When the data Di (i = 0 to 255) of the minimum program unit for the first area 101 is transferred from the host 300 to the memory controller 200, as shown in FIG. 4, the buffer memory 201 Will be programmed in the first area 101 through the operation of the SLC program under the control of the memory controller 200. [ The memory controller 200 determines whether or not the data of the minimum program unit for the second area 102 is stored in the buffer memory 201 in addition to the determination of whether or not the data of the minimum program unit for the first area 101 is stored in the buffer memory 201 1 area 101. In this case, The memory controller 200 will control the one-step program operation, the coarse program operation, or the fine program operation for the second region 102 according to the determination result. More specifically, it is as follows.
The one-step program operation, the coarse program operation, or the fine program operation for the second area 102 will be determined according to the address scramble sequence shown in FIG. Step programming operation for the word line WL0 based on the data D0 and D1 stored in the first area 101 when data D0 and D1 are stored in the first area 101, Lt; / RTI > When the data D2 and D3 are stored in the first area 101, a one-step program operation for the word line WL1 will be performed. That is, the one-step programming operation for the word line WL1 will be performed based on the data D2 and D3 stored in the first area 101. [
Subsequently, when the data D4 and D5 are stored in the first area 101, the rough program for the word line WL0 based on the data D0, D1, D4 and D5 stored in the first area 101 An operation will be performed. The one-step programming operation for the word line WL2 will be performed based on the data D6 and D7 stored in the first area 101 when the data D6 and D7 are stored in the first area 101. [ When the data D8 and D9 are stored in the first area 101, the rough program operation for the word line WL1 is performed based on the data D2, D3, D8 and D9 stored in the first area 101 will be. The data D0, D1, D4, and D5 stored in the first area 101 are subjected to the coarse programming operation on the word line WL1 based on the data D8 and D9 stored in the first area 101, A sophisticated program operation on the word line WL0 will be performed. Thereafter, until the data D254 is stored in the first area 101, the remaining data D10 to D253 are subjected to the one-step program operation of the data D6 and D7, the coarse program operation of the data D8 and D9 And the data D0, D1, D4, and D5 in the same manner as the sophisticated program operation.
When data D254 and D255 are stored in the first area 101, a rough program operation on the word line WL63 will be performed based on the data D254 and D255 stored in the first area 101. [ The data D246, D247, D252, and D253 stored in the first area 101 are subjected to the coarse programming operation on the word line WL63 based on the data D254 and D255 stored in the first area 101 A sophisticated program operation on the word line WL62 will be performed. Finally, based on the data D250, D251, D254, and D255 stored in the first area 101, a sophisticated program operation on the word line WL63 will be performed.
As will be understood from FIG. 4, the SLC program operation, a series of SLC and one-step program operations, a series of SLC and coarse programs (e.g., Operations, a series of SLC, coarse and fine program operations, and a series of SLC, coarse, sophisticated, and sophisticated program operations. An SLC program operation, a one-step program operation, a coarse program operation, or a sophisticated program operation may be performed, for example, when corresponding instructions are provided from the memory controller 200 to the multi-bit memory device 100. Or a series of operations (e.g., SLC program operation, a series of SLC and one-step program operations, a series of SLC and coarse program operations, a series of SLC, coarse and fine program operations, Bit memory device 100 is provided with a set of instructions to inform a program pattern comprised of a set of instructions (e.g., a set of SLC, coarse, sophisticated, and sophisticated program operations) It can automatically perform a series of operations. A series of program operations belonging to the program pattern will be changed according to the address scramble scheme, the number of bits per cell, and the like. Table 1 below shows the program patterns that are applied to the program operations described in FIGS. 3 and 4. The instruction set that informs the program pattern will also include the addresses needed for read and program operations.
Program pattern Pattern 1 SLC program Pattern 2 SLC program + 1-step program Pattern 3 SLC program + rough program Pattern 4 SLC program + rough program + sophisticated program Pattern 5 SLC program + rough program + sophisticated program + sophisticated program
5 is a diagram schematically illustrating a data flow according to the series of single-bit program operations and the one-step program operation described in FIG.
5, the data D0 is loaded into the page buffer 103 of the multi-bit memory device 100 and the data D0 loaded into the page buffer 103 is stored in the first area 101 do. The data D1 is then loaded into the page buffer 103 of the multi-bit memory device 100 and the data D1 loaded into the page buffer 103 is stored in the first area 101. [ When the data D0 and D1 are stored in the first area 101, that is, when data (for example, 2 pages) of the minimum program unit for the second area 102 is accumulated in the first area 101 The data D0 and D1 from the first area 101 will be sequentially read by the page buffer 103. [ Thereafter, the data D0 and D1 stored in the page buffer will be stored in the second area 102 in accordance with the one-step program operation. Data transfer from the first area 101 to the page buffer 103 will be performed by the SLC read operation. A series of single-bit / SLC read operations and one-step program operations will be automatically performed in the multi-bit memory device 100 without the intervention of the memory controller 200. As another example, a single-bit / SLC read operation, a one-step program operation, a coarse program operation, and a sophisticated program operation may be performed under the control of the memory controller 200. Each of the one-step program operations shown in FIG. 4 is performed substantially the same as that shown in FIG. 5, and the description thereof will therefore be omitted.
FIG. 6 is a schematic diagram illustrating a data flow according to a series of single-bit program operations and coarse / fine program operations illustrated in FIG.
6, the data D4 is loaded into the page buffer 103 of the multi-bit memory device 100 and the data D4 loaded into the page buffer 103 is stored in the first area 101 do. The data D5 is then loaded into the page buffer 103 of the multi-bit memory device 100 and the data D5 loaded into the page buffer 103 is stored in the first area 101. [ When data D4 and D5 are stored in the first area 101, that is, data of the minimum program unit for the second area 102 is collected in the first area 101, as shown in FIG. 6 The data D0, D1, D4, and D5 from the first area 101 will be sequentially read by the page buffer 103 in accordance with the SLC read operation. Then, the data D0, D1, D4, and D5 stored in the page buffer 103 will be stored in the second area 102 by a coarse program operation. A series of single-bit / SLC read operations and coarse program operations will be automatically performed within the multi-bit memory device 100 without the intervention of the memory controller 200. As another example, a single-bit / SLC read operation, a one-step program operation, a coarse program operation, and a sophisticated program operation may be performed under the control of the memory controller 200. Each of the coarse program operations shown in FIG. 4 is performed substantially the same as that shown in FIG. 6, and the description thereof will therefore be omitted.
The sophisticated program operation will also be done in the same manner as the coarse program operation. For example, a sophisticated program operation on the word line WL0 sequentially transfers data D0, D1, D4, and D5 from the first area 101 to the page buffer 103 in accordance with the SLC read operation, (D0, D1, D4, D5) stored in the second area 103 in the second area 102. [
FIG. 7 is a schematic diagram illustrating a data flow according to the series of single-bit program operations, coarse program operations, and sophisticated program operations described in FIG.
7, the data D8 is loaded into the page buffer 103 of the multi-bit memory device 100 and the data D8 loaded into the page buffer 103 is stored in the first area 101 do. The data D9 is then loaded into the page buffer 103 of the multi-bit memory device 100 and the data D9 loaded into the page buffer 103 is stored in the first area 101. [ When the data D8 and D9 are stored in the first area 101, that is, when the data of the minimum program unit for the second area 102 is collected in the first area 101, A coarse program operation will be performed. That is, the data D2, D3, D8, and D9 from the first area 101 will be sequentially read by the page buffer 103 in accordance with the SLC read operation. The data D2, D3, D8, and D9 stored in the page buffer 103 will be stored in the second area 102 by coarse program operation. After the coarse program operation on the word line WL1 is performed, a sophisticated program operation on the word line WL0 will be performed without the intervention of the memory controller 200. [ That is, the data D0, D1, D4, and D5 from the first area 101 will be sequentially read by the page buffer 103 in accordance with the SLC read operation. The data D0, D1, D4, and D5 stored in the page buffer 103 will be stored in the second area 102 by a sophisticated program operation.
8 is a flowchart for explaining a read operation of the memory system shown in FIG. Hereinafter, a read operation of the memory system according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.
In step S100, a read operation from the outside (for example, a host) will be requested. In step < RTI ID = 0.0 > S110, < / RTI > the memory controller 200 will determine whether the read request is associated with a word line for which a sophisticated program operation has been completed. Whether the sophisticated program operation for each word line has been completed or not will be determined based on the address mapping information. If it is determined that the read request is associated with a word line for which a sophisticated program operation has been completed, then in step 120, the memory controller 200 controls the multi-bit memory device 100 to read the requested data from the second area 102 something to do. The read operation for the second area 102 will be an MLC read operation. The data read from the second area 102 will be temporarily stored in the buffer memory 201 of the memory controller 200. [ Thereafter, the procedure will proceed to step S140. On the other hand, if the read request is determined to be associated with a word line for which a sophisticated program operation has not been completed, then in step 130, the memory controller 200 determines whether the requested data is read from the first area 101, (100). The read operation for the first area 101 will be an SLC read operation. The data read from the first area 101 will be temporarily stored in the buffer memory 201 of the memory controller 200. [ Thereafter, the procedure will proceed to step S140. In step S140, data stored in the buffer memory 201 may be transmitted to the host 300. [
FIG. 9 is a diagram showing an exemplary address scrambling scheme of a multi-bit memory device in which 3-bit data per cell is stored and a 3-step reprogramming method is applied, and FIG. Figure 2 is a schematic diagram of data flow during operation. Hereinafter, the program operation of the data storage system according to another exemplary embodiment of the present invention will be described in detail with reference to the drawings.
For convenience of description, it is assumed that each memory block includes 64 word lines (WL0 to WL63), and each memory cell stores 3-bit data, as shown in Fig. According to this assumption, each memory block will store 192 pages.
3 and 4, when the data Di (i = 0 to 191) of the minimum program unit for the first area 101 is stored in the buffer memory 201 of the memory controller 200, The data Di stored in the buffer memory 201 will be programmed into the first area 101 of the multi-bit memory device 100 through the SLC program operation. In addition, the memory controller 200 will determine whether or not the data of the minimum program unit for the second area 102 is collected in the first area 101. A one-step program operation, a coarse program operation, or a sophisticated program operation for the second area 102 will be performed according to the determination result. The one-step program operation, coarse program operation, or fine program operation for the second area 102 will be determined according to the address scramble sequence shown in FIG. Step programming operation for the word line WL0 based on the data D0 and D1 stored in the first area 101 when data D0 and D1 are stored in the first area 101, Lt; / RTI > When the data D2 and D3 are stored in the first area 101, a one-step program operation for the word line WL1 will be performed. That is, the one-step programming operation for the word line WL1 will be performed based on the data D2 and D3 stored in the first area 101. [
Subsequently, when the data D4 is stored in the first area 101, a rough program operation for the word line WL0 is performed based on the data D0, D1, and D4 stored in the first area 101 . Step programming operation for the word line WL2 will be performed based on the data D5 and D6 stored in the first area 101 when the data D5 and D6 are stored in the first area 101. [ When the data D7 is stored in the first area 101, the rough program operation on the word line WL1 will be performed based on the data D2, D3, D7 stored in the first area 101. [ The data D0, D1 and D4 stored in the first area 101 are subjected to the coarse programming operation on the word line WL1 based on the data D2, D3 and D7 stored in the first area 101 A sophisticated program operation on the word line WL0 will be performed. Thereafter, until the data D191 is stored in the first area 101, the remaining data D8 to D190 are subjected to the one-step program operation of the data D5 and 6, the coarse program operation of the data D7, Will be stored in the second area 102 in the same order as the sophisticated program operation of the data D0, D1, and D4.
When data D191 is stored in the first area 101, a rough program operation on the word line WL63 will be performed based on the data D188, D189, and D191 stored in the first area 101. [ The data D185, D186 and D190 stored in the first area 101 are subjected to the coarse programming operation on the word line WL63 based on the data D188, D189 and D191 stored in the first area 101 A sophisticated program operation on the word line WL62 will be performed. Finally, a sophisticated program operation on the word line WL63 will be performed based on the data (D188, D189, D191) stored in the first area 101. [
Even if 3-bit data is stored in each memory cell, a method of reading data from the multi-bit memory device 100 will be performed substantially the same as that described in FIG. Therefore, the description thereof will therefore be omitted.
As described in FIG. 4, the program operation described in FIG. 10 will also include program patterns. Such program patterns may include SLC program operation, a series of SLC and one-step program operations, a series of SLC and coarse program operations, a series of SLC, coarse and fine program operations, and a series of SLC, Sophisticated program operations. Each program operation may be performed each time an instruction is transferred from the memory controller 200 to the multi-bit memory device 100, and a series of program operations belonging to each program pattern may be executed using the instruction set described above, Or may be performed automatically by the memory device 100. [
11 schematically illustrates a page interleaving method according to an exemplary embodiment of the present invention.
For convenience of explanation, it is assumed that 4-page data is stored in memory cells belonging to one word line. Generation of common ECC data will be done page by page. On the other hand, in the case of the page interleaving method for keeping the error rate of each page constant, the pages to be stored in the memory cells belonging to each word line are divided into a plurality of ECC groups (for example, four ECC groups) , ECC data will be generated based on the data belonging to each ECC group. When the page interleaving scheme is applied to the data storage system 1000, the minimum program unit for the first area 101 will be different from that described above. This will be described in detail later.
FIG. 12 is a diagram schematically illustrating a data flow during a program operation of a data storage system to which the page interleaving method illustrated in FIG. 11 is applied. Hereinafter, the program operation of the data storage system according to another exemplary embodiment of the present invention will be described in detail with reference to the drawings.
For convenience of description, it is assumed that each memory block includes 64 word lines (WL0 to WL63), and each memory cell stores 4-bit data. According to this assumption, 256 pages will be stored in each memory block. The program operation of the data storage system to which the page interleaving scheme is applied under the condition that the address scramble scheme described in FIG. 3 is used will be described.
Referring to FIG. 12, data will be transmitted from the host 300 to the memory controller 200. Since the page interleaving scheme is used, the memory controller 200 will wait until the data to be stored in the word line WL0, that is, the 4-page data D0, D1, D4 and D5 is stored. Once the data to be stored in the word line WL0, that is, the 4-page data D0, D1, D4 and D5 is stored in the buffer memory 201, the data to be stored in the word line WL0, Bit memory device 100 will be sequentially stored in the first area 101 under the control of the memory controller 200. In this case, As mentioned above, data will be programmed in the first area 101 via a single-bit / SLC program operation. Thereafter, the one-step programming operation for the word line WL0 will be performed based on the data D0 and D1 stored in the first area 101. [ The data to be stored in the word line WL1, that is, the 4-page data D2, D3, D8, and D9, is input to the memory controller 200 from the host 300 when the page data D6 to D9 are input again to the memory controller 200. [ Bit memory device 100 in accordance with the control of the controller 200 in the first area 101 of the multi-bit memory device 100. The one-step programming operation for the word line WL1 and the coarse programming operation for the word line WL0 are then performed based on the data D2, D3 and D4, D5 stored in the first area 101 Will be performed sequentially.
The data to be stored in the word line WL1, that is, the 4-page data D6, D7, D12, and D13, is stored in the buffer memory 201, Bit memory device 100 according to the first embodiment of the present invention. Then, the one-step programming operation for the word line WL3, the rough program operation for the word line WL1, and the sophisticated programming operation for the word line WL0 are performed on the data stored in the first area 101 Will be performed sequentially. The operation pattern performed when the data D10 to D13 is input will be repeatedly performed until the data D254 is stored in the buffer memory 201. [
The data to be stored in the word line WL63, that is, the 4-page data D250, D251, D254, and D255, are stored in the buffer memory 201 of the memory controller 200, Bit memory device 100 according to the control of the memory controller 200 of FIG. Then, a one-step program operation for the word line WL63, a coarse program operation for the word line WL62, a fine program operation for the word line WL61, a rough program operation for the word line WL63, A sophisticated program operation for the word line WL62 and a sophisticated program operation for the word line WL63 will be sequentially performed based on the data stored in the first area 101. [
In an exemplary embodiment, the size of the first area 101 of the multi-bit memory device 100 may be determined by the number of open blocks and the minimum number of pages that must be maintained by the first area 101. A random write to the first memory block and a second memory block other than the first memory block may be requested before the first memory block is filled with data. In this case, the first memory block is referred to as an open block. The number of open blocks may be determined differently depending on the policy that manages the multi-bit memory device 100. The minimum number of pages to be maintained by the first area 101 is the number of pages D0 to D9 stored in the second area 102 before completing a sophisticated program operation for any word line (e.g., WL0) . The minimum number of pages to be maintained by the first area 101 may be, for example, 10-pages in the case of the address scrambling scheme of FIG.
FIG. 13 is a diagram showing another exemplary address scrambling scheme of a multi-bit memory device in which 3-bit data per cell is stored and a reprogramming method is applied, and FIG. 14 is a diagram illustrating an example of address scrambling performed in accordance with the address scramble scheme shown in FIG. 13 Figure 2 is a schematic diagram of data flow during program operation. The operation of a data storage system according to an exemplary embodiment of the present invention will now be described in detail with reference to the drawings.
For convenience of description, as shown in FIG. 13, it is assumed that each memory block includes 64 word lines (WL0 to WL63), and each memory cell stores 3-bit data. According to this assumption, each memory block will store 192 pages.
If the data D0 of the minimum program unit for the first area 101 is transferred from the host 300 to the buffer memory 201 of the memory controller 200 and the data D0 stored in the buffer memory 201, Bit memory device 100 will be programmed into the first area 101 of the multi-bit memory device 100 under the control of the memory controller 200. As described above, the data D0 will be programmed in the first area 101 through the SLC program operation. The memory controller 200 determines whether or not the data of the minimum program unit for the second area 102 is collected in the first area 101 and controls the main program operation according to the determination result. Whether data of the minimum program unit for the second area 102 is collected in the first area 101 or not will be determined based on the page address. Since only one page D0 is stored in the first area 101, the main program operation will not be performed. When the data D1 of the minimum program unit for the first area 101 is transferred from the host 300 to the buffer memory 201 of the memory controller 200, Bit memory device 100 will be programmed into the first area 101 of the multi-bit memory device 100 under the control of the controller 200. [
When the data D2 of the minimum program unit for the first area 101 is transferred from the host 300 to the buffer memory 201 of the memory controller 200, the data D2 stored in the buffer memory 201 is transferred to the memory Bit memory device 100 will be programmed into the first area 101 of the multi-bit memory device 100 under the control of the controller 200. [ Since the data of the minimum program unit for the second area 102 (for example, two pages required for the one-step program operation) are collected in the first area 101, the memory controller 200 controls the first area Bit memory device 100 so that the data D0 and D2 stored in the first area 102 and the data D0 and D2 stored in the second area 102 are stored in the second area 102. [ That is, the one-step program operation for the word line WL0 will be performed based on the data D0 and D2 stored in the first area 101. [
When the minimum program unit data D3 for the first area 101 is transferred from the host 300 to the buffer memory 201 of the memory controller 200, the data D3 stored in the buffer memory 201 is transferred to the memory Bit memory device 100 will be programmed into the first area 101 of the multi-bit memory device 100 under the control of the controller 200. [ When the data D4 of the minimum program unit for the first area 101 is transferred from the host 300 to the buffer memory 201 of the memory controller 200, the data D4 stored in the buffer memory 201 is transferred to the memory Bit memory device 100 will be programmed into the first area 101 of the multi-bit memory device 100 under the control of the controller 200. [ Since the data of the minimum program unit for the second area 102 (for example, two pages required for the one-step program operation) are collected in the first area 101, the memory controller 200 controls the first area Bit memory device 100 so that the data D1 and D4 stored in the second area 102 are stored in the second area 102. [ That is, the one-step program operation for the word line WL1 will be performed based on the data D1 and D4 stored in the first area 101. [
As described above, when data of the minimum program unit for the first area 101 is stored in the buffer memory 201, the data stored in the buffer memory 201 is stored in the multi-bit memory 201 under the control of the memory controller 200. [ Will be programmed into the first area 101 of the device 100. [ Data will be stored in the first area 101 through the SLC program operation. When the data Di of the minimum program unit (i = 0 to 191) for the first area 101 is transferred from the host 300 to the memory controller 200, as shown in FIG. 14, Will be programmed in the first area 101 through the operation of the SLC program under the control of the memory controller 200. [ The memory controller 200 determines whether or not the data of the minimum program unit for the second area 102 is stored in the buffer memory 201 in addition to the determination of whether or not the data of the minimum program unit for the first area 101 is stored in the buffer memory 201 1 area 101. In this case, The memory controller 200 will control the one-step program operation, the coarse program operation, or the fine program operation for the second region 102 according to the determination result. More specifically, it is as follows.
The one-step program operation, coarse program operation, or sophisticated program operation for the second region 102 will be determined according to the address scramble sequence shown in Fig. Step programming operation for the word line WL0 based on the data D0 and D2 stored in the first area 101 when the data D0 and D2 are stored in the first area 101, Lt; / RTI > When the data D1 and D4 are stored in the first area 101, a one-step program operation for the word line WL1 will be performed. That is, the one-step programming operation for the word line WL1 will be performed based on the data D1 and D4 stored in the first area 101. [
Subsequently, when the data D5 is stored in the first area 101, a rough program operation for the word line WL0 is performed based on the data DO, D2, and D5 stored in the first area 101 . The one-step programming operation for the word line WL2 will be performed based on the data D3 and D7 stored in the first area 101 when the data D3 and D7 are stored in the first area 101. [ When the data D8 is stored in the first area 101, a rough program operation on the word line WL1 will be performed based on the data D1, D4, and D8 stored in the first area 101. [ D2 and D5 stored in the first area 101 after the coarse programming operation on the word line WL1 is performed based on the data D1, D4 and D8 stored in the first area 101, A sophisticated program operation on the word line WL0 will be performed. Until the data D191 is stored in the first area 101, the remaining data D10 to D190 are stored in the first area 101 and the remaining data D10 to D190 are stored in the first area 101, The program operation, and the sophisticated program operation of the data D0, D2, and D5 in the same manner as in the second area 102. [
When the data D191 is stored in the first area 101, the rough program operation on the word line WL63 will be performed based on the data D186, D189, and D191 stored in the first area 101. [ D187 and D190 stored in the first area 101 after the coarse programming operation on the word line WL63 is performed based on the data D186, D189 and D191 stored in the first area 101 A sophisticated program operation on the word line WL62 will be performed. Finally, a sophisticated program operation on the word line WL63 will be performed based on the data (D186, D189, D191) stored in the first area 101. [
14, a SLC program operation (first program pattern), a series of SLC and one-step programs (first program pattern) are executed according to information (e.g., page address information) related to data to be stored in the first area 101 (A second program pattern), a series of SLC and coarse program operations (a third program pattern), a series of SLC, coarse and sophisticated program operations (a fourth program pattern), and a series of SLC, coarse, And sophisticated program operations (fifth program pattern) can be determined. As described with reference to Table 1, the SLC program operation, the one-step program operation, the coarse program operation, or the sophisticated program operation may be performed, for example, by a corresponding instruction from the memory controller 200 to the multi- 100), respectively. Or a series of operations (e.g., SLC program operation, a series of SLC and one-step program operations, a series of SLC and coarse program operations, a series of SLC, coarse and fine program operations, Bit memory device 100 is provided with a set of instructions to inform a program pattern comprised of a set of instructions (e.g., a set of SLC, coarse, sophisticated, and sophisticated program operations) It can automatically perform a series of operations. A series of program operations belonging to the program pattern will be changed according to the address scramble scheme, the number of bits per cell, and the like.
15 is a schematic diagram illustrating a page buffer structure of a multi-bit memory device according to an exemplary embodiment of the present invention.
Referring to FIG. 15, the bit line BL is connected to a plurality of strings (or NAND strings), and one of the strings will be connected to the page buffer PB through the bit line BL. The page buffer PB will contain a plurality of latches. The number of latches included in the page buffer PB may be determined according to the number of data bits stored in the memory cell. Each of the strings includes a plurality of memory cells, and each of the memory cells will store multi-bit data. For example, each memory cell will store 3-bit data. In this case, the page buffer PB will include at least four latches L1, L2, L3, L4. Data to be stored in the first area 101 in the buffer program operation will be loaded into the first latch L1. During the main program operation, data stored in the first area 101 will be read through the latch L1. The data stored in the latch L1 will be dumped to either of the second to fourth latches L2, L3, L4 under the control of the memory controller 200. [ In an exemplary embodiment, the memory controller 200 may be coupled to the multi-bit memory device 100 to transfer the data of the first latch L1 to either of the second to fourth latches L2, L3, A specific command (for example, a command for notifying a dump operation) will be provided. At this time, information specifying the latch to which the data of the first latch L1 is to be dumped will also be provided to the multi-bit memory device 100 in the memory controller 200.
Although FIG. 15 shows a page buffer that includes only four latches L1, L2, L3, and L4, the page buffer may be configured to include more or fewer latches, depending on the number of bits per cell. Further, the page buffer PB may be further provided with a cache register.
FIG. 16 is a view showing a command sequence for the one-step program operation described in FIGS. 13 and 14, and FIG. 17 is a diagram showing a data flow according to the one-step program command sequence shown in FIG. The operation of a data storage system according to an exemplary embodiment of the present invention will now be described in detail with reference to the drawings.
Prior to the description, the one-step program operation described in Figs. 13 and 14 will be performed when a two-page, which is the minimum program unit for the second area 102, is stored in the first area 101. [ As a main program operation, the one-step program operation for the second area 102 involves two SLC read operations for the first area 101 and one MLC program operation for the second area 102 will be.
In the case of the data storage system 1000 according to the exemplary embodiment of the present invention, prior to performing the one-step program operation, the command DAh for switching to the SLC operating mode is transferred from the memory controller 200 to the multi- Bit memory device 100 as shown in FIG. When the mode changeover command DAh is input, the multi-bit memory device 100 will recognize the command provided from the memory controller 200 as an instruction related to the SLC operation. The SLC operation will include the SLC read operation, the data dump operation, and the like described above.
16, the memory controller 200 sends a series of instructions 00h, an address Addr5, and an instruction 39h to the multi-bit memory device 100 ). At this time, the address Addr5 may be an address for designating one page (for example, the first page P1) of the two-page data necessary for the one-step program operation. After the instruction 39h is input, the page buffer 103 of the multi-bit memory device 100 reads the first page data P1 from the first area 101, as shown in Fig. The read data P1 will be stored in the first latch L1. During the read operation, as shown in FIG. 16, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the busy state. After the read operation is completed, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the ready state.
16, the memory controller 200 responds to the status of the Ready / busy signal R / B so that data is written to the multi-bit memory device 100 along with the dump command C0h (L1 - > L3) for specifying a latch (e.g., L3) to be dumped. As the dump instruction C0h is input, the multi-bit memory device 100 will control the page buffer 103 so that the data P1 of the latch L1 is dumped to the latch L3. During the dump operation, as shown in FIG. 16, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the busy state. After the dump operation is completed, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the ready state.
16, the memory controller 200 responds to the state of the ready / busy signal R / B by sending a series of instructions 00h, Addr5, and an instruction 39h to the multi-bit memory device 100. [ At this time, the address Addr5 may be an address for designating the remaining page (for example, the second page P2) of the two-page data necessary for the one-step program operation. After the instruction 39h is input, the page buffer 103 of the multi-bit memory device 100 reads the first page data P2 from the first area 101, as shown in Fig. The read data P2 will be stored in the first latch L1. During the read operation, as shown in FIG. 16, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the busy state. After the read operation is completed, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the ready state.
16, the memory controller 200 responds to the status of the Ready / busy signal R / B so that data is written to the multi-bit memory device 100 along with the dump command C0h (L? L4) for specifying a latch (e.g., L4) to be dumped. As the dump command C0h is input, the multi-bit memory device 100 will control the page buffer 103 so that the data P2 of the latch L1 is dumped to the latch L4. During the dump operation, as shown in FIG. 16, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the busy state. After the dump operation is completed, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the ready state.
Once the data necessary for the one-step program operation is ready, a one-step program operation for the second area 102 will be performed. Prior to performing the one-step program operation, the memory controller 200 will send a command DFh for mode switching to the multi-bit memory device 100. Such an instruction (DFh) is intended to exit from the mode for SLC operation. As the instruction DFh is input, the multi-bit memory device 100 will recognize the instruction provided from the memory controller 200 as a command related to the main program operation, e.g., MLC operation.
Thereafter, the memory controller 200 will send a series of instructions 8Bh, an address Addr5, and an instruction 10h to the multi-bit memory device 100, as shown in Fig. At this time, the address Addr5 will be an address for designating one of the pages to be programmed in one step (for example, the first page). No data will be transferred from the memory controller 200 to the multi-bit memory device 100 because the data necessary for the one-step program operation is prepared in the page buffer 103. [ After the instruction 10h is input, the data P1 and P2 stored in the page buffer 103 will be programmed in the second area 102, as shown in Fig. During the program operation, as shown in FIG. 16, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the busy state. After the program operation is completed, the multi-bit memory device 100 will set the ready / busy signal R / B to indicate the ready state.
According to the foregoing description, the one-step program operation can be constituted by a data setup section and a program section (or a program check section). During the one-step program operation, as shown in FIG. 16, the data setup period will include a first page data setup period and a second page data setup period. Each of the first and second page data setup intervals will include an SLC read operation and a dump operation. A mode change is performed prior to the first page data set, and a mode change will be performed before main programming.
FIG. 18 is a view showing a command sequence for the coarse program operation described in FIGS. 13 and 14, and FIG. 19 is a diagram showing a data flow according to the coarse program command sequence shown in FIG. The operation of a data storage system according to an exemplary embodiment of the present invention will now be described in detail with reference to the drawings.
Prior to the description, the coarse program operation described in Figs. 13 and 14 will be performed when a 3-page, which is the minimum program unit for the second area 102, is stored in the first area 101. [ The coarse program operation for the second area 102 will involve three SLC read operations for the first area 101 and one MLC program operation for the second area 102. [
Each of the SLC read operations is substantially the same as that described in Figs. 16 and 17, as shown in Fig. 18, and the description thereof will therefore be omitted. Prior to performing the SLC read operation on the first page data, a command DAh for mode switching will be sent from the memory controller 200 to the multi-bit memory device 100, as shown in Figure 18 . The MLC program operation for the second region 102 is substantially the same as that described in Figures 16 and 17 except that the 3-bit data is stored in the second region 102, Will be. Prior to performing the coarse program operation, a command DFh for mode switching will be transferred from the memory controller 200 to the multi-bit memory device 100, as shown in FIG.
Although not shown in the figure, the sophisticated program operation as the main program operation will be performed in the same manner according to the command sequence shown in Fig. Since the instruction sequence for sophisticated program operation is the same as the instruction sequence for rough program operation, rough program operation and sophisticated program operation will be distinguished based on the address Addr5 provided in the program verify period. For example, the address Addr5 provided in the program check interval related to the coarse program operation is an address for designating the second page, and the address Addr5 provided in the program check interval related to the sophisticated program operation corresponds to the third page It will be the address to specify.
FIG. 20 is a diagram schematically showing a data flow during a page interleaving method illustrated in FIG. 11 and a program operation of a data storage system to which the address scramble method described in FIG. 13 is applied. Hereinafter, the program operation of the data storage system according to another exemplary embodiment of the present invention will be described in detail with reference to the drawings.
For convenience of description, it is assumed that each memory block includes 64 word lines (WL0 to WL63), and each memory cell stores 3-bit data. According to this assumption, each memory block will store 192 pages. The program operation of the data storage system to which the page interleaving scheme is applied under the condition that the address scramble scheme described in FIG. 13 is used will be described.
Referring to FIG. 20, data will be transmitted from the host 300 to the memory controller 200. Since the page interleaving scheme is used, the memory controller 200 will wait until the data to be stored in the word line WL0, that is, the 3-page data DO, D2, and D5 is stored. Once the data to be stored in the word line WL0, that is, the 3-page data D0, D2 and D5, is stored in the buffer memory 201, the data to be stored in the word line WL0, D2 and D5 will be sequentially stored in the first area 101 of the multi-bit memory device 100 under the control of the memory controller 200. [ As mentioned above, data will be programmed in the first area 101 via SLC program operation. Thereafter, the one-step programming operation for the word line WL0 will be performed based on the data D0 and D2 stored in the first area 101. [ Page data D6 to D8 are input from the host 300 to the memory controller 200, the data to be stored in the word line WL1, i.e., the 3-page data D1, D4 and D8, Bit memory device 100 in accordance with the control of the memory controller (not shown). The one-step programming operation for the word line WL1 and the coarse programming operation for the word line WL0 are then performed on the data D1, D4 and D0, D2, D5 stored in the first area 101, As will be described later.
The page data D9 to D11 are stored in the buffer memory 201 and the data to be stored in the word line WL2, that is, the 3-page data D3, D7 and D11, Bit memory device 100 will be sequentially stored in the first area 101 of the multi-bit memory device 100. [ Step program operation for word line WL2, coarse program operation for word line WL1, and sophisticated program operation for word line WL0 are then performed on data stored in first area 101 Will be performed sequentially. The operation pattern to be performed when the data D9 to D11 is inputted will be repeatedly performed until the data D189 is stored in the buffer memory 201. [
The data to be stored in the word line WL62, that is, the 3-page data D183, D187 and D190, is stored in the buffer memory 201 of the memory controller 200, Bit memory device 100 in accordance with the control of the controller 100. The first area 101 of the multi- Thereafter, a one-step programming operation for the word line WL62, a coarse programming operation for the word line WL61, and a sophisticated programming operation for the word line WL60 are performed based on the data stored in the first area 101 Will be performed sequentially.
The data to be stored in the word line WL62, that is, the 3-page data D186, D189 and D191, is stored in the buffer memory 201 of the memory controller 200, Bit memory device 100 according to the first embodiment of the present invention. Then, a one-step program operation for the word line WL63, a coarse program operation for the word line WL62, a fine program operation for the word line WL61, a rough program operation for the word line WL63, A sophisticated program operation for the word line WL62 and a sophisticated program operation for the word line WL63 will be sequentially performed based on the data stored in the first area 101. [
Figure 21 is a diagram illustrating another exemplary address scrambling scheme of a multi-bit memory device in which 4-bit data per cell is stored and a reprogramming method is applied.
The address scrambling scheme shown in FIG. 21 will be applied to a multi-bit memory device that stores 4-bit data per cell. The data storage system to which the address scrambling scheme shown in FIG. 21 is applied will operate substantially the same as described above. For example, when the minimum program unit data for the first area 101 is stored in the buffer memory 201, the memory controller 200 stores the data stored in the buffer memory 201 in the first area 101 Bit memory device 100 to be programmed. Similarly, the memory controller 200 determines whether or not the data of the minimum program unit for the second area 102 is prepared in the first area 101, and performs a one-step program operation, a rough program operation And control the multi-bit memory device 100 to perform sophisticated program operations. Such operations will be performed according to the patterns shown in Table 1 based on the page address information.
Figures 22A-22D are diagrams illustrating various combinations of first and second regions of a multi-bit memory device in accordance with an exemplary embodiment of the present invention. In the figure, "BP" represents buffer programming for the first area 101 and "MP" represents main programming for the second area 102.
As described above, the multi-bit memory device 100 will include a first area 101 and a second area 102. Here, the first region 101 and the second region 102 will constitute a memory cell array of the multi-bit memory device 100. Although not shown in the figure, the memory cell array will include more areas (e.g., meta area, spare area, etc.). It will be appreciated that the regions of the memory cell array are logically separated rather than physically separated. This means that areas are defined according to the address mapping of the memory controller 200.
Referring to FIG. 22A, in the case of a multi-bit memory device that stores 3-bit data per cell, the first area 101 is composed of memory cells each storing 1-bit data, May comprise memory cells each storing 3-bit data. In this case, buffer programming will be done according to the SLC programming scheme. The main programming will be done according to the MLC programming method described above.
Referring to FIG. 22B, in the case of a multi-bit memory device for storing 4-bit data per cell, the first area 101 is composed of memory cells each storing 1-bit data, May comprise memory cells each storing 4-bit data. In this case, buffer programming will be done according to the SLC programming scheme. The main programming will be done according to the MLC programming method described above.
Referring to FIG. 22C, in the case of a multi-bit memory device storing 3-bit data per cell, the first region 101 is composed of memory cells each storing 2-bit data, May comprise memory cells each storing 3-bit data. In this case, the buffer programming will be done according to the general or MLC program method described above. The main programming will be performed according to the MLC programming method (for example, reprogramming method) described above.
Referring to FIG. 22D, in the case of a multi-bit memory device that stores 4-bit data per cell, the first area 101 is composed of memory cells each storing 2-bit data, May comprise memory cells each storing 4-bit data. In this case, the buffer programming will be done according to the general or MLC program method described above. The main programming will be performed according to the MLC programming method (for example, reprogramming method) described above.
It will be appreciated that, in the exemplary embodiment, the definitions of the first and second regions 101,102 shown in Figures 22A-22D are not limited to what is disclosed herein. For example, if the storage medium included in the data storage device is comprised of a plurality of multi-bit memory devices, the first and second areas 101 and 102 may be defined in each multi-bit memory device . As another example, the first area 101 may be defined only in any multi-bit memory device. Alternatively, any multi-bit memory device may be defined as the first area 101.
23 is a flowchart for explaining the operation of the memory controller according to an exemplary embodiment of the present invention. The operation of the memory controller according to an exemplary embodiment of the present invention will now be described in detail with reference to the drawings.
In step S200, the memory controller 200 will determine whether data has been input. If it is determined that no data is input, step S200 will be repeated. If it is determined that data is input, the procedure goes to step S210, and in step S210, the inputted data will be stored in the buffer memory 201. [ In step S220, the memory controller 200 will determine whether or not the buffer program operation is required. If buffer program operation is not required, the procedure will end.
If it is determined that the buffer program operation is required, the procedure will proceed to step S230. In step S230, data stored in the buffer memory 201, that is, data of the minimum program unit for the first area 101, will be transferred to the multi-bit memory device 100. [ This means that the data of the minimum program unit for the first area 101 is stored in the first area 101 of the multi-bit memory device 100. In step S240, the memory controller 200 will determine whether the main program operation is required (or whether the buffer program operation involves the main program operation). This will be done based on the page address information, as mentioned above.
If it is determined that the main program operation is not required, the procedure will be terminated. On the other hand, if it is determined that the main program operation is required, the procedure will proceed to step S250. In step S250, a program pattern related to the main program operation will be determined. The program pattern of the main program operation that follows the buffer program operation may consist of a one-step program operation, a coarse program operation, a series of coarse and fine program operations, and a series of coarse, fine, and sophisticated program operations . In step S260, the memory controller 200 will generate a series of instructions for main programming based on the determined program pattern. Such instructions may include a mode change command, an SLC read command, a dump command, a program verify command, and the like, as described in FIG. 16 and FIG. Thereafter, the procedure will end.
24 is a flowchart for explaining the operation of the memory controller according to another exemplary embodiment of the present invention. The operation of the memory controller according to an exemplary embodiment of the present invention will now be described in detail with reference to the drawings.
In step S300, the memory controller 200 will determine whether data has been input. If it is determined that no data is input, step S300 will be repeated. If it is determined that data is input, the procedure goes to step S310, and in step S310, the inputted data will be stored in the buffer memory 201. [ In step S320, the memory controller 200 will determine whether or not the buffer program operation is required. If buffer program operation is not required, the procedure will end.
If it is determined that the buffer program operation is required, in step S330, the memory controller 200 will determine whether the main program operation is required (or whether the buffer program operation involves the main program operation). This will be done based on the page address information, as mentioned above. If it is determined that the main program operation is not required, the procedure will proceed to step S340. In step S340, data stored in the buffer memory 201, that is, data of the minimum program unit for the first area 101, will be transferred to the multi-bit memory device 100. [ This means that the data of the minimum program unit for the first area 101 is stored in the first area 101 of the multi-bit memory device 100.
On the other hand, if the main program operation is determined to be required, the procedure will proceed to step S350. In step S350, a program pattern will be determined. The program pattern may be any one of the program patterns described in Table 1. It will be appreciated, however, that program patterns may change when interleaving is used. In step S360, the memory controller 200 will generate a series of instructions for buffer and main programming based on the determined program pattern. The instructions for buffer programming include SLC program instructions, and the instructions for the main program include a mode switch command, a SLC read command, a dump command, a program verify command, etc., as described in Figures 16 and 18 will be. Thereafter, the procedure will end.
In the exemplary embodiment, the data for buffer programming will be sent to the multi-bit memory device 100 following the SLC program instructions and prior to the instructions for the main program.
25 is a flowchart illustrating an operation of a memory controller according to another exemplary embodiment of the present invention. The operation of the memory controller according to an exemplary embodiment of the present invention will now be described in detail with reference to the drawings.
In step S400, the memory controller 200 will determine whether data has been input. If it is determined that no data is input, step S400 will be repeated. If it is determined that data is input, the procedure goes to step S410, and in step S410, the input data is stored in the buffer memory 201. [ In step S420, the memory controller 200 will determine a program pattern. The program pattern may be any one of the program patterns described in Table 1. It will be appreciated, however, that program patterns may change when interleaving is used. In step S430, the memory controller 200 will generate a series of commands for buffer programming and buffer programming and main programming based on the determined program pattern. The instructions for buffer programming include SLC program instructions, and the instructions for the main program include a mode switch command, a SLC read command, a dump command, a program verify command, etc., as described in Figures 16 and 18 will be. Thereafter, the procedure will end.
In the exemplary embodiment, the data for buffer programming will be sent to the multi-bit memory device 100 following the SLC program instructions and prior to the instructions for the main program. The program pattern may be determined to include or exclude instructions for buffer programming.
In an exemplary embodiment, an instruction (e.g., DAh in FIG. 16) to inform the SLC mode prior to performing the buffer program operation may be provided to the multi-bit memory device 100. Similarly, after the buffer program operation is performed, an instruction (e.g., DFh in FIG. 16) indicating the end of the SLC mode will be provided to the multi-bit memory device 100.
In the exemplary embodiment, the first and second regions 101 and 102 will be defined by the memory controller 200 prior to the operations described in Figures 23-25. After the definitions of the first and second areas 101 and 102 are made, the buffer program operation and the main program operation for the data provided from the host 300 will be performed according to the manner described above.
In an exemplary embodiment, the program pattern may be variously defined. For example, the program pattern can be defined separately for the buffer program operation and the main program operation. Alternatively, the program pattern may be defined for buffer and main program operations. The main program operation will include a series of program operations such as one-step program operation, coarse program operation, coarse and fine program operations, coarse, fine and sophisticated program operations, and the like.
26 is a diagram showing an example of configuring a memory cell array as memory blocks for an all-bit line memory structure or an odd-even memory structure. Exemplary structures of the memory cell array 110 included in the multi-bit memory device 100 shown in FIG. 2 will be described. As an example, a NAND flash memory device in which the memory cell array 110 is divided into 1024 memory blocks will be described. Data stored in each memory block can be erased simultaneously. In one embodiment, the memory block is the smallest unit of storage elements that are simultaneously erased. Each memory block has a plurality of columns each corresponding to, for example, bit lines (e.g., 1 KB of bit lines). In one embodiment, referred to as an all bit line (ABL) structure, all bit lines of a memory block may be selected simultaneously during read and program operations. The storage elements belonging to the common word line and connected to all the bit lines can be programmed simultaneously.
In the exemplary embodiment, a plurality of storage elements belonging to the same column are connected in series to form the NAND string 111. One terminal of the NAND string is connected to the corresponding bit line through the selection transistor controlled by the string selection line SSL and the other terminal is connected to the common source line CSL through the selection transistor controlled by the ground selection line GSL. .
In another exemplary embodiment, referred to as an odd-even architecture, the bit lines are divided into even bit lines BLe and odd bit lines BLo. In the odd / even bit line structure, storage elements connected to odd bit lines are programmed at a first time when belonging to a common word line, while storage elements connected to even bit lines belong to a second word Programmed in time. The data can be programmed into other blocks and read from other memory blocks. This operation can be performed simultaneously.
A flash memory device constituting a multi-bit memory device is a non-volatile memory device capable of retaining stored data even when power is turned off. With the increasing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, flash memory devices are more widely used as code storage as well as data storage. Flash memory devices can also be used in home applications such as HDTV, DVD, routers, and GPS.
Figure 27 is a block diagram that schematically illustrates a computing system in accordance with an exemplary embodiment of the present invention.
The computing system includes a microprocessor 2100, a user interface 2200, a modem 2300 such as a baseband chipset, a memory controller 2400, and a multi-bit memory device 2500 as a storage medium . The memory controller 2400 and the multi-bit memory device 2500 will be configured substantially the same as those shown in FIG. This means that it is possible to minimize the size of the buffer memory included in the memory controller 2400. Bit memory device 2500 will store N-bit data to be processed / processed by the microprocessor 2100 (N is an integer greater than or equal to 1) through the memory controller 2400. If the computing system is a mobile device, a battery 2600 for supplying the operating voltage of the computing system will additionally be provided. Although not shown in the drawings, it will be appreciated that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided in the computing system according to the present invention.
Figure 28 is a block diagram that schematically illustrates a memory controller in accordance with an exemplary embodiment of the present invention. Referring to Figure 28, a memory controller according to an exemplary embodiment of the present invention includes a first interface 3210, a second interface 3220, a processing unit 3230, a buffer 3240, an ECC unit 3250, and ROM 3260. < / RTI > The memory controller shown in Fig. 28 will be applied to the system shown in Fig. 2 or Fig.
The first interface 3210 may be configured to interface with the outside (or the host). The second interface 3220 may be configured to interface with the storage medium 3100 shown in FIG. 2 or FIG. The processing unit 3230 will be configured to control the overall operation of the controller 3200. For example, the CPU 3230 may be configured to operate firmware such as a Flash Translation Layer (FTL) stored in the ROM 3260. The buffer 3240 may be used to temporarily store data that is transmitted to the outside via the first interface 3210. [ The buffer 3240 may be used to temporarily store data transferred from the storage medium 3100 via the second interface 3220. [ The ECC unit 3250 will be configured to encode the data to be stored in the storage medium 3100 and to decrypt the data read from the storage medium 3100.
In an exemplary embodiment, the memory controller will be configured to generate instructions sequentially in accordance with the instruction sequence described in Figures 16 and 18. [ Alternatively, the memory controller may be configured to generate a set of instructions informing the program pattern described above.
29 is a block diagram schematically illustrating a semiconductor drive according to an exemplary embodiment of the present invention.
29, the semiconductor drive 4000 (SSD) will include a storage medium 4100 and a controller 4200. The storage medium 4100 may be coupled to the controller 4200 via a plurality of channels. A plurality of nonvolatile memories will be commonly connected to each channel. Each non-volatile memory will be composed of the memory described in Fig. The controller 4200 may be configured to control the storage medium 4100 according to any of the programming schemes described with reference to FIGS. This means that the size of the buffer memory included in the controller 4200 can be minimized.
FIG. 30 is a block diagram schematically showing the storage using the semiconductor drive shown in FIG. 29, and FIG. 31 is a block diagram schematically showing a storage server using the semiconductor drive shown in FIG.
A semiconductor drive 4000 in accordance with an exemplary embodiment of the present invention may be used to configure storage. As shown in FIG. 30, the storage will include a plurality of semiconductor drives configured substantially the same as those described in FIG. 29. A semiconductor drive 4000 in accordance with an exemplary embodiment of the present invention may be used to configure a storage server. As shown in FIG. 31, the storage server will include a plurality of semiconductor drives 4000 configured substantially the same as those described in FIG. 29, and a server 4000A. It will also be appreciated that RAID controller 4000B, well known in the art, may be provided to the storage server.
32 to 34 are diagrams schematically showing systems to which a data storage device according to exemplary embodiments of the present invention is applied.
When a semiconductor drive including a data storage device comprised of a memory controller and multi-bit memory devices according to exemplary embodiments of the present invention is applied to the storage, as shown in Figure 32, And / or a storage 6100 that communicates wirelessly with the host. When a semiconductor drive including a data storage device according to exemplary embodiments of the present invention is applied to a storage server, as shown in Figure 33, the system 7000 may be a storage server that communicates wired and / Lt; RTI ID = 0.0 > 7100 < / RTI > 34, the semiconductor drive including the data storage device according to the exemplary embodiment of the present invention may also be applied to the mail server 8100. [
35 is a block diagram schematically showing a memory card according to an embodiment of the present invention.
The memory card may be, for example, an MMC card, an SD card, a multiuse card, a micro SD card, a memory stick, a compact SD card, an ID card, a PCMCIA card, an SSD card, a chip card, ), A USB card, and the like.
35, the memory card includes an interface portion 9221 for performing an interface with the outside, a controller 9222 having a buffer memory and controlling the operation of the memory card, one or more nonvolatile memory devices 9207 ). The controller 9222, as a processor, can control the write operation and the read operation of the nonvolatile memory device 9207. [ Specifically, the controller 9222 is coupled to the nonvolatile memory device 9207 and the interface portion 9221 via a data bus (DATA) and an address bus (ADDRESS). The controller 9222 and the nonvolatile memory 9207 shown in FIG. 32 will correspond to the memory controller 200 and the multi-bit memory device 100 described in FIG. The controller 9222 will be configured to control the non-volatile memory 9207 according to any of the programming schemes described with reference to Figures 3-21. This means that the size of the buffer memory included in the controller 9222 can be minimized.
36 is a block diagram schematically showing a digital still camera according to an embodiment of the present invention.
36, a digital still camera includes a body 9301, a slot 9302, a lens 9303, a display portion 9308, a shutter button 9312, a strobe 9318, and the like. Particularly, a memory card 9331 can be inserted in the slot 9308, and the memory card 9331 will include the memory controller 200 and the multi-bit memory device 100 described in FIG. The memory controller included in the memory card 9331 will be configured to control the multi-bit memory device according to any of the programming schemes described with reference to Figures 3 to 21. [ This means that it is possible to minimize the size of the buffer memory included in the memory controller.
When the memory card 9331 is in the contact type, the memory card 9331 and the specific electric circuit on the circuit board are brought into electrical contact when the memory card 9331 is inserted into the slot 9308. [ If the memory card 9331 is a non-contact type, the memory card 9331 will be accessed via the wireless signal.
37 is an exemplary diagram illustrating various systems in which the memory card of Fig. 35 is used.
37, the memory card 9331 can be used as a video camera, a television, an audio device, a game device, an electronic music device, a mobile phone, a computer, a PDA (Personal Digital Assistant), a voice recorder, .
In an exemplary embodiment of the present invention, the memory cells may be comprised of variable resistance memory cells, and exemplary variable resistance memory cells and memory devices containing the same are disclosed in U.S. Patent No. 7529124, Will be included.
In another exemplary embodiment of the present invention, the memory cells may be implemented using one of various cell structures having a charge storage layer. The cell structure with the charge storage layer will include a charge trap flash structure using a charge trap layer, a stack flash structure in which the arrays are stacked in multiple layers, a flash structure without a source-drain, a pin-type flash structure, and the like.
A memory device having a charge trap flash structure as the charge storage layer is disclosed in U.S. Patent No. 6858906, U.S. Patent Publication No. 2004-0169238, and U.S. Patent Publication No. 2006-0180851, each of which is incorporated herein by reference . A flash structure without a source / drain is disclosed in Korean Patent No. 673020, which will be incorporated by reference in this application.
The flash memory device and / or memory controller according to the present invention may be implemented using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention can be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Wafer-Level Processed Stack Package (WSP), and the like.
It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

100: Multi-bit memory device
200: memory controller
300: Host

Claims (23)

A nonvolatile memory device having a memory cell array; And a memory controller having a buffer memory and controlling the non-volatile memory device, the method comprising:
Storing the input data in the buffer memory according to an external request;
Determining whether data stored in the buffer memory is data accompanying a buffer program operation for the memory cell array;
Determining whether a main program operation for the memory cell array is required when the data stored in the buffer memory is data accompanied by a buffer program operation;
Determining a pattern of a main program operation for the memory cell array when a main program operation for the memory cell array is required; And
And outputting to the nonvolatile memory device a series of instructions for a main program operation for the memory cell array based on the determined pattern,
The memory cell array is defined as first and second areas, the first area is programmed through the buffer program operation, the second area is programmed through the main program operation,
The non-volatile memory device comprising page buffers, each of the page buffers having a plurality of latches, one of the latches being used to store data to be stored in or read from the first area Wherein the data stored in the one latch is dumped to a selected one of the remaining ones of the latches during a program operation for the second region,
Wherein determining the pattern of the main program operation comprises determining at least one program to be executed among the one-step program, the coarse program and the sophisticated program during the main program operation. delete The method according to claim 1,
Wherein the pattern for the main program operation is determined based on address information of data accompanying the buffer program operation. The method of claim 3,
Wherein the main program operation includes at least one of a one-step program operation, a coarse program operation, and a sophisticated program operation. 5. The method of claim 4,
Wherein the series of instructions output to the non-volatile memory device when the main program operation is requested includes a single-bit read instruction for the first area, a dump instruction, and a multi-bit program instruction for the second area Wherein the data storage device is a data storage device. The method according to claim 1,
Wherein the first area is programmed via a single-bit program operation and the second area is programmed through a multi-bit program operation. delete The method according to claim 1,
Wherein the data for the buffer program operation is transferred to the first area before determining whether the main program operation is required. A nonvolatile memory device having a memory cell array; And a memory controller having a buffer memory and controlling the non-volatile memory device, the method comprising:
Storing the input data in the buffer memory according to an external request;
Determining whether data stored in the buffer memory is data accompanying a buffer program operation for the memory cell array;
Determining whether a main program operation for the memory cell array is required when the data stored in the buffer memory is data accompanied by a buffer program operation;
Determining a pattern of a main program operation for the memory cell array when a main program operation for the memory cell array is required; And
And outputting to the nonvolatile memory device a series of instructions for a main program operation for the memory cell array based on the determined pattern,
The memory cell array is defined as first and second areas, the first area is programmed through the buffer program operation, the second area is programmed through the main program operation,
Wherein data for the buffer program operation is transferred to the first area while a series of instructions for the main program operation are output to the nonvolatile memory device based on the determined pattern,
Wherein determining the pattern of the main program operation comprises determining at least one program to be executed among the one-step program, the coarse program and the sophisticated program during the main program operation. delete A nonvolatile memory device including a memory cell array having a first region and a second region; And
A memory controller having a buffer memory and configured to control the non-volatile memory device,
Wherein the memory controller controls the nonvolatile memory device so that data stored in the buffer memory is stored in the first area when data of a minimum program unit for the first area is stored in the buffer memory,
If it is determined that data of the minimum program unit for the second area is collected in the first area, the nonvolatile memory device reads at least a part of the data of the minimum program unit from the first area, Storing the data of the minimum program unit in the second area by repeating the program operation in the second area more than once,
Wherein the nonvolatile memory device stores the first data and the second data in the first area under the control of the memory controller and reads the first data from the first area to perform one program operation in the second area And reads the first data and the second data from the first area to perform another one of the program operations in the second area. delete delete delete 12. The method of claim 11,
Wherein the minimum program unit for the first area comprises one page and the minimum program unit for the second area comprises one or more pages according to the number of bits per cell. 12. The method of claim 11,
Wherein the second area is programmed according to a reprogramming scheme including a one-step program operation, a coarse program operation, and a sophisticated program operation. 17. The method of claim 16,
And upon a read request, the memory controller is configured to determine whether the read-requested data is associated with a word line for which the sophisticated program operation has been completed. 18. The method of claim 17,
Wherein if the read-requested data is determined to be associated with a word line for which the sophisticated program operation has been completed, the memory controller controls the non-volatile memory device to control the non-volatile memory device such that the read- . 18. The method of claim 17,
Wherein if the read-requested data is determined to be associated with a word line for which the sophisticated program operation is not completed, the memory controller is configured to determine whether the read-requested data is to be read from the first area, Storage system. 12. The method of claim 11,
Wherein the first data and the second data are stored in different memory cells in the first region and in the same memory cells in the second region. 12. The method of claim 11,
Wherein the memory controller determines a pattern of program operation when storing the first data and the second data in the second area,
Determining a pattern of the program operation comprises determining at least one program to be executed among a one-step program, a glide program, and a sophisticated program. 22. The method of claim 21,
Wherein the memory controller determines a pattern of the program operation based on at least one of an address scramble scheme and a number of bits per cell of the second area. delete

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