KR101769072B1 - High efficiency light emitting diode and method of fabricating the same - Google Patents

Abstract

A high-efficiency light emitting diode and a method for manufacturing the same are disclosed. The light emitting diode includes: a support substrate; A semiconductor laminated structure disposed on the supporting substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; A protective layer disposed between the supporting substrate and the semiconductor laminated structure and having at least one groove exposing the semiconductor laminated structure; The semiconductor layered structure being located between the protective layer and the support substrate and being filled with at least one groove so as to make an ohmic contact with the semiconductor layered structure with the edge between the protective layer and the support substrate and between the edge of the semiconductor stacked structure and the edge of the support substrate Reflective metal layer; And a barrier metal layer located between the support substrate and the reflective metal layer and surrounding the reflective metal layer to surround the reflective metal layer. This prevents the reflective metal layer from being exposed to the outside, and can prevent the crack from affecting the electrical characteristics and reliability of the light emitting diode even if cracks are generated in the barrier metal layer near the edge of the reflective metal layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a high efficiency light emitting diode and a method of manufacturing the same. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a light emitting diode and a method for manufacturing the same, and more particularly, to a gallium nitride-based high efficiency light emitting diode in which a growth substrate is removed by a substrate separation process and a method for manufacturing the same.

Generally, nitrides of Group III elements such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct bandgap energy band structure. Therefore, recently, It is attracting much attention as a material. In particular, blue and green light emitting devices using indium gallium nitride (InGaN) are utilized in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high density light sources, high resolution output systems and optical communication.

Such a nitride semiconductor layer of a group III element is difficult to fabricate a substrate of the same kind capable of growing the same, and it is difficult to fabricate a nitride semiconductor layer of a Group III element by using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) ≪ / RTI > A sapphire substrate having a hexagonal system structure is mainly used as a heterogeneous substrate. However, since sapphire is electrically nonconductive, it limits the light emitting diode structure. Recently, epitaxial layers such as a nitride semiconductor layer are grown on a heterogeneous substrate such as sapphire, a supporting substrate is bonded to the epitaxial layers, and then a heterogeneous substrate is separated using a laser lift- A technique for manufacturing a high-efficiency light emitting diode having a structure is being developed.

In general, a vertical-structured light-emitting diode is superior in current dispersion performance due to the structure in which the p-side is located below the light-emitting diode of the conventional horizontal-type structure, and adopts a support substrate having a higher thermal conductivity than sapphire Excellent heat dissipation performance. Furthermore, by arranging a reflective metal layer between the support substrate and the p-type semiconductor layer to reflect light directed toward the support substrate, the light extraction efficiency can be improved.

On the other hand, silver (Ag) is generally used as the reflective metal layer. However, when silver (Ag) easily migrates and is exposed to the outside, its electrical characteristics are easily deformed because it is easily deteriorated by oxidation. Furthermore, during the etching of the epilayers to pattern the epilayers in individual chip units, when silver is exposed, the etch by-products adhere to the sidewalls of the epilayers to cause an electrical short between the p-type semiconductor layer and the n- . Accordingly, a technique of covering the reflective metal layer with a barrier metal layer to prevent movement of silver atoms is generally used, and further, a technique of covering the edge of the reflective metal layer with the barrier metal layer or the insulating layer to prevent the reflective metal layer from being exposed to the outside (See, for example, U.S. Patent No. 6,744,071). The barrier metal layer and / or the insulating layer covers the edge of the reflective metal layer to prevent the reflective metal layer from being exposed to the outside.

According to the related art, the reflective metal layer can be prevented from being exposed to the outside by covering the reflective metal layer with the barrier metal layer or the insulating layer and the barrier metal layer, and further, the movement of the atoms can be prevented to maintain the electrical characteristics of the reflective metal layer.

However, in the prior art in which the edges of the reflective metal layer are covered with the barrier metal layer or the insulating layer, stress is concentrated on the insulating layer or the barrier metal layer near the edge of the reflective metal layer, and cracks are likely to occur.

1 is a SEM cross-sectional photograph showing an edge portion of a reflective metal layer in a vertical type light emitting diode manufactured according to a conventional technique.

1, a reflective metal layer 11 is formed on a p-type semiconductor layer 9, and an edge of the reflective metal layer 11 is covered with an insulating layer 13. The insulating layer 13 is patterned to have grooves (not shown) for exposing the reflective metal layer 11. A barrier metal layer 15 is formed on the insulating layer 13 and the reflective metal layer 11 exposed by the groove. Next, a bonding metal 17 is formed on the barrier metal layer 15, and a supporting substrate (not shown) is attached thereon via a bonding metal 17. The reflective metal layer 11 comprises silver (Ag), the insulating layer 13 is generally formed of SiO 2 and the barrier metal layer 15 is formed of a repeated layer of Pt, Ni, Ti or W, do.

A crack is generated in the insulating layer 13 and the barrier metal layer 15 near the edge of the reflective metal layer 11, as shown in Fig. It has been confirmed that such a crack occurs even when the insulating layer 13 is not used, that is, when the barrier metal layer 15 is directly formed on the reflective metal layer 11. [ The cracks are formed to be wide in the vicinity of the reflective metal layer 11 and decrease in width away from the reflective metal layer 11, and extend over almost the entire thickness of the barrier metal layer.

This crack is expected to occur because the coefficient of thermal expansion of the reflective metal layer 11 is relatively large compared to the thermal expansion coefficient of the insulating layer 13 and the barrier metal layer 15. [ That is, when the thermal process is performed, since the reflective metal layer 11 expands relatively more than the insulating layer 13 and the barrier metal layer 15, stress is concentrated on the edge of the reflective metal layer 11, It is judged that cracks are generated in the insulating layer 13 close to the reflective metal layer 11 and transferred to the barrier metal layer 15.

The electrical characteristics of the reflective metal layer are deformed near the edges of the reflective metal layer 11 due to the occurrence of the cracks and problems such as interface delamination between the reflective metal layer 11 and the p- The ohmic characteristics of the metal layer deteriorate. Further, since the crack is generated on the surface of the p-type semiconductor layer 9, the reliability of the light emitting diode is expected to deteriorate.

Therefore, a problem to be solved by the present invention is to provide a light emitting device capable of preventing the reflective metal layer 11 from being exposed to the outside, and preventing deterioration of electrical characteristics and reliability due to cracks generated near the edge of the reflective metal layer 11 Diode.

Furthermore, another object to be solved by the present invention is to provide a high efficiency light emitting diode which improves current dispersion performance and / or light extraction efficiency.

The present invention provides a high-efficiency light emitting diode and a method of manufacturing the same. According to one aspect of the present invention, there is provided a light emitting diode comprising: a support substrate; A semiconductor laminated structure disposed on the supporting substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; A protective layer disposed between the supporting substrate and the semiconductor laminated structure and having at least one groove exposing the semiconductor laminated structure; Wherein the semiconductor layered structure is formed on the semiconductor layered structure and the semiconductor layered structure is formed on the semiconductor layered structure, A reflective metal layer positioned between the edges of the support substrate; And a barrier metal layer disposed between the supporting substrate and the reflective metal layer and surrounding the reflective metal layer to surround the reflective metal layer.

According to embodiments of the present invention, the reflective metal layer is embedded in the light emitting diode by the protective layer, the barrier metal layer, and the semiconductor laminated structure, and is therefore not exposed to the outside. Further, since the edge of the reflective metal layer is located below the protective layer, even if a crack occurs in the barrier metal layer near the edge of the reflective metal layer, it is possible to prevent the crack from affecting the electrical characteristics and reliability of the light emitting diode. Further, by allowing the edge of the reflective metal layer to be located outside the semiconductor laminated structure, it is possible to prevent the deterioration of the ohmic characteristics of the reflective metal layer even if the characteristic of the reflective metal layer is deformed by the crack, It is possible to block the influence on the laminated structure.

The protective layer may be a metal layer that is a Schottky contact with the semiconductor laminate structure, for example, the p-type semiconductor layer, or may be a multiple insulating layer such as a single insulating layer such as SiO2 or a distributed Bragg reflector. In order to prevent short-circuiting by metal etching by-products in the manufacturing process, it is more preferable that the protective layer is an insulating layer.

The light emitting diode may include: a first electrode pad positioned on the semiconductor laminated structure; An electrode extension extending from the first electrode pad; And an upper insulating layer interposed between the first electrode pad and the semiconductor laminated structure.

By arranging the upper insulating layer between the first electrode pad and the semiconductor laminated structure, it is possible to prevent current from concentrating and flowing from the first electrode pad directly to the semiconductor laminated structure.

Furthermore, the protective layer may have a plurality of grooves, and the first electrode pad and the electrode extension may be located above the protective layer region. Therefore, it is possible to further prevent the current from concentrating in the vertical direction from the first electrode pad and the electrode extension.

In some embodiments, the light emitting diode includes a plurality of first electrode pads; And a plurality of electrode extensions extending from the plurality of first electrode pads. The plurality of first electrode pads and electrode extensions may be located above the protective layer region.

On the other hand, the semiconductor laminated structure may include a roughened surface, and the upper insulating layer may cover the roughened surface. Furthermore, the upper insulating layer may form an uneven surface along the roughened surface. As the upper insulating layer forms the uneven surface, the total internal reflection generated on the upper surface of the upper insulating layer can be reduced, and thus the light extraction efficiency can be further improved.

In addition, the semiconductor laminated structure may include a flat surface, and the first electrode pad and the electrode extension may be located on the flat surface. Further, the electrode extension portion may contact the flat surface of the semiconductor laminated structure. In addition, the roughened surface may be located below the electrode extension.

The supporting substrate may be a conductive substrate, for example, a metal substrate or a semiconductor substrate.

The supporting substrate may be formed by plating or the like, or may be bonded using a bonding metal.

According to another aspect of the present invention, a method of manufacturing a light emitting diode is provided. This method comprises: forming a semiconductor laminated structure including an n-type compound semiconductor layer, an active layer and a p-type compound semiconductor layer on a growth substrate; Forming a protective layer on the semiconductor laminated structure, wherein the protective layer has at least one groove exposing an upper surface of the semiconductor laminated structure; Forming a reflective metal layer on the protective layer, the reflective metal layer having an edge on the protective layer in addition to filling the groove; Forming a barrier metal layer covering the reflective metal layer, the barrier metal layer covering the edge of the reflective metal layer and surrounding the reflective metal layer; Attaching a support substrate on the barrier metal layer; Removing the growth substrate to expose the semiconductor stacked structure; And exposing the protective layer by patterning the semiconductor laminated structure. Here, the edge of the reflective metal layer is located below the exposed region of the protective layer.

Thus, the reflective metal layer can be prevented from being exposed to the outside, and the electrical characteristics and reliability of the light emitting diode can be prevented from being deteriorated even if cracks are generated in the barrier metal layer at the edge of the reflective metal layer.

The method includes forming a mask pattern on the exposed semiconductor laminated structure and forming a roughened surface together with the flat surface by anisotropically etching the upper surface of the semiconductor laminated structure using the mask pattern as an etching mask Quot;

Further, the method may further comprise: forming an upper insulating layer covering the surface of the patterned semiconductor laminated structure, the upper insulating layer having an opening exposing a part of the flat surface, And forming an electrode extension extending from the first electrode pad. At this time, the electrode extension part is formed in the opening of the upper insulating layer.

In addition, the protective layer may have a plurality of grooves, and the first electrode pad and the electrode extension may be located above the protective layer region.

Meanwhile, the upper insulating layer may have an uneven surface formed along the rough surface.

The method may further include dividing the support substrate into individual light emitting diodes, wherein the reflective metal layer is located within an edge region of the divided support substrate.

According to the present invention, even when cracks are generated in the barrier metal layer near the edges of the reflective metal layer while preventing the reflective metal layer from being exposed to the outside, it is possible to prevent the electrical characteristics and reliability of the LED from being affected by such cracks. Also, a light emitting diode having improved current dispersion performance can be provided by interposing an upper insulating layer between the first electrode pad and the semiconductor laminated structure. The upper insulating layer is formed to have an uneven surface along the rough surface of the semiconductor laminated structure The light extraction efficiency of the light emitting diode can be improved.

1 is a SEM cross-sectional photograph showing an edge portion of a reflective metal layer in a vertical type light emitting diode manufactured according to a conventional technique.
2 is a schematic layout view illustrating a light emitting diode according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along the cutting line AA of FIG. 2 to illustrate a light emitting diode according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view taken along a perforation line BB of FIG. 2 to illustrate a light emitting diode according to an embodiment of the present invention.
5 is a cross-sectional view taken along line CC of FIG. 2 to illustrate a light emitting diode according to an embodiment of the present invention.
6 to 10 are cross-sectional views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention, which are sectional views corresponding to the perforated line AA in FIG. 2, respectively.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the same reference numerals denote the same elements, and the width, length, thickness, and the like of the elements may be exaggerated for convenience.

2 is a schematic layout view for explaining a light emitting diode according to an embodiment of the present invention, and FIGS. 3 to 5 are sectional views taken along the perforated lines A-A, B-B, and C-C of FIG. 2, respectively. In Fig. 2, the groove 31a and the reflective metal layer 33 in the protective layer 31 located under the semiconductor laminated structure 30 are indicated by dotted lines.

2 to 5, the light emitting diode includes a support substrate 41, a semiconductor laminated structure 30, a protective layer 31, a reflective metal layer 33, and a barrier metal layer 35. The light emitting diode may further include a bonding metal 43, an upper insulating layer 47, an n-electrode pad 51, and an electrode extension portion 51a.

The support substrate 41 is a secondary substrate separated from the growth substrate for growing the compound semiconductor layers and attached to the already grown compound semiconductor layers. The support substrate 41 may be a conductive substrate such as a metal substrate or a semiconductor substrate, but is not limited thereto, and may be an insulating substrate such as sapphire.

The semiconductor laminated structure 30 is located on the supporting substrate 41 and includes a p-type compound semiconductor layer 29, an active layer 27, and an n-type compound semiconductor layer 25. Here, the p-type compound semiconductor layer 29 is located closer to the support substrate 41 than the n-type compound semiconductor layer 25, similar to a general vertical light emitting diode. The semiconductor laminated structure 30 is located on a partial area of the supporting substrate 41. That is, the supporting substrate 41 has a relatively large area as compared with the semiconductor laminated structure 30, and the semiconductor laminated structure 30 is located in a region surrounded by the edge of the supporting substrate 41.

The n-type compound semiconductor layer 25, the active layer 27 and the p-type compound semiconductor layer 29 may be formed of a III-N compound semiconductor such as (Al, Ga, In) N semiconductor. The n-type compound semiconductor layer 25 and the p-type compound semiconductor layer 29 may each be a single layer or a multi-layer. For example, the n-type compound semiconductor layer 25 and / or the p-type compound semiconductor layer 29 may include a contact layer and a cladding layer, and may also include a superlattice layer. In addition, the active layer 27 may be a single quantum well structure or a multiple quantum well structure. It is easy to form a roughened surface R on the upper surface of the n-type compound semiconductor layer 25 by positioning the n-type compound semiconductor layer 25 having a relatively small resistance on the opposite side of the support substrate 41, The true surface R improves the extraction efficiency of the light generated in the active layer 27.

The protective layer 31 is located between the semiconductor laminated structure 30 and the supporting substrate 41 and has grooves 31a for exposing the semiconductor laminated structure 30 such as the p-type compound semiconductor layer 29. The protective layer 31 may have a plurality of grooves 31a exposing the semiconductor laminated structure 30. [ The protective layer 31 extends outside the semiconductor laminated structure 30 and is located below the side surface of the semiconductor laminated structure 30 so that the upper surface of the reflective metal layer 33 is located on the side of the semiconductor laminated structure 30 Thereby preventing exposure.

The protective layer 31 may be a single layer or a multilayer of a silicon oxide film or a silicon nitride film or may be a distributed Bragg reflector in which a plurality of insulating layers having different refractive indices such as SiO2 / TiO2 or SiO2 / Nb2O5 are repeatedly laminated. Alternatively, the protective layer 31 may be a metal layer such as Ti which is Schottky contact with the semiconductor laminated structure 30, for example, the p-type compound semiconductor layer 29.

The reflective metal layer 33 is located between the passivation layer 31 and the support substrate 41 and fills the grooves 31a of the passivation layer 31 to form the semiconductor laminated structure 30 such as the p- ). The reflective metal layer 33 may comprise a reflective layer such as Ag. The edge (33a) or side of the reflective metal layer (33) is located under the protective layer (31). That is, the edge of the reflective metal layer 33 is located between the protective layer 31 and the support substrate 41. Further, the edge 33a of the reflective metal layer 33 may be positioned between the edge of the semiconductor laminated structure 30 and the edge of the support substrate 41, as shown in Fig. That is, the semiconductor laminated structure 30 is confinedly positioned in the upper region of the region surrounded by the edge 33a of the reflective metal layer 33.

The barrier metal layer 35 is located between the reflective metal layer 33 and the supporting substrate 41 and surrounds the reflective metal layer 33 by covering the edge 33a of the reflective metal layer 33. That is, the side surface and the lower surface of the reflective metal layer 33 are covered with the barrier metal layer 35. The barrier metal layer 35 prevents the movement of a metallic material such as Ag of the reflective metal layer 33 and prevents the side of the reflective metal layer 33 from being exposed to the outside. The barrier metal layer 35 may include, for example, Pt, Ni, Ti, W, or an alloy thereof, and may be located on the front surface of the support substrate 41.

On the other hand, the supporting substrate 41 may be bonded onto the barrier metal layer 35 through the bonding metal 43. The bonding metal 43 may be formed, for example, by Au-Sn using eutectic bonding. Alternatively, the support substrate 41 may be formed on the barrier metal layer 35 using, for example, a plating technique. When the supporting substrate 41 is a conductive substrate, it can function as a p-electrode pad. Alternatively, when the supporting substrate 41 is an insulating substrate, a p-electrode pad may be formed on the barrier metal layer 35 located on the supporting substrate 41.

On the other hand, the upper surface of the semiconductor laminated structure 30, that is, the surface of the n-type compound semiconductor layer 25 may include a roughened surface R and a flat surface. As shown in Figs. 3 to 5, the n-electrode pad 51 and the electrode extension portion 51a may be located on a flat surface. As shown in the figure, the n-electrode pad 51 and the electrode extension portion 51a are located on a flat surface and may have a width narrower than the width of the flat surface. Therefore, it is possible to prevent the electrode pad or the electrode extension portion from being peeled off by occurrence of undercut or the like in the semiconductor laminated structure 30, and reliability can be improved. On the other hand, the roughened surface R may be located below the flat surface. That is, below the roughened surface (R) electrode pad 51 and the electrode extension portion 51a.

The n-electrode pad 51 is located on the semiconductor laminated structure 30, and the electrode extension portion 51a extends from the n-electrode pad 51. A plurality of n-electrode pads 51 may be positioned on the semiconductor laminated structure 30 and the electrode extensions 51a may extend from the n-electrode pads 51, respectively. The electrode extensions 51a are electrically connected to the semiconductor laminated structure 30 and can directly contact the n-type compound semiconductor layer 25. [

The n-electrode pad 51 may also be located above the protective layer 31 region. That is, immediately below the n-electrode pad 51, the reflective metal layer 33 does not make an ohmic contact with the p-type compound semiconductor layer 29, and instead, the protective layer 31 is located. Further, the electrode extension part 51a may also be located above the region of the protective layer 31. [ Accordingly, it is possible to prevent the current intensively flowing immediately below the electrode extension portion 51a.

On the other hand, an upper insulating layer 47 is interposed between the n-electrode pad 51 and the semiconductor laminated structure 30. The upper insulating layer 47 prevents the current from flowing directly from the n-electrode pad 51 to the semiconductor laminated structure 30, and particularly prevents the current from being concentrated directly below the n-electrode pad 51 . Further, the upper insulating layer 47 covers the rough surface R. At this time, the upper insulating layer 47 may have an uneven surface formed along the rough surface R. The irregular surface of the upper insulating layer 47 may have a convex shape. The total internal reflection generated on the upper surface of the upper insulating layer 47 can be reduced by the uneven surface of the upper insulating layer 47.

The upper insulating layer 47 may also cover the side surface of the semiconductor laminated structure 30 to protect the semiconductor laminated structure 30 from the external environment. Further, the upper insulating layer 47 may have an opening for exposing the semiconductor laminated structure 30, and the electrode extending portion 51a may be positioned within the opening to contact the semiconductor laminated structure 30.

6 to 10 are cross-sectional views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention. Here, the sectional views correspond to the sectional views taken along the perforated line A-A in Fig. 2, respectively.

6, a semiconductor laminated structure 30 including an n-type semiconductor layer 25, an active layer 27, and a p-type semiconductor layer 29 is formed on a growth substrate 21. The growth substrate 21 may be a sapphire substrate, but is not limited thereto, and may be a different substrate such as a silicon substrate. The n-type and p-type semiconductor layers 25 and 29 may be formed as a single layer or a multi-layer, respectively. In addition, the active layer 27 may be formed of a single quantum well structure or a multiple quantum well structure.

The compound semiconductor layers may be formed of a III-N compound semiconductor and may be grown on a growth substrate 21 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) .

On the other hand, a buffer layer (not shown) may be formed before forming the compound semiconductor layers. The buffer layer is employed to alleviate the lattice mismatch between the sacrificial substrate 21 and the compound semiconductor layers, and may be a layer of a gallium nitride based material such as gallium nitride or aluminum nitride.

Referring to FIG. 7, a protective layer 31 is formed on the semiconductor laminated structure 30. The protective layer 31 has a groove (see 31a in Fig. 1) for exposing the semiconductor laminated structure 30. The protective layer 31 may be formed of a silicon oxide film or a silicon nitride film, or may be formed of a distributed Bragg reflector by repeatedly laminating insulating layers having different refractive indices. Alternatively, the passivation layer 31 may be formed of a metal layer for Schottky contact with the semiconductor laminated structure 30, for example, the p-type compound semiconductor layer 29.

A reflective metal layer 33 is formed on the protective layer 31. The reflective metal layer 33 covers the protective layer 31 and fills the grooves in the protective layer 31 to make an ohmic contact with the semiconductor laminated structure 30. The reflective metal layer 33 includes a reflective metal such as silver (Ag). On the other hand, the edge of the reflective metal layer 33 is located on the protective layer 31. The reflective metal layer 33 may be formed in a continuous plate shape for each individual light emitting diode region.

Then, a barrier metal layer 35 is formed on the reflective metal layer 33. The barrier metal layer 35 covers the upper surface of the reflective metal layer 33 and also surrounds the edge 33a of the reflective metal layer 33.

Referring to FIG. 8, a supporting substrate 41 is attached on the barrier metal layer 35. The supporting substrate 41 may be manufactured separately from the semiconductor laminated structure 30 and then bonded onto the barrier metal layer 35 through the bonding metal 43. [ Alternatively, the support substrate 41 may be formed by plating on the barrier metal layer 35.

Thereafter, the growth substrate 21 is removed and the surface of the n-type semiconductor layer 25 of the semiconductor laminated structure 30 is exposed. The growth substrate 21 may be removed using a laser lift-off (LLO) technique.

Referring to FIG. 9, a mask pattern 45 is formed on the exposed n-type semiconductor layer 25. The mask pattern 45 covers the region of the n-type semiconductor layer 25 corresponding to the groove of the reflective metal layer 33 and exposes the other region. In particular, the mask pattern 45 covers an area where the n-electrode pad and the electrode extension are to be formed. The mask pattern 45 may be formed of a polymer such as a photoresist.

Subsequently, the surface of the n-type semiconductor layer 25 is anisotropically etched using the mask as an etching mask to form a rough surface R on the n-type semiconductor layer 25. Then, Thereafter, the mask 45 is removed. The surface of the n-type semiconductor layer 25 where the mask 45 is located maintains a flat surface.

On the other hand, a chip division region is formed by patterning the semiconductor laminated structure 30, and the protective layer 31 is exposed. The chip region may be formed before or after the roughened surface R is formed. The edge of the reflective metal layer 33 is located under the protective layer 31 exposed in the chip region. Therefore, the reflective metal layer 33 is prevented from being exposed to the outside by the protective layer 31.

Referring to FIG. 10, an upper insulating layer 47 is formed on the n-type semiconductor layer 25 on which the roughened surface R is formed. The upper insulating layer 47 is formed along the roughened surface R and has an uneven surface corresponding to the roughened surface R. [ In addition, the upper insulating layer 51 covers a flat surface on which the n-electrode pad 51 is to be formed. The upper insulating layer 47 may also cover the side surface of the semiconductor laminated structure 30 exposed in the chip region. However, the upper insulating layer 47 has an opening 47a exposing the flat surface of the region where the electrode extension 51a is to be formed.

Next, an n-electrode pad 51 is formed on the upper insulating layer 47, and an electrode extension is formed in the opening 47a. The electrode extension extends from the n-electrode pad 51 and is electrically connected to the semiconductor laminated structure 30.

Thereafter, the supporting substrate 41 is divided along the chip dividing regions to separate the individual light emitting diode chips, thereby completing the light emitting diodes (see FIG. 3). At this time, the protective layer 31, the barrier metal layer 35, and the supporting substrate 41 may be divided together, and thus the side surfaces thereof may be parallel to each other. On the other hand, the reflective metal layer is located in the region surrounded by the edges of the divided support substrate, so that the reflective metal layer 33 is embedded in the light emitting diode without being exposed to the outside.

Claims (10)

A support substrate;
A semiconductor laminated structure located on the supporting substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer, and located on a partial region of the supporting substrate;
A protective layer which is located along the edge of the semiconductor laminated structure between the supporting substrate and the semiconductor laminated structure and protects the semiconductor laminated structure and the supporting substrate;
A barrier metal layer disposed between the protective layer and the support substrate and covering the entire surface of the protective layer;
A reflective layer that is covered by the barrier metal layer and that is part of the first surface facing the semiconductor layer is located in a region surrounded by the protective layer, the second surface opposite to the first surface and the side surface is surrounded by the barrier metal layer;
A first electrode pad located on the semiconductor laminated structure;
An electrode extension extending from the first electrode pad; And
And an upper insulating layer covering the semiconductor multilayer structure,
Wherein the semiconductor laminated structure includes a roughened surface and a flat surface,
Wherein the upper insulating layer covers the roughened surface,
Wherein the upper insulating layer forms an uneven surface along the roughened surface,
Wherein the electrode extension is located on a flat surface of the semiconductor laminated structure,
The lower surface of the electrode extension portion is in contact with the flat surface of the semiconductor laminated structure,
Wherein the electrode extension portion has a width narrower than a width of a flat surface of the semiconductor laminated structure. The method according to claim 1,
And another region on the support substrate other than the partial region is covered with the protective layer. The method of claim 2,
Wherein the barrier metal layer is formed to be curved due to the shape of the protective layer. The method of claim 3,
Further comprising a protective layer located on a lower surface of the semiconductor multilayer structure opposite to the first electrode pad,
Wherein the first electrode pad is located on top of the semiconductor laminated structure and is in electrical contact with the semiconductor laminated structure. The method of claim 4,
Wherein a side surface and an upper surface of a surface of the protective layer located on a lower surface of the semiconductor laminated structure opposite to the first electrode pad except a surface in contact with the semiconductor laminated structure are surrounded by the reflective layer. The method of claim 5,
Wherein the semiconductor laminated structure includes a roughened surface in a region other than an upper surface portion where the first electrode pad and the electrode extension portion are located. The method according to claim 1,
And the upper insulating layer is sandwiched between the first electrode pad and the semiconductor laminated structure. delete The method according to claim 1,
Wherein the supporting substrate is a conductive substrate. The method according to claim 1,
And a bonding metal interposed between the supporting substrate and the barrier metal layer.

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