KR101715226B1 - Liquid crystal display device and Method of fabricating the same - Google Patents

Abstract

The gate insulating film and the protective layer are positioned between the common electrode and the data line so that the thickness of the insulating layer located between the common electrode and the data line is maximized and the thickness of the insulating layer located between the common electrode and the pixel electrode is The crosstalk problem can be solved without increasing the driving voltage.

Thus, it is possible to provide a high-quality image without increasing the driving voltage.

Further, since an additional mask process is not required, an array substrate for a liquid crystal display device capable of providing a high-quality image without increasing the manufacturing cost is provided.

Liquid crystal display, fringe field, crosstalk

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an array substrate for a fringe field switching mode liquid crystal display device and a manufacturing method thereof.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, It is attracting attention.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio.

However, liquid crystal driving by an electric field that is applied up and down has a drawback that the viewing angle characteristic is not excellent.

Therefore, a transverse electric field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in the figure, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other and face each other. A liquid crystal layer 11 is interposed between the upper and lower substrates 9, .

The common electrode 17 and the pixel electrode 30 are formed on the same plane on the lower substrate 10 and the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30 And is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views respectively showing operations of an on-state and an off-state of a general transverse electric field type liquid crystal display device.

2A, the change of the liquid crystal 11a at the position corresponding to the common electrode 17 and the pixel electrode 30 is expressed by the following equation The liquid crystal 11b located between the common electrode 17 and the pixel electrode 30 is formed by a horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, And arranged in the same direction as the horizontal electric field L. That is, since the liquid crystal is moved by the horizontal electric field in the transverse electric field type liquid crystal display device, the viewing angle becomes wide.

Next, referring to FIG. 2B, a horizontal electric field is not formed between the common electrode and the pixel electrode since the liquid crystal display device is in an off state in which no voltage is applied, so that the alignment state of the liquid crystal layer 11 is not changed.

In addition to the advantages of the transverse electric field type liquid crystal display device having a wide viewing angle, a fringe field switching mode liquid crystal display device which can simultaneously use a horizontal electric field and a vertical electric field has been proposed.

FIG. 3 is a plan view of one pixel region of an array substrate for a conventional fringe field switching mode liquid crystal display, and FIG. 4 is a cross-sectional view of a portion cut along the line IV-IV of FIG.

As shown in FIGS. 3 and 4, a plurality of gate wirings 60 extend in one direction, and a plurality of pixel regions P are defined by intersecting the plurality of gate wirings 60, The data wiring 70 is formed.

Each of the plurality of pixel regions P is connected to the data line 70 and the gate line 60 defining the gate line 62 and the gate insulating layer 64 and an active layer 66a made of pure amorphous silicon And the source and drain electrodes 72 and 74 are formed on the semiconductor layer 66 including the ohmic contact layer 66b made of the impurity amorphous silicon and the ohmic contact layer 66b made of the impurity amorphous silicon. The thin film transistor Tr is located in the switching region TrA.

In each of the plurality of pixel regions P, a pixel electrode 76 having a plate shape connected to the drain electrode 74 of the thin film transistor Tr is formed.

A protective layer 80 as an insulating layer is formed on the pixel electrode 76. A plurality of slit-shaped holes 92 are formed on the protective layer 80 so as to overlap with the plate- The common electrode 90 is formed. The common electrode is formed on the entire surface of the display region where the plurality of pixel regions P are formed.

When a voltage is applied between the common electrode 90 and the plate-shaped pixel electrode 76, a fringe field is formed to drive the liquid crystal, thereby improving the transmission efficiency and displaying a high-quality image .

The array substrate 50 for a liquid crystal display having the above-described structure is manufactured by a total of six mask processes.

Briefly, first, the gate wiring 60 and the gate electrode 62 are formed on the substrate 51 by a first mask process. At the same time, a gate pad (not shown) is formed at one end of the gate wiring 60. Then, the gate insulating film 64 is formed.

Next, the pixel electrode 76 is formed on the gate insulating film 64 by a second mask process.

Next, the active layer 66a and the ohmic contact layer 66b are formed by a third mask process.

Next, the source electrode 72, the drain electrode 74 and the data line 70 are formed by a fourth mask process, and the source electrode 72 and the drain electrode 74 are used as masks To expose the central portion of the active layer 66a by removing a part of the ohmic contact layer 66b. At the same time, a data pad (not shown) is formed at one end of the data line 70.

Next, a gate pad contact hole (not shown) for exposing the gate pad (not shown) and the data pad (not shown) by a fifth mask process and a data pad contact hole ). When forming the gate pad contact hole (not shown), not only the protective layer 80 but also the gate insulating layer 64 under the protective layer 80 are patterned.

Next, the common electrode 90 is formed by a sixth mask process.

The common electrode 90 overlaps with the data line 70 because the common electrode 90 is formed on the entire surface of the substrate 51 on the protective layer 80. At this time, cross-talk occurs between the common electrode 90 and the data line 70, resulting in deterioration of image quality.

In order to minimize the crosstalk problem, the thickness t of the protective layer 80 positioned between the common electrode 90 and the data line 70 should be maximized, and the minimum thickness thereof is about 6000 Å.

However, as the thickness t of the protective layer 80 is increased, the intensity of the electric field formed between the pixel electrode 76 and the common electrode 90 is weakened, so that the driving voltage is increased . That is, in a conventional array substrate for a liquid crystal display device, either a problem of crosstalk or a problem of an increase in driving voltage necessarily occurs.

The present invention aims at solving the crosstalk problem occurring between the common wiring and the data wiring without increasing the driving voltage.

Accordingly, there is a need to provide an array substrate for a liquid crystal display having all advantages of low power consumption while providing a high-quality image.

In order to solve the above problems, the present invention provides a liquid crystal display comprising: a substrate on which a pixel region is defined; A gate line disposed on the substrate and extending along one side of the pixel region; A data line disposed on the substrate and extending along the other side of the pixel region; A thin film transistor connected to the gate wiring and the data wiring; A gate insulating film covering the gate wiring and the data wiring and having a first thickness; A pixel electrode disposed on the gate insulating layer and having a plate shape in the pixel region and connected to the thin film transistor; A protective layer covering the thin film transistor, the pixel electrode, and the gate insulating film, the protective layer having a second thickness; And a common electrode which is located on the protective layer and has a plurality of first holes corresponding to the pixel electrode, wherein the common electrode overlaps the data line, and between the common electrode and the data line, And the protective layer are disposed on the substrate.

The first thickness is 3000 to 5000 Å, and the second thickness is 1000 to 3000 Å.

The sum of the first and second thicknesses is 6000 to 7000 Å.

Wherein the gate wiring includes first to third gate wirings which are spaced apart from each other in parallel to each other, the data wiring includes a first data wiring located between the first and second gate wirings, And a connection pattern in which one end of the second data line is connected to the first data line and the other end of the connection pattern is connected to the second data line.

Wherein the gate insulating film includes first and second contact holes that respectively expose the first data line and the second data line, the connection pattern is located on the gate insulating film, 1 contact hole and the other end of the connection pattern is connected to the second data line through the second contact hole.

And the common electrode has a second hole corresponding to the thin film transistor and the connection pattern.

Wherein the thin film transistor includes a gate electrode connected to the gate wiring and located under the gate insulating film, a semiconductor layer located on the gate insulating film and corresponding to the gate electrode, and source and drain electrodes spaced from each other on the semiconductor layer And the gate insulating film includes a contact hole exposing the data line, and the source electrode is connected to the data line through the contact hole.

A gate pad located on the substrate and connected to one end of the gate wiring; A data pad located on the substrate and connected to one end of the data line; A gate pad electrode connected to the gate pad through a first contact hole formed through the protective layer and the gate insulating layer; And a data pad electrode connected to the data pad through a second contact hole formed through the protective layer and the gate insulating layer.

In another aspect, the present invention provides a method of manufacturing a liquid crystal display device, comprising: forming a gate line extending along one side of the pixel region on a substrate on which a pixel region is defined; and a data line extending along the other side of the pixel region; Forming a thin film transistor connected to the gate line and the data line in the pixel region; Forming a gate insulating film having a first thickness covering the gate wiring and the data wiring; Forming a pixel electrode on the gate insulating film and having a plate shape in the pixel region and connected to the thin film transistor; Forming a protective layer covering the thin film transistor, the pixel electrode, and the gate insulating film, the protective layer having a second thickness; And forming a common electrode on the protective layer and having a plurality of first holes corresponding to the pixel electrode, wherein the common electrode overlaps the data line, and the common electrode is provided between the common electrode and the data line Wherein the gate insulating film and the protective layer are disposed on the gate insulating film.

The first thickness is 3000 to 5000 angstroms, the second thickness is 1000 to 3000 angstroms, and the sum of the first and second thicknesses is 6000 to 7000 angstroms.

The present invention has the advantage of solving the crosstalk problem without increasing the driving voltage by maximizing the thickness of the insulating layer located between the common electrode and the data wiring and minimizing the thickness of the insulating layer located between the common electrode and the pixel electrode .

Thus, it is possible to provide a high-quality image without increasing the driving voltage.

Further, since an additional mask process is not required, an array substrate for a liquid crystal display device capable of providing a high-quality image without increasing the manufacturing cost is provided.

Hereinafter, the present invention will be described in detail with reference to the drawings.

5 is a plan view of a part of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention.

The array substrate for a liquid crystal display of the present invention includes a gate wiring 110 formed on a substrate 101, a data wiring 120, a connection pattern 166, a thin film transistor Tr A pixel electrode 130, a common electrode (not shown), a gate pad 114, and a data pad 116.

The gate wiring 110 extends in a first direction and includes first to third gate wirings 110a, 110b and 110c. The second gate wiring 110b is located between the first and third gate wirings 110a and 110c.

The data line 120 extends in a second direction intersecting the first direction and includes first and second data lines 120a and 10b. The first data line 120a is located between the first and second gate lines 110a and 110b and the second data line 120b is located between the second and third gate lines 110b and 110c. Located.

A region surrounded by the gate wiring 110 and the data wiring 120 is defined as a pixel region P. [ That is, the gate line 110 extends along one side of the pixel region P, and the data line 120 extends along the other side of the pixel region P.

The connection pattern 166 connects the first and second data lines 120a and 10b. That is, one side of the connection pattern 166 is connected to the first data line 120a through a first contact hole 122 exposing the first data line 120a, And the other side is connected to the second data line 120b through a second contact hole 124 exposing the second data line 120b.

The thin film transistor Tr is located in the pixel region P and is connected to the gate line 110 and the data line 120. The thin film transistor Tr includes a gate electrode 112 connected to the gate wiring 110, a gate insulating film (not shown), an active layer (not shown) made of pure amorphous silicon, and an ohmic contact layer A source electrode 162 connected to the data line 120, and a drain electrode 164. The semiconductor layer (not shown) The gate insulating film covers the gate electrode 112, and the semiconductor layer is located on the gate insulating film and overlaps with the gate electrode 112. The source electrode 162 and the drain electrode 164 are located on the semiconductor layer and are spaced apart from each other.

The pixel electrode 130 is located in the pixel region P and has a plate shape. The pixel electrode 130 is made of a transparent conductive material and is connected to the thin film transistor Tr.

The common electrode (not shown) covers the entire substrate 101. That is, the common electrode overlaps the data line 120 and the gate line 110. The common electrode has a plurality of first holes 182 corresponding to the pixel electrodes 130. In addition, the common electrode has a second hole 184 corresponding to the thin film transistor Tr and the connection pattern 166. However, the second hole 184 may be omitted, and the common electrode (not shown) may cover the thin film transistor Tr and the connection pattern 166.

When a voltage is applied to the pixel electrode 130 and the common electrode, an electric field is generated to drive the liquid crystal molecules.

The gate pad 114 is located at one end of the gate line 110 and the data pad 116 is located at one end of the data line 120.

FIG. 6 is a cross-sectional view of the portion cut along the cutting line VI-VI of FIG. 5, and FIG. 7 is a cross-sectional view of the portion cut along the cutting line VII-VII of FIG. FIG. 8 is a cross-sectional view of the portion cut along the cutting line VIII-VIII in FIG. 5, and FIG. 9 is a cross-sectional view of the portion cut along the cutting line IX-IX in FIG.

As shown in the drawing, the first gate wiring (110a in FIG. 5), the second gate wiring 110b, and the third gate wiring (110c in FIG. 5) which are spaced apart from each other in parallel are formed on the substrate 101 And the gate electrode 112 connected to the gate wiring 110 are located. The gate electrode 112 extends from the gate wiring 110.

The first data line 120a located between the first and second gate lines 110a and 110b and the second data line 120b located between the second and third gate lines 110b and 110c The data line 120 including the data line 120b is located on the substrate 101. [

The gate pad 114 connected to one end of the gate line 110 and the data pad 116 connected to one end of the data line 120 are disposed on the substrate 101.

The gate line 110, the gate electrode 112, the data line 120, the gate pad 114 and the data pad 116 are formed on the same layer and made of the same material. The gate line 110, the gate electrode 112, the data line 120, the gate pad 114 and the data pad 116 may be formed of copper, copper alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, Chromium, and a chromium alloy, or may be a multi-layer structure composed of at least two materials.

The gate insulating layer 122 is positioned to cover the gate line 110, the gate electrode 112, the data line 120, the gate pad 114, and the data pad 116. The gate insulating film 122 is made of an inorganic insulating material such as silicon oxide or silicon nitride. In addition, the gate insulating layer 122 has a first thickness t1 of about 3000 to 5000 ANGSTROM.

The gate insulating layer 122 includes a first contact hole 124 exposing one end of the data line 120 and a second contact hole 126 exposing the other end of the data line 120b. And a third contact hole 128 located between the first and second contact holes 124 and 126 and exposing the data line 120. Referring to the second gate line 110b, one end of the first data line 120a located on one side of the second gate line 110b is exposed by the first contact hole 124, The other end of the second data line 120b located on the other side of the second gate line 110b is exposed by the second contact hole 126 and a part of the first data line 120a is exposed by the third And is exposed by the contact hole 128.

On the gate insulating film 122, the pixel electrode 130 is located corresponding to the pixel region (P in FIG. 5). The pixel electrode 130 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) Respectively.

Also, on the gate insulating layer 122, the semiconductor layer 140 overlapping the gate electrode 112 is located. The semiconductor layer 140 includes an active layer (not shown) made of pure amorphous silicon and an ohmic contact layer (not shown) made of impurity amorphous silicon.

The connection pattern 166 is located on the gate insulating layer 122. One end of the connection pattern 166 is connected to the first data line 120a through the first contact hole 124 and the other end of the connection pattern 166 is connected to the second data line 120a through the second contact hole 126 And is connected to the second data line 120b. As a result, the first and second data lines 120a and 120b are connected to each other through the connection pattern 166 that crosses the gate line 110.

The source electrode 162 and the drain electrode 164 are positioned on the semiconductor layer 140 and the gate insulating layer 122. The source electrode 162 is connected to the data line 120 through the third contact hole 128 and the drain electrode 164 is spaced apart from the source electrode 162. In addition, the drain electrode 164 is in contact with the pixel electrode 130.

The source electrode 162, the drain electrode 164, and the connection pattern 166 are located on the same layer and are made of the same material. For example, each of the source electrode 162, the drain electrode 164 and the connection pattern 166 may be formed of a single material selected from the group consisting of copper, copper alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, Layer structure.

The gate electrode 112, the gate insulating layer 122, the semiconductor layer 140, the source electrode 162 and the drain electrode 164 constitute the thin film transistor Tr, (Tr) is connected to the gate wiring 110 and the data wiring 120.

A protective layer 170 is disposed to cover the source electrode 162, the drain electrode 164, and the connection pattern 166. The passivation layer 170 is made of an inorganic insulating material such as silicon oxide or silicon nitride and has a second thickness t2 of about 1000 to 3000 ANGSTROM. That is, the protective layer 170 has a thickness smaller than that of the gate insulating layer 122.

The passivation layer 170 and the gate insulating layer 122 may include a fourth contact hole 172 for exposing the gate pad 114 and a fifth contact hole 174 for exposing the data pad 116 do.

The common electrode 180, the gate pad electrode 186, and the data pad electrode 188 are located on the passivation layer 170. The common electrode 180 covers the entire surface of the substrate 101 and has a plurality of first holes 182 corresponding to the pixel electrodes 130. In addition, the thin film transistor Tr has a second hole 184 corresponding to the connection pattern 166.

The gate pad electrode 186 is connected to the gate pad 114 through the fourth contact hole 172 and the data pad electrode 188 is connected to the data pad 174 through the fifth contact hole 174. [ 116).

The common electrode 180, the gate pad electrode 186 and the data pad electrode 188 are formed of indium-tin-oxide (ITO) or indium-zinc- oxide, IZO).

In the array substrate for a liquid crystal display device having the above-described structure, the thickness of the protective layer 170 located between the common electrode 180 and the pixel electrode 130 is about 1000 to 3000 ANGSTROM, The intensity of the electric field formed between the common electrode 180 and the pixel electrode 130 can be increased with a small driving voltage.

Table 1 shows experimental data of the maximum transmittance and the maximum drive voltage according to the thickness of the protective layer.

Table 1

The thickness of the protective layer [Å] 1000 2000 3000 4000 5000 6000 Maximum transmittance 73.30% 73.57% 73.80% 73.98% 74.12% 74.22% Maximum driving voltage 3.5 3.7 3.9 4.1 4.3 4.5

As shown in Table 1, it can be seen that a thicker protective layer requires a higher driving voltage to exhibit the maximum transmittance. That is, although the change in the thickness of the protective layer hardly changes in terms of the transmittance, the increase in the thickness of the protective layer 170 involves an increase in the drive voltage. As a result, when the problem of crosstalk is to be prevented by increasing only the thickness of the protective layer in the conventional array substrate for a liquid crystal display, the driving voltage necessarily increases.

However, in the present invention, the gate insulating layer 122 and the protective layer 170 are positioned between the common electrode 180 and the data line 120 while the thickness of the protective layer 170 is about 1000 to 3000 ANGSTROM, And an array substrate for a liquid crystal display device which does not require an increase in driving voltage is provided.

The data line 120 is located below the gate insulating layer 122 and the sum of the thickness of the gate insulating layer 122 and the data line 120 is at least 6000 ANGSTROM. The problem of crosstalk can be prevented. For example, the total thickness of the gate insulating layer 122 and the passivation layer 170 may be about 6000 to 7000 ANGSTROM.

That is, in the conventional array substrate for a liquid crystal display device, only a protective layer having a thickness of 6000 ANGSTROM or more exists between the common electrode and the data line in order to prevent crosstalk, Causing a problem of an increase in voltage.

However, in the array substrate for a liquid crystal display of the present invention, since only the protective layer is located between the common electrode and the pixel electrode and the gate insulating film as well as the protective layer is located between the data wiring and the common wiring, It has an advantage that it can be driven.

Figs. 10A to 10G are process sectional views of the portion cut along the cutting line VI-VI of Fig. 5, and Figs. 11A to 11G are process sectional views of the portion cut along the cutting line VII-VII of Fig. Figs. 12A to 12G are process cross-sectional views of the portion cut along the cutting line VIII-VIII in Fig. 5, and Figs. 13A to 13G are process cross-sectional views of the portion cut along the cutting line IX-IX in Fig.

Figures 10A, 11A, 12A and 13A show a first mask process.

A first metal material layer (not shown) is formed on the substrate 101 and patterned by the first mask process, as shown in FIGS. 10A, 11A, 12A, and 13A, 110, the gate electrode 112, the data line 120, the gate pad 114, and the data pad 116 are formed. The first metallic material layer may be a single layer or a multilayer. For example, the first metal material layer may have a single layer structure composed of any one of copper, copper alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, chromium, and chromium alloy.

Next, an inorganic insulating material such as silicon oxide or silicon nitride is deposited on the gate line 110, the gate electrode 112, the data line 120, the gate pad 114, and the data pad 116 Thereby forming the gate insulating film 122 having the first thickness t1.

10B, 11B, 12B and 13B show a second mask process.

As shown in FIGS. 10B, 11B, 12B, and 13B, a first transparent conductive material layer (not shown) is formed on the gate insulating layer 122 and patterned by a second mask process, The pixel electrode 130 is formed. For example, the first transparent conductive material layer is made of ITO or IZO. The pixel electrode 130 has a plate shape in the pixel region P.

FIGS. 10c, 10d, 11c, 11d, 12c, 12d, 13c and 13d show a third mask process.

The pure amorphous silicon layer and the impurity amorphous silicon layer are sequentially deposited on the pixel electrode 130 and the gate insulating layer 122 as shown in FIGS. 10C, 11C, 12C, and 13C, (Not shown) and an impurity amorphous silicon layer (not shown) are formed. Thereafter, a photoresist (PR) is coated on the impurity amorphous silicon layer to form a PR layer (not shown), and a transmissive portion TP, a blocking portion BP, and a semi-transmissive portion HTP ) Is positioned. The transmissive portion TP corresponds to the first to third contact holes 124, 126 and 128, the blocking portion BP corresponds to the semiconductor layer 140 in FIG. 6, And the transmission portion (HTP) corresponds.

The PR layer is exposed and developed using the mask M to form a first PR pattern 191 having a third thickness corresponding to the transflective portion HTP and a second PR pattern 191 having a third thickness corresponding to the blocking portion BP, A second PR pattern 192 having a fourth thickness greater than the third thickness is formed. The PR layer corresponding to the transmissive portion TP is removed to expose the impurity amorphous silicon layer.

Next, by etching the impurity amorphous silicon layer, the pure amorphous silicon layer and the gate insulating film 122 below the first and second PR patterns 191 and 192 as an etching mask, The third contact holes 124, 126, and 128, the pure amorphous silicon pattern 132, and the impurity amorphous silicon pattern 134 are formed.

Next, as shown in FIGS. 10D, 11D, 12D, and 13D, the ashing process is performed to remove the first PR pattern 191 to expose the impurity amorphous silicon pattern 134. At this time, the second PR pattern 192 is reduced in thickness to form a third PR pattern 193 having a fifth thickness smaller than the fourth thickness. That is, the third PR pattern 193 corresponds to the gate electrode 112.

Next, the impurity amorphous silicon pattern 134 and the underlying pure amorphous silicon pattern 132 are etched using the third PR pattern 193 as an etching mask to form the pixel electrode 130, The semiconductor layer 140 including the active layer 140a made of pure amorphous silicon and the ohmic contact layer 140b made of the impurity amorphous silicon corresponding to the gate electrode 112 is formed on the gate insulating film 122).

FIGS. 10E, 11E, 12E and 13E show the fourth mask process.

A second metal material layer (not shown) is formed on the gate insulating layer 122, the pixel electrode 130 and the semiconductor layer 140, as shown in FIGS. 10E, 11E, 12E and 13E. And the second metal material layer is patterned by a fourth mask process to form the source electrode 162, the drain electrode 164, and the connection pattern 166. The second metallic material layer may be a single layer or a multilayer. For example, the second metal material layer may have a single layer structure composed of any one of copper, copper alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, chromium, and chromium alloy.

The source electrode 162 is connected to the data line 120 through the third contact hole 128 and the drain electrode 164 is spaced apart from the source electrode 162. The drain electrode 164 is in contact with the pixel electrode 130. The connection pattern 166 contacts the first and second data lines 120a and 120b through the first and second contact holes 124 and 126 so that the first and second data lines 120a, and 120b.

Figs. 10F, 11F, 12F and 13F show a fifth mask process.

The pixel electrode 130, the source electrode 162, the drain electrode 164, and the connection pattern 166 (see FIG. 10F, FIG. 11F, 12F and 13F) The protective layer 170 is formed.

Then, the fourth and fifth contact holes 172 and 174 are formed by patterning the passivation layer 170 and the gate insulating layer 122 under the passivation layer by a fifth mask process. The protective layer 170 has a second thickness t2 and is made of an inorganic insulating material such as silicon oxide or silicon nitride. The fourth and fifth contact holes 172 and 174 expose the gate pad 114 and the data pad 116, respectively.

Figures 10g, 11g, 12g and 13g show the sixth mask process.

A second transparent conductive material layer (not shown) is formed on the protective layer 170 and patterned by a sixth mask process, as shown in FIGS. 10G, 11G, 12G, and 13G, The electrode 180, the gate pad electrode 186, and the data pad electrode 188 are formed. For example, the second transparent conductive material layer is made of ITO or IZO. The gate pad electrode 186 is connected to the gate pad 114 through the fourth contact hole 172 and the data pad electrode 188 is connected to the data pad 174 through the fifth contact hole 174. [ 116, respectively.

The common electrode 180 has a plurality of first holes 182 corresponding to the pixel electrode 130 and a second hole 184 corresponding to the thin film transistor Tr and the connection pattern 166 .

Since the common electrode 180 is formed over the entire surface of the substrate 101, the common electrode 180 overlaps the data line 120. At this time, a crosstalk problem arises between the common electrode 180 and the data line 120. In the present invention, the gate insulating film 122 having the first thickness t1 and the second thickness t2 have a cross- The protective layer 170 is located between the common electrode 180 and the data line 120. The cross talk problem between the common electrode 180 and the data line 120 can be effectively prevented because the sum of the thicknesses of the gate insulating layer 122 and the protective layer 170 is about 6000 ANGSTROM.

That is, in the present invention, the thickness of the protective layer 170 is smaller than that of the conventional array substrate for a liquid crystal display, but the protective layer 170 is formed between the common electrode 180 and the data line 120, The gate insulating film 122 is located and the crosstalk problem can be prevented.

In addition, since the thickness of the protective layer 170 located between the common electrode 180 and the pixel electrode 130 is smaller than that of the conventional array substrate for a liquid crystal display apparatus, the driving voltage and the power consumption can be reduced .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

2A and 2B are cross-sectional views respectively showing operations of an on-state and an off-state of a general transverse electric field type liquid crystal display device.

3 is a plan view of one pixel region of an array substrate for a conventional fringe field switching mode liquid crystal display.

FIG. 4 is a cross-sectional view of a portion cut along line IV-IV of FIG. 3; FIG.

5 is a plan view of a part of an array substrate for a fringe field switching mode liquid crystal display according to a first embodiment of the present invention.

FIG. 6 is a cross-sectional view of the portion cut along line VI-VI of FIG. 5; FIG.

Fig. 7 is a cross-sectional view of the portion cut along line VII-VII of Fig. 5;

8 is a cross-sectional view of the portion cut along line VIII-VIII of FIG. 5;

Fig. 9 is a cross-sectional view of a portion cut along the cutting line IX-IX of Fig. 5; Fig.

Figs. 10A to 10G are process cross-sectional views of the portion of Fig. 5 cut along the cutting line VI-VI.

11A to 11G are process cross-sectional views of a portion cut along line VII-VII of FIG.

Figs. 12A to 12G are process cross-sectional views of the portion cut along the cutting line VIII-VIII of Fig. 5;

Figs. 13A to 13G are process sectional views of a portion cut along the cutting line IX-IX in Fig. 5;

Claims (11)

A substrate having a pixel region defined therein; A gate wiring formed on the substrate and including first to third gate wirings extending along one side of the pixel region and spaced apart from each other in parallel; A first data line located on the substrate and extending along the other side of the pixel region and located between the first and second gate wirings, and a second data line located between the second and third gate wirings; A data line including a data line; First and second contact holes exposing the first and second portions of the first data line and the third contact hole covering the gate line and the data line, and a third contact hole exposing the second data line, A gate insulating film having a gate insulating film; A thin film transistor connected to the gate wiring and the data wiring and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode, the source electrode connected to the first data line through the first contact hole; A connection pattern located on the gate insulating film and having one end connected to the first data line through the second contact hole and the other end connected to the second data line through the third contact hole; A pixel electrode disposed on the gate insulating layer and having a plate shape in the pixel region and connected to the thin film transistor; A protective layer covering the thin film transistor, the pixel electrode, and the gate insulating film, the protective layer having a second thickness; And a common electrode located on the protective layer and having a plurality of first holes corresponding to the pixel electrodes, and a second hole corresponding to the thin film transistor and the connection pattern, Wherein the common electrode overlaps the data line, and the gate insulating film and the protective layer are positioned between the common electrode and the data line. The method according to claim 1, Wherein the first thickness is 3000 to 5000 ANGSTROM and the second thickness is 1000 to 3000 ANGSTROM. 3. The method of claim 2, And the sum of the first and second thicknesses is 6000 to 7000 ANGSTROM. delete delete delete The method according to claim 1, Wherein the gate electrode is connected to the gate wiring and is located under the gate insulating film, the semiconductor layer is located on the gate insulating film and corresponds to the gate electrode, and the source electrode and the drain electrode are spaced apart from each other And a plurality of pixel electrodes. The method according to claim 1, A gate pad located on the substrate and connected to one end of the gate wiring; A data pad located on the substrate and connected to one end of the data line; A gate pad electrode connected to the gate pad through a gate pad contact hole formed through the protective layer and the gate insulating layer; And a data pad electrode connected to the data pad through a data pad contact hole formed through the protective layer and the gate insulating layer. A gate wiring including first to third gate wirings extending along one side of the pixel region and spaced parallel to each other on a substrate on which a pixel region is defined; a gate electrode connected to the gate wiring; Forming a data line including a first data line extending between the first and second gate lines and a second data line extending between the second and third gate lines; First and second contact holes exposing the first and second portions of the first data line and the third contact hole covering the gate line and the data line, and a third contact hole exposing the second data line, Forming a gate insulating film having a gate insulating film thereon; Forming a pixel electrode on the gate insulating film and having a plate shape in the pixel region; Forming a semiconductor layer corresponding to the gate electrode on the gate insulating film; A source electrode disposed on the semiconductor layer and connected to the first data line through the first contact hole; a drain electrode spaced from the source electrode on the semiconductor layer and connected to the pixel electrode; Forming a connection pattern in which one end is connected to the first data line through the second contact hole and the other end is connected to the second data line through the third contact hole; Forming a protective layer covering the source electrode, the drain electrode, the connection pattern, the pixel electrode, and the gate insulating layer, the protective layer having a second thickness; Forming a common electrode on the protective layer and having a plurality of first holes corresponding to the pixel electrodes and a second hole corresponding to the source electrode, the drain electrode, and the connection pattern, Wherein the common electrode overlaps with the data line, and the gate insulating film and the protective layer are positioned between the common electrode and the data line. 10. The method of claim 9, Wherein the first thickness is 3000 to 5000 angstroms, the second thickness is 1000 to 3000 angstroms, and the sum of the first and second thicknesses is 6000 to 7000 angstroms. A substrate having a pixel region defined therein; A gate line disposed on the substrate and extending along one side of the pixel region; A data line disposed on the substrate and extending along the other side of the pixel region; A thin film transistor connected to the gate wiring and the data wiring; A gate insulating film covering the gate wiring and the data wiring and having a first thickness; A pixel electrode disposed on the gate insulating layer and having a plate shape in the pixel region and connected to the thin film transistor; A protective layer covering the thin film transistor, the pixel electrode, and the gate insulating film, the protective layer having a second thickness; And a common electrode which is located on the protective layer and has a plurality of first holes corresponding to the pixel electrodes, Wherein the common electrode overlaps the data line and the gate insulating film and the protective layer are positioned between the common electrode and the data line, and the second thickness is smaller than the first thickness.

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