KR101692446B1 - Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same - Google Patents

Abstract

A three-dimensional semiconductor device and a manufacturing method thereof are provided. The apparatus includes a conductive structure disposed on a substrate, the conductive pattern including conductive patterns stacked in that order, a semiconductor pattern penetrating through the conductive structure to be inserted into the upper surface of the substrate, and an insulating film structure interposed between the semiconductor pattern and the conductive structure do. Further, the semiconductor pattern extends horizontally below the insulating film structure to directly contact the side walls of the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional semiconductor device,

The present invention relates to a semiconductor device, and more particularly, to a three-dimensional memory semiconductor device including three-dimensionally arranged memory cells.

3D-IC memory technology is a technique for increasing the memory capacity, which means various technologies related to three-dimensionally arranging memory cells. Memory capacity can be increased by (1) pattern refinement techniques and (2) multilevel cell (MLC) techniques in addition to 3D-IC memory technology. However, pattern refinement techniques are costly, and MLC technology is limited by the number of bits per cell that can be increased. For this reason, 3D-IC technology appears to be an inevitable way to increase memory capacity. Of course, pattern refinement and MLS techniques are also expected to evolve independently of 3D-IC technology, in that pattern fining and MLS technologies can be implemented in 3D-IC technology to further increase memory capacity.

As one of the 3D-IC technologies, punch-and-plug technology has recently been proposed. The punch-and-plug technique includes forming sequentially multiple layers of thin films on a substrate and then forming plugs through the thin films. With this technology, the memory capacity of a 3D memory device can be greatly increased without a large increase in manufacturing cost, and this technology has attracted a great deal of attention in recent years.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a three-dimensional semiconductor device capable of preventing a decrease in operating current and an increase in resistance of a string.

 SUMMARY OF THE INVENTION It is an object of the present invention to provide a three-dimensional semiconductor device capable of preventing a reduction in operating current and an increase in resistance of a string.

There is provided a method of manufacturing a three-dimensional semiconductor device including a semiconductor pattern inserted into an upper surface of a substrate. The method includes forming a mold structure on a substrate, forming an opening through the mold structure to expose an upper surface of the substrate, sequentially forming a vertical film and a first semiconductor film covering the inner wall of the opening, A through hole is formed through the first semiconductor film and the vertical film to expose the upper surface of the substrate at the bottom of the through hole, and the vertical film exposed through the through hole is isotropically etched to form an undercut And forming a second semiconductor film in the undercut region, the second semiconductor film connecting the substrate and the first semiconductor film.

According to some embodiments, the vertical film and the first semiconductor film are formed so as to cover the inner wall of the opening portion in a substantially cone-shaped thickness, and the sum of the deposition thicknesses of the vertical film and the first semiconductor film is And may be less than half the width of the opening. At this time, the step of forming the through-holes may include forming an insulating film on the first semiconductor film by anisotropically etching the first semiconductor film to form a semiconductor spacer exposing an upper surface of the vertical film at the bottom of the opening, .

According to some embodiments, the step of forming the penetrating groove may include forming a protective film spacer exposing a bottom surface of the first semiconductor film to an inner wall of the first semiconductor film before anisotropically etching the first semiconductor film As shown in FIG. The protective film spacer may be formed of a material having etch selectivity with respect to the first semiconductor film. In addition, the protective film spacer may be formed to have a thickness thinner than a half of a difference between a half of the width of the opening and a sum of the vertical film and the deposition thickness of the first semiconductor film.

According to some embodiments, before forming the undercut region, a step of isotropically etching the first semiconductor film using the protective film spacer as an etching mask may be further performed. In addition, the protective film spacer may be removed during the step of forming the undercut region.

According to some embodiments, the vertical film includes a capping film, a charge storage film, and a tunnel film that in turn cover the inner wall of the opening, and the step of forming the undercut region includes forming the charge storage film exposed by the through- And forming a first undercut region exposing the capping film and the tunnel film. Then, the capping film and the tunnel film exposed by the first undercut region may be isotropically etched to form a second undercut region.

According to other embodiments, the vertical film includes a capping film, a charge storage film, and a tunneling film that in turn cover the inner wall of the opening, and the step of forming the undercut region includes forming the tunneling film exposed by the through- And forming a first undercut region exposing the charge storage film by isotropically etching the film. Thereafter, the charge storage film exposed by the first undercut region may be isotropically etched to form a second undercut region.

There is provided a three-dimensional semiconductor device including a semiconductor pattern inserted into an upper surface of a substrate. The apparatus includes a conductive structure disposed on a substrate including conductive patterns stacked in turn, a semiconductor pattern penetrating the conductive structure to be inserted into the upper surface of the substrate, and an insulating film structure interposed between the semiconductor pattern and the conductive structure . ≪ / RTI > In addition, the semiconductor pattern may extend horizontally below the insulating film structure to directly contact the side wall of the substrate.

According to some embodiments, the substrate may be comprised of a semiconductor material having fewer crystal defects than the semiconductor pattern.

According to some embodiments, the semiconductor pattern may include a semiconductor spacer covering the inner wall of the insulator structure and a semiconductor body covering the inner wall of the spacer. In this case, the bottom surface of the semiconductor spacer is inserted deeper into the substrate than the bottom surface of the insulating film structure, and the semiconductor body portion extends horizontally below the insulating film structure to directly contact the side wall of the substrate.

According to some embodiments of the present invention, an undercut region is formed below the vertical pattern, and a semiconductor material is formed in the undercut region to connect the substrate and the semiconductor spacer. Accordingly, the problems of the reduction of the operating current and the resistance increase of the string, which will be described with reference to Fig. 65, can be prevented.

1 to 11 are perspective views for explaining a method of manufacturing a three-dimensional semiconductor device according to a first embodiment of the present invention.
12 to 21 are perspective views for explaining a method of manufacturing a three-dimensional semiconductor device according to a second embodiment of the present invention.
22 to 24 are perspective views for explaining the three-dimensional semiconductor devices according to the first embodiment of the present invention.
25 to 27 are perspective views for explaining the three-dimensional semiconductor devices according to the second embodiment of the present invention.
28 to 43 are perspective views for explaining embodiments of the present invention related to the structure of the information storage film.
44 to 46 are sectional views for explaining the three-dimensional semiconductor devices according to the modified embodiments.
47 and 48 are perspective views for explaining three-dimensional semiconductor devices according to other modified embodiments.
49 and 50 are perspective views for explaining the three-dimensional semiconductor devices according to the comparative examples.
Figs. 51 to 64 are sectional views showing specific embodiments for forming the undercut region described with reference to Fig. 24. Fig.
65 and 66 are cross-sectional views for explaining and comparing three-dimensional semiconductor devices according to embodiments of the present invention.
67 is a block diagram schematically showing an example of a memory card having a flash memory device according to the present invention.
68 is a block diagram briefly showing an information processing system incorporating a memory system according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween. Further, in the drawings, the thicknesses of the films and regions are exaggerated for an effective explanation of the technical content. Also, while the terms first, second, third, etc. in various embodiments of the present disclosure are used to describe various regions, films, etc., these regions and films should not be limited by these terms . These terms are only used to distinguish any given region or film from another region or film. Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment.

The three-dimensional semiconductor device according to embodiments of the present invention may include a cell array region, a peripheral circuit region, a sense amplifier region, a decoding circuit region, and a connection region. The cell array region is provided with a plurality of memory cells and bit lines and word lines for electrical connection to the memory cells. Circuits for driving the memory cells are arranged in the peripheral circuit region, and circuits for reading information stored in the memory cells are arranged in the sense amplifier region. The connection region may be disposed between the cell array region and the decoding circuit region, and a wiring structure for electrically connecting the word lines and the decoding circuit region may be disposed.

In the following, technical features related to a part of the cell array region of the three-dimensional semiconductor device will be mainly described. Korean Patent Application No. 2009-0126854 filed on December 18, 2009, Korean Patent Application No. 2010-0014751 filed on February 18, 2010, Korean Patent Application No. 2010 Korean Patent Application No. 2009-0099370 filed on October 19, 2009, and U.S. Patent Application No. 12 / 480,399 filed on June 8, 2009 are not limited to the cell array region ≪ / RTI > and the like). The contents disclosed in Korean Patent Application Nos. 2009-0126854, 2010-0014751, 2010-0006124, 2009-0099370 and U.S. Patent Application No. 12 / 480,399 are incorporated in their entirety as part of this application.

In addition, Korean Patent Application No. 2010-0006124 discloses a structure in which memory structures are formed in multiple layers by repeating the steps of forming a memory structure. The technical concept of the present invention can be implemented by extending to embodiments forming multi-layer memory structures by repeatedly forming the memory structure described below.

[Method - First Example ]

1 to 11 are perspective views for explaining a method of manufacturing a three-dimensional semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1, a mold structure 100 is formed on a substrate 10. The substrate 10 may be one of a semiconductor material, an insulating material, a semiconductor covered by an insulating material, or a conductor. For example, the substrate 10 may be a silicon wafer.

According to a modified embodiment, a lower structure (not shown) including at least one transistor may be disposed between the substrate 10 and the mold structure 100. However, for the sake of an easier understanding of the technical idea of the present invention, an embodiment in which the mold structure 100 is formed directly on the substrate 10 will be exemplified below. Nevertheless, the technical idea of the present invention is not limited thereto.

The mold structure 100 may include a plurality of insulating films 121 to 129: 120 and a plurality of sacrificial films 131 to 138: 130. The insulating films 120 and the sacrificial films 130 may be alternately and repeatedly stacked, as shown. The sacrificial layer 130 may be formed of a material that can be etched with respect to the insulating layer 120 with etching selectivity. That is, in the step of etching the sacrificial layer 130 using a predetermined etching recipe, the sacrificial layer 130 may be formed of a material that can be etched while minimizing the etching of the insulating layer 120. As is known, such etch selectivity can be quantitatively expressed through the ratio of the etch rate of the sacrificial layer 130 to the etch rate of the insulating layer 120. According to one embodiment, the sacrificial layer 130 may provide an etch selectivity of 1: 10 to 1: 200 (more specifically 1: 1 to 1: 100) to the insulating layer 120 It can be one of the substances. For example, the insulating layer 120 may be at least one of a silicon oxide layer and a silicon nitride layer. The sacrifice layer 130 may be formed of a silicon oxide layer, a silicon oxide layer, a silicon carbide layer, Lt; / RTI > In the following, for the sake of a better understanding of the technical idea of the present invention, an embodiment will be described in which the insulating films 120 are a silicon oxide film and the sacrificial films 130 are silicon nitride films.

Meanwhile, according to one embodiment, as illustrated, the sacrificial layers 130 may be formed to have substantially the same thickness. Alternatively, the thicknesses of the insulating films 120 may not be all the same. For example, the lowermost layer 121 of the insulating layers 120 is formed to be thinner than the sacrificial layer 130, and the third layer 123 and the third layer 127 from the bottom are formed at the sacrifice layer 130, The remaining portions of the insulating films 120 may be thinner or thicker than the sacrificial layer 130. [ However, the thickness of the insulating films 120 may be variously changed from that shown in FIG. 1, and the number of the layers constituting the mold structure 100 may be variously modified.

Referring to FIGS. 2 and 3, after forming the openings 105 through the mold structure 100, a vertical film 150 is formed which cone-covers the inner walls of the openings 105. The vertical film 150 may extend horizontally from the openings 105 to cover the upper surface of the mold structure 100.

According to this embodiment, the openings 105 may be formed in a hole shape. That is, each of the openings 105 may be formed such that its depth is at least five times larger than its width. In addition, according to this embodiment, the openings 105 can be formed two-dimensionally on the upper surface (i.e., the xy plane) of the substrate 10. [ That is, each of the openings 105 may be an isolated region formed apart from others along the x and y directions.

The forming of the openings 105 may include forming a predetermined mask pattern defining the positions of the openings 105 on the mold structure 100 and forming the openings 105 on the mold structure 100 ) May be anisotropically etched. Meanwhile, since the mold structure 100 includes at least two different films, the side walls of the opening 105 may not be completely perpendicular to the upper surface of the substrate 10. For example, the closer to the upper surface of the substrate 10, the smaller the width of the opening 105 can be. Such non-uniformity of the width of the opening 105 may cause non-uniformity in the operating characteristics of the transistors arranged three-dimensionally. A more detailed description of such non-uniformity and methods for improving it are disclosed in U.S. Serial No. 12 / 420,518, the disclosure of which is incorporated herein by reference in its entirety.

In an embodiment in which the mold structure 100 is formed directly on the substrate 10, the opening 105 may be formed to expose the upper surface of the substrate 10 as shown in the figure. In addition, as a result of the over-etch in the anisotropic etching step, the substrate 10 under the opening 105 as shown can be recessed to a predetermined depth.

The vertical film 150 may be formed of one thin film or a plurality of thin films. For example, the vertical film 150 may comprise at least one of the thin films used as a memory element of a charge trapped non-volatile memory transistor. Embodiments of the present invention can be variously classified according to the thin films constituting the vertical film 150. These refined embodiments will be described again in detail with reference to Figs. 28 to 35 hereinafter.

Referring to FIG. 4, a vertical pattern 155 and a semiconductor spacer 165, which sequentially cover the inner wall of each of the openings 105, are formed. In this step, after forming a first semiconductor film that cone-covers the resultant product formed with the vertical film 150, the first semiconductor film and the vertical film 150 are anisotropically etched to form an opening at the bottom of the openings 105 And exposing the top surface of the substrate 10. Accordingly, the vertical patterns 155 and the semiconductor spacers 165 may be formed into a cylindrical shape having open ends. Also, as a result of the over-etching in the step of anisotropically etching the first semiconductor film, the upper surface of the substrate 10 exposed by the semiconductor spacers 165, as shown, .

During the anisotropic etching step, a part of the vertical film 150 located under the semiconductor spacer 165 may not be etched. In this case, the vertical pattern 155 may be formed on the semiconductor spacer 165, And a bottom portion interposed between the bottom surface of the substrate 10 and the top surface of the substrate 10. According to a modified embodiment, the step of etching the exposed surface of the vertical pattern 155 using the semiconductor spacer 165 as an etch mask may further be performed. In this case, as shown in FIG. 24, an undercut region may be formed under the semiconductor spacer 165, and the length of the vertical pattern 155 may be shorter than the length of the semiconductor spacer 165.

In addition, the top surface of the mold structure 100 may be exposed as a result of the anisotropic etching of the first semiconductor film and the vertical film 150. Thus, each of the vertical patterns 155 and each of the semiconductor spacers 165 may be localized within the openings 105. [ That is, the vertical patterns 155 and the semiconductor spacers 165 may be two-dimensionally arranged on the xy plane.

The first semiconductor film may be a polycrystalline silicon film formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. In addition, the first semiconductor film may be formed to have a thickness selected from the range of 1/50 to 1/5 of the width of the opening 105. According to a modified embodiment of the present invention, the first semiconductor film may be formed using one of the epitaxial techniques. Korean Patent Application No. 2010-0009628, filed February 2, 2010, discloses epitaxial technologies that can be used to implement the technical idea of the present invention, the disclosure of which is incorporated herein by reference in its entirety do. According to another modified embodiment of the present invention, the first semiconductor film may be one of an organic semiconductor film and carbon nanostructures.

Referring to FIGS. 5 and 6, a second semiconductor layer 170 and a buried insulating layer 180 are sequentially formed on the resultant structure having the vertical pattern 155 formed thereon.

The second semiconductor film 170 may be a polycrystalline silicon film formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. According to one embodiment, the second semiconductor film 170 may be formed in conformity with a thickness that does not completely fill the opening 105. That is, as shown in the drawing, the second semiconductor film 170 may define a pinhole 105a in the opening 105.

The buried insulating layer 180 may be formed to fill the pin hole 105a, and may be one of insulating materials and a silicon oxide layer formed using the SOSO technique. According to one embodiment, before forming the buried insulating layer 180, a hydrogen annealing step may be further performed in which the resultant with the second semiconductor layer 170 is annealed in a gas atmosphere including hydrogen or deuterium. Many of the crystal defects present in the semiconductor spacer 165 and the second semiconductor film 170 can be healed by this hydrogen annealing step.

According to a modified embodiment of the present invention, the second semiconductor film 170 may be formed to fill the openings 105 in which the semiconductor spacer 165 is formed. In this case, The forming step may be omitted. Figures 23 and 24 illustrate the final result according to this modified embodiment by way of example.

Referring to FIG. 7, trenches 200 are formed through the mold structure 100 to expose the sacrificial layers 130 and the sidewalls of the insulating layers 120. The trenches 200 may be spaced apart from and spaced from the openings 105 as shown.

The forming of the trenches 200 may be performed by forming an etch mask on the upper surface of the mold structure 100 or the upper surface of the buried insulating layer 180, And anisotropically etching the films under the etch mask. Thus, as shown, the second semiconductor layer 170 and the buried insulating layer 180 may be patterned on top of the mold structure 100 to define the top inlets of the trenches 200. As a result of the over-etch in the anisotropic etching step, the substrate 10 under the trench 200 as shown can be recessed to a predetermined depth.

On the other hand, since the object to be etched is substantially the same, the trenches 200 may have a reduced width, as the opening 105 is closer to the upper surface of the substrate 10. This non-uniformity of the widths of the trenches 200 may cause non-uniformity in the operating characteristics of the transistors arranged in a three-dimensional manner. A more detailed description of such non-uniformity and methods for improving it are disclosed in U.S. Application No. 12 / 420,518, filed on April 8, 2009, the disclosure of which is incorporated herein by reference in its entirety do.

According to one embodiment, as shown, a pair of trenches 200 may be formed on either side of each of the openings 105. [ That is, the numbers of the openings 105 and the trenches 200 arranged along the x-axis direction with the same y-coordinate may be substantially the same. However, the technical idea of the present invention is not limited to these embodiments. For example, Korean Patent Application No. 2009-0126854, filed on December 18, 2009, discloses modified embodiments relating to the relative placement of the trenches 200 to the openings 105. The contents disclosed in Korean Patent Application No. 2009-0126854 are incorporated in their entirety as part of this application.

Referring to FIG. 8, the exposed sacrificial layers 130 are selectively removed to form recessed regions 210 between the insulating layers 120.

The recessed regions 210 may be a gap region extending horizontally from the trenches 200 and may be formed to expose sidewalls of the vertical patterns 155. More specifically, the outer boundary of the recessed region 210 is defined by the insulating films 120 located on its upper / lower sides and the trenches 200 located on both sides thereof . In addition, the internal boundary of the recessed region 210 is defined by the vertical patterns 155 passing vertically through it.

The forming of the recessed regions 210 may include etching the sacrificial layers 130 horizontally using etch recipe having etch selectivity with respect to the insulating layers 120 and the vertical patterns 155 . For example, if the sacrificial layer 130 is a silicon nitride layer and the insulating layers 120 are a silicon oxide layer, the horizontal etching may be performed using an etchant containing phosphoric acid.

Referring to FIG. 9, horizontal structures HS filling the recessed regions 210 are formed. The horizontal structure HS may include horizontal patterns 220 covering the inner wall of the recess region 210 and a conductive pattern 230 filling the remaining space of the recess region 210.

The forming of the horizontal structures HS may include forming a horizontal layer and a conductive layer sequentially filling the recessed regions 210 and then removing the conductive layer in the trenches 200, And leaving the conductive patterns 230 within the conductive patterns 210.

The horizontal film or the horizontal patterns 220 may be formed of one thin film or a plurality of thin films, similar to the case of the vertical film 150. According to one embodiment, the horizontal pattern 220 may comprise a blocking dielectric layer of a charge trapped non-volatile memory transistor. As described above, the embodiments of the present invention can be variously classified according to the thin film constituting each of the vertical film 150 and the horizontal pattern 220. These refined embodiments will be described again in detail with reference to Figs. 28 to 35 hereinafter.

The conductive film may be formed to fill the recessed regions 210 covered by the horizontal film. At this time, the trenches 200 may be completely or partially filled with the conductive film. The conductive film may include at least one of doped silicon, metal materials, metal nitride films, and metal silicides. For example, the conductive film may include a tantalum nitride film or tungsten. According to one embodiment, the conductive layer may be formed to cone-cover the inner wall of the trench 200, in which case the forming of the conductive pattern 230 may be performed in the trench 200, And removing the film by a method of isotropic etching. According to another embodiment, the conductive layer may be formed to fill the trench 200, wherein forming the conductive pattern 230 includes anisotropically etching the conductive layer in the trench 200 .

According to an embodiment of the present invention for a flash memory, the step of forming the conductive patterns 230 and then forming the impurity regions 240 may be further performed. The impurity regions 240 may be formed through an ion implantation process and may be formed in the substrate 10 exposed through the trenches 200. Meanwhile, the impurity regions 240 may have a different conductivity type from the substrate 10. Alternatively, the region of the substrate 10 contacting the second semiconductor film 170 (hereinafter referred to as a contact region) may have the same conductivity type as that of the substrate 10. Accordingly, the impurity regions 240 may form a p-n junction with the substrate 10 or the second semiconductor film 170.

According to one embodiment, each of the impurity regions 240 may be connected to each other to be in an equipotential state. According to another embodiment, each of the impurity regions 240 may be electrically isolated so as to have different potentials. According to another embodiment, the impurity regions 240 may constitute a plurality of independent source groups including a plurality of different impurity regions, and each of the source groups may be electrically connected to each other to have different potentials Can be separated.

Referring to FIG. 10, an electrode separation pattern 250 filling the trenches 200 is formed. The step of forming the electrode separation pattern 250 may include exposing an upper surface of the mold structure 100 by forming an electrode separation layer on the resultant product in which the impurity regions 240 are formed, . The electrode separator may be formed of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, and the etching step may be performed using a planarization technique such as a chemical-mechanical polishing technique or an etch-back technique. As a result of the planarization etch, the buried insulating layer 180 and the second semiconductor layer 170 may be patterned to form buried patterns 185 and < RTI ID = 0.0 > Semiconductor body portions 175 may be formed.

According to an embodiment of the present invention, the vertical pattern 155, the semiconductor spacer 165 and the semiconductor body portion 175 may constitute one vertical structure (VS), and on the substrate 10, , A plurality of vertical structures VS may be formed, which are two-dimensionally arranged through the mold structure 100. According to the above-described configuration, the positions at which the vertical structures VS are arranged are defined by the openings 105. Meanwhile, the embedding pattern 185 may also constitute the vertical structure VS.

11, upper plugs 260 are formed on upper portions of the vertical structures VS, and upper wires 270 connecting the upper plugs 260 are formed on upper portions of the upper plugs 260. Referring to FIG. have.

According to one embodiment, the semiconductor spacer 165 and the upper region of the semiconductor body portion 175 may have an upper impurity region (not shown). The bottom of the upper impurity region may be higher than the upper surface of the uppermost one of the horizontal structures HS. In addition, the upper impurity region may be doped with a different conductivity type than a portion of the semiconductor spacer 165 underlying it. Accordingly, the upper impurity region can form a diode and a lower region thereof. According to this embodiment, the upper plugs 260 may be one of doped silicon and metallic materials.

According to another embodiment, the upper plugs 260 may be silicon films doped with a different conductivity type than the semiconductor spacers 165 and the semiconductor body portion 175. In this case, the upper plugs 260 may form a pn junction with the semiconductor spacer 165 and the semiconductor body portion 175.

Each of the upper wirings 270 may be electrically connected to the semiconductor spacer 165 and the semiconductor body portion 175 through the upper plug 260 and may be formed to cross the horizontal structures HS. . According to an embodiment for a NAND flash memory, the upper interconnects 270 can be used as bit lines connecting to one ends of a plurality of cell strings.

[Method - 2nd Example ]

12 to 21 are perspective views for explaining a method of manufacturing a three-dimensional semiconductor device according to a second embodiment of the present invention. For the sake of brevity, the technical features of the second embodiment, which are substantially the same as the first embodiment described above, can be omitted from the following description.

Referring to FIGS. 1 and 12, openings 106 are formed through the mold structure 100. According to this embodiment, the openings 106 may include a hexahedral portion with aspect ratios of the cross-sections projected on the xy plane and the xz plane being at least 5 or greater. That is, the lengths of the openings 106 in the y and z directions may be at least five times larger than the length in the x direction.

Referring to FIG. 13, a preliminary vertical pattern 154 and a preliminary semiconductor spacer 164 which sequentially cover the inner walls of the openings 106 are formed. In this step, after forming a vertical film and a first semiconductor film which sequentially cover the inner walls of the openings 106, the first semiconductor film is anisotropically etched to form the upper surface of the substrate 10 at the bottom of the opening 106 The method comprising the steps of: As a result of the over-etch in the step of anisotropically etching the first semiconductor film, the upper surface of the substrate 10 exposed by the spare semiconductor spacers 164, as shown, have.

In the meantime, as in the previous embodiment, the vertical film may be composed of one thin film or a plurality of thin films. As will be described later in detail with reference to FIGS. 36 to 43, Thin films constituting the film can be variously classified according to what is.

Referring to FIGS. 14 and 15, a second semiconductor film 170 and a string defining mask 182 are sequentially formed on the resultant product in which the preliminary vertical pattern 154 is formed. The second semiconductor film 170 may be a polycrystalline silicon film formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques, and the string definition mask 182 may be formed using S- And a silicon oxide film.

The step of forming the string defining mask 182 may include forming a string separating film filling the openings 106 on the resultant product of the second semiconductor film 170, And patterning the string separation membrane. Patterning the string isolation layer may include anisotropically etching the string isolation layer using an etch recipe having etch selectivity for the second semiconductor layer 170. According to one embodiment, patterning the string isolation layer may be performed to expose the second semiconductor layer 170 at the bottom of the opening 106.

Each of the string defining masks 182 thus includes an upper pattern 182a that traverses an upper portion of the openings 106 and a lower portion that extends downwardly from the upper pattern 182a to partially Filling patterns 182b. The surfaces of the second semiconductor film 170 between the extended patterns 182b may be exposed. That is, the extension patterns 182b may be formed to expose the sidewalls and the bottom surface of the second semiconductor film 170 located between the extension patterns 182b.

Referring to FIG. 16, the second semiconductor film 170 and the preliminary semiconductor spacer 164 are sequentially patterned using the string definition masks 182 as an etching mask. This patterning step may include isotropically etching the second semiconductor film 170 and the preliminary semiconductor spacer 164 using an etch recipe having etch selectivity for the preliminary vertical pattern 154 .

According to one embodiment, during the patterning step, the pre-vertical patterns 154 may be etched together to expose the sidewalls of the mold structure 100. In this case, the preliminary vertical patterns 154 are horizontally separated to form two-dimensionally arranged vertical patterns 155, and the preliminary semiconductor spacers 164 are horizontally separated and arranged two-dimensionally Gt; 165 < / RTI > That is, between the string defining masks 182 and the mold structure 100, vertical patterns 155 and semiconductor spacers 165 arranged two-dimensionally on the substrate 10 are formed. In addition, as a result of the patterning process, the second semiconductor film 170 also forms horizontally separated second semiconductor patterns 174. The second semiconductor patterns 174 may include semiconductor body portions 175 interposed between the semiconductor spacers 165 and the string definition masks 182 as shown.

According to another embodiment, the second semiconductor patterns 174 are separated by the patterning process, but the preliminary vertical pattern 154 may remain on the inner wall of the openings 106. That is, the patterning process may be performed so as not to expose the side walls of the mold structure 100. FIG. 27 is a perspective view showing a part of an end result according to this modified embodiment. FIG. In the case where the vertical film is formed of a plurality of thin films, a part of the plurality of thin films constituting the vertical film or the preliminary vertical pattern 154 may remain on the inner walls of the openings 106.

17 and 18, string separating films ISO filling the openings 106 between the string defining masks 182 are formed, and then the sacrificial films 100 are formed through the mold structure 100. [ (130) and the trenches (200) exposing the sidewalls of the insulating films (120).

The string separation membranes ISO may be formed of at least one of the insulating materials. In addition, the string separating films ISO may be formed in a shape similar to the string defining masks 182. That is, each of the string separation membranes ISO has an upper separation pattern ISOa horizontally traversing the openings 106 and an extension extending downward from the upper separation pattern ISOa to fill the openings 106. [ (Not shown).

The trenches 200 may be formed to intersect the openings 105 and may be formed using the method of the first embodiment described with reference to FIG. The semiconductor bodies 175 constituting the second semiconductor pattern 174 are separated from each other by the trenches 200 and the extension patterns 182b constituting the string definition mask 182 are separated from each other Can be separated. Accordingly, the semiconductor bodies 175 may be two-dimensionally arranged on the substrate 10 similar to the vertical patterns 155 and the semiconductor spacers 165.

According to the above-described configuration, a plurality of vertical structures VS and a plurality of string separation membranes ISO disposed therebetween may be disposed in one opening 106, and each of the vertical structures VS A pair of the vertical patterns 155, and a pair of the semiconductor spacers 165, as shown in FIG. Meanwhile, the vertical structure VS may further include the extension pattern 182b.

19, after the exposed sacrificial layers 130 are selectively removed to form recessed regions 210 between the insulating films 120, as shown in FIG. 20, To form horizontal structures (HS) filling the recessed regions (210). The recessed regions 210 and the horizontal structures HS may be formed using the method of the first embodiment described with reference to FIGS. Accordingly, the horizontal structure HS may include horizontal patterns 220 covering the inner wall of the recess region 210 and a conductive pattern 230 filling the remaining space of the recess region 210 . 20, impurity regions 240 may be further formed in the substrate 10 exposed through the trenches 200 after the conductive patterns 230 are formed (see FIG. 20) .

21, the electrode separation patterns 250 filling the trenches 200, the upper plugs 260 connected to the vertical structures VS and the upper plugs 260 connected to the vertical structures VS, The upper wirings 270 are formed. The electrode separation patterns 250, the upper plugs 260, and the upper wirings 270 may be formed using the method of the first embodiment described with reference to FIGS. 10 and 11. FIG.

[3D Semiconductor Device]

Hereinafter, three-dimensional semiconductor devices according to the technical idea of the present invention will be described with reference to FIGS. 22 to 27. FIG. 22 to 27, in order to reduce the complexity in the drawings and to better understand the technical idea of the present invention, some of the elements constituting the three-dimensional semiconductor device have been intentionally omitted. It will be apparent to those skilled in the art that these omitted parts can be easily recovered from the parts shown in the drawings and the manufacturing methods described above, so that a separate description thereof will be omitted. In addition, for brevity of description, description of technical features overlapping with the above-described manufacturing methods can be omitted. However, it should be noted that the three-dimensional semiconductor device to be described herein may be manufactured through variations of the manufacturing method described above or other manufacturing methods thereof, it is necessary to have all or substantially all of the technical features described in the above- There is no.

[Structure - 1st Example  And Modifications ]

FIG. 22 is a perspective view for explaining a three-dimensional semiconductor device according to a first embodiment of the present invention, and FIGS. 23 and 24 are perspective views for explaining a three-dimensional semiconductor device according to modified first embodiments.

22, horizontal structures HS are three-dimensionally arranged on a substrate 10 and vertical structures VS vertically penetrating the horizontal structures HS are formed on the substrate 10, As shown in Fig.

Each of the horizontal structures HS includes a conductive pattern 230 and a horizontal pattern 220. The conductive pattern 230 is disposed such that its long axis is parallel to the top surface (i.e., the xy plane) of the substrate 10. [ A plurality of openings 105 penetrating the vertical structures VS are formed in the conductive pattern 230. The horizontal pattern 220 may be interposed between the conductive pattern 230 and the vertical structures VS. That is, the horizontal pattern 220 may cover the inner walls of the conductive patterns 230 or the side walls of the openings 105. In addition, according to this embodiment, the horizontal patterns 220 may extend horizontally from the openings 105 to cover the upper surface and the lower surface of the conductive pattern 230.

The conductive pattern 230 may include at least one of doped silicon, metal materials, metal nitride films, and metal silicides. For example, the conductive pattern 230 may include a tantalum nitride film or tungsten. The horizontal pattern 220 may be formed of one thin film or a plurality of thin films. According to one embodiment, the horizontal pattern 220 may include at least a blocking insulating film used as a memory element of a charge trapped nonvolatile memory transistor.

Each of the vertical structures VS includes a semiconductor pattern SP connected to the upper surface of the substrate 10 and a vertical pattern 155 interposed between the semiconductor pattern SP and the horizontal structures HS. . According to one embodiment, the semiconductor pattern SP may include a semiconductor spacer 165 and a semiconductor body portion 175. The semiconductor spacer 165 may be in the shape of a cylinder with upper and lower openings open and the semiconductor body portion 175 may cover the inner surface of the semiconductor spacer 165 and the upper surface of the substrate 10. [ It can be a cup shape. That is, the semiconductor body part 175 is formed to have a thickness that does not completely fill the opening 105, so that a pinhole 105a can be defined therein. According to this embodiment, as shown, the pinholes 105a may be filled by the buried patterns 185. [

The vertical pattern 155 may have a cylindrical shape with upper and lower openings open, and may include a bottom extending downwardly of the semiconductor spacer 165. The vertical pattern 155 extends vertically between the semiconductor pattern SP and the horizontal structures HS and is a single body that covers the entire outer wall of one semiconductor pattern SP as shown in FIG. .

According to one embodiment, the semiconductor pattern SP may be one of materials having semiconductor properties. For example, each of the semiconductor spacer 165 and the semiconductor body portion 175 may be one of polycrystalline silicon, an organic semiconductor film, and carbon nanostructures. The vertical pattern 155 may be formed of one thin film or a plurality of thin films. According to one embodiment, the vertical pattern 155 may comprise at least a tunnel insulating layer used as a memory element of a charge trapped nonvolatile memory transistor.

Meanwhile, the horizontal structures HS and the vertical structures VS include localized intersecting regions (or channel regions) between them, vertical adjacent regions vertically adjacent to the intersecting regions And horizontal adjacent regions horizontally adjacent to the crossing regions. The vertical adjacent regions may be defined as sidewalls of the vertical structure VS positioned between the horizontal structures HS and the horizontal adjacent regions are defined between the vertical structures VS, Lt; RTI ID = 0.0 > (HS). ≪ / RTI > According to an aspect of the present invention, the horizontal pattern 220 and the vertical pattern 155 are disposed in the intersecting areas, and the horizontal pattern 220 extends to the horizontal adjacent areas, 155 extend to the vertical adjacent regions.

Referring to FIG. 23, the semiconductor body portion 175 may be formed to substantially completely fill the opening 105 in which the semiconductor spacer 165 is formed. According to one embodiment, voids may be formed in the semiconductor body portion 175.

On the other hand, the semiconductor body portion 175 or the semiconductor spacer 165 may be formed of a polycrystalline silicon (e.g., silicon carbide) formed through chemical vapor deposition by experiencing a crystal structure altering step (for example, an epitaxial technique including a laser annealing step) And may have a crystal structure different from that of the crystal structure. For example, the semiconductor body portion 175 or the semiconductor spacer 165 may be formed such that the lower region thereof and the upper region thereof have different grain sizes. The semiconductor body portion 175 or the semiconductor spacer 165 according to the above-described or later embodiments may have the same technical characteristics as those related to the crystal structure.

Referring to FIG. 24, the length of the vertical pattern 155 may be shorter than the length of the semiconductor spacer 165. That is, an under-cut region 77 defining a bottom surface of the vertical pattern 155 may be formed under the semiconductor spacer 165. This structure can be obtained by isotropically etching the lower region of the vertical pattern 155 using the semiconductor spacer 165 as an etch mask, as described above with reference to FIG. The undercut region 77 may be filled with the semiconductor body portion 175. Vertical structures VS according to embodiments described above or below may have the same technical features as those associated with the undercut region.

[Structure - 2nd Example  And Modifications ]

FIG. 25 is a perspective view for explaining a three-dimensional semiconductor device according to a second embodiment of the present invention, and FIGS. 26 and 27 are perspective views for explaining a three-dimensional semiconductor device according to modified second embodiments. For the sake of brevity, description of the technical features overlapping with the three-dimensional semiconductor device according to the first embodiment described with reference to FIGS. 22 to 24 can be omitted.

Referring to FIG. 25, horizontal structures HS are arranged three-dimensionally on a substrate 10, and vertical structures VS are arranged between the horizontal structures HS. The vertical structures VS are two-dimensionally arranged on the substrate 10 and arranged to face sidewalls of the horizontal structures HS.

Each of the horizontal structures HS includes a conductive pattern 230 and a horizontal pattern 220. The conductive pattern 230 may be formed in a line shape whose long axis is parallel to the upper surface of the substrate 10. The horizontal pattern 220 is interposed between the conductive patterns 230 and the vertical structures VS and may extend horizontally to cover the upper and lower surfaces of the conductive patterns 230. However, one side wall of the conductive pattern 230 spaced from the vertical structure VS may not be covered by the horizontal pattern 220. That is, the cross-section of the horizontal pattern 220 projected on the xz plane may be a "C" or "U" shape.

Each of the vertical structures VS includes a semiconductor pattern SP connected to the upper surface of the substrate 10 and a vertical pattern 155 interposed between the semiconductor pattern SP and the horizontal structures HS. . According to one embodiment, one semiconductor pattern SP constituting one vertical structure VS includes a pair of semiconductor spacers 165 and one semiconductor body portion 175 disposed therebetween .

The semiconductor body portion 175 may include a pair of sidewall portions vertically crossing the horizontal structures HS and a bottom portion connecting the bottom surfaces of the sidewall portions. That is, the semiconductor body portion 175 may include a horseshoe-shaped portion. Each of the semiconductor spacers 165 may include a hexahedral portion interposed between the side wall portion of the semiconductor body portion 175 and the vertical pattern 155. The thicknesses of the side walls of the semiconductor body portion 175 and the semiconductor spacers 165 in the x direction may be smaller than the interval between the pair of adjacent conductive patterns 230. Between the side wall portions of the semiconductor body portion 175, an extension pattern 182b of the string defining mask 182 can be disposed, as shown in Fig.

The vertical pattern 155 may have a hexahedral shape, but its thickness in the x direction may be smaller than the gap between the pair of horizontally adjacent conductive patterns 230. That is, the vertical pattern 155 may be in the form of an elongated plate. In addition, the vertical pattern 155 may further include a bottom portion that extends downwardly of the semiconductor spacer 165 and may extend vertically and continuously, as shown, to define the entire one side wall of the semiconductor spacer 165 .

Referring to FIGS. 26 and 27, the semiconductor body portion 175 may be formed to substantially completely fill the opening 105 in which the semiconductor spacer 165 is formed. According to one embodiment, a discontinuous interface 179 or void may be formed within the semiconductor body portion 175. On the other hand, as described with reference to FIG. 23, the semiconductor body portion 175 or the semiconductor spacer 165 can be formed by experiencing a crystal structure changing step (for example, an epitaxial technique including a laser annealing step) And may have a different crystal structure than polycrystalline silicon formed through chemical vapor deposition.

Referring to FIG. 27, the vertical pattern 155 may include a horizontally extending horizontal extension 155e, as described with reference to FIG. That is, the horizontal extending portion 155e may be disposed between the semiconductor bodies 175 horizontally adjacent to each other and may contact the side wall of the string separation membrane ISO.

36 to 43, the vertical patterns 155 are formed on the tunnel insulating film TIL and the charge storage film CL, according to embodiments of the charge trap type nonvolatile memory device, And may further include a capping layer (CPL) as shown in the figure. According to some of these embodiments, the horizontal extension 155e may include both the tunnel insulating film TIL and the charge storage film CL. 27, the horizontal extension 155e includes only the capping layer (CPL), and the charge storage layer (CL) and the tunnel insulation layer (TIL) Can be horizontally separated by the string separation membrane (ISO). This separation can be realized through the manufacturing method described with reference to Fig.

[ Information storage film ]

When the technical idea of the present invention is used to implement a charge trap type nonvolatile memory device, the horizontal pattern 220 and the vertical pattern 155 in the above embodiments constitute an information storage film of a memory cell transistor . In this case, the number and kinds of thin films constituting each of the horizontal and vertical patterns 220 and 155 may vary, and the technical idea of the present invention can be subdivided into various embodiments based on this variety. For example, embodiments of the present invention relating to an information storage film can be classified as shown in Table 1 below.

Information storage film Corresponding drawing VS HS SP TIL CL CPL BIL1 230 28/36 ^[1] SP TIL CL BIL1 230 29/37 SP TIL CL BIL1 230 30/38 SP TIL CL BIL1 BIL2 230 31/39 SP TIL CL BIL1 BIL2 230 32/40 SP TIL CL CPL BIL1 230 33/41 ^[2] SP TIL CL CPL BIL1 230 34/42 ^[3] SP TIL CL CPL BIL1 BIL2 230 35/43 TIL: Tunnel Insulating Layer BIL: Blocking Insulating Layer
CL: Charge storing layer CPL: CaPping Layer
[1]: For CPL with uniform thickness
[2]: For CPL with recessed sidewalls
[3]: For vertically separated CPLs

When the technical idea of the present invention is used to implement a flash memory, as shown in Tables 1 and 28 to 43, the information storage film includes a tunnel insulating film TIL, a charge storage film CL and a first blocking insulating film BIL1 ). According to some embodiments, the information storage layer may further include a second blocking insulating layer BIL2 disposed between the first blocking insulating layer BIL1 and the conductive pattern 230. [ In addition, the information storage layer may further include a capping layer (CPL) interposed between the charge storage layer (CL) and the first blocking insulating layer (BIL1). The films constituting the information storage film may be formed using a deposition technique (for example, chemical vapor deposition or atomic layer deposition technique) capable of providing excellent step coverage.

As shown in Table 1 and FIGS. 28 to 43, the vertical structure VS includes at least a tunnel insulating film TIL, and the horizontal structure HS includes the first and second blocking insulating films BIL1 and BIL2 ). At this time, according to some embodiments, as shown in FIGS. 28, 29, 31, 33-37, 39 and 41-43, the vertical structure VS may include the charge storage film CL. Further, according to other embodiments, as shown in FIGS. 30, 32, 38 and 40, the horizontal structure HS may include the charge storage film CL.

When the vertical structure VS includes the charge storage film CL, as shown in FIGS. 28, 33-36 and 41-43, the vertical structure VS further includes the capping layer CP can do. However, as shown in FIGS. 29, 31, 37 and 39, the vertical structure VS and the horizontal structure HS may be in direct contact without the capping layer CPL.

Meanwhile, the thickness of the sidewall of the capping layer (CPL) may be uneven. For example, while forming the recessed regions 210, the sidewalls of the capping layer CPL adjacent to the horizontal structure HS may be horizontally recessed. 33 and 41, the thickness of the capping layer CPL is greater than that between the horizontal structures HS in a region (a) (or a channel region) adjacent to the horizontal structure HS, In the region b (or vertically adjacent region). Alternatively, as shown in FIGS. 34 and 42, the capping layer (CPL) locally remains in the vertical adjacent region (b), and the horizontal structure (HS) It can directly contact the side wall of the film CL. However, as exemplarily shown in Figs. 28 and 36, the thickness of the sidewall of the capping layer CPL may be substantially uniform.

According to some embodiments of the present invention, as shown in FIGS. 31, 32, 35, 39, 40, and 43, the horizontal structure HS may include both the first and second blocking insulating films BIL1 and BIL2 .

On the other hand, in the kind of material and the forming method, the charge storage film CL may be one of insulating films including trapping sites and abundant insulating films and nanoparticles, and one of chemical vapor deposition or atomic layer deposition techniques . ≪ / RTI > For example, the charge storage film CL may include one of a trap insulating film, a floating gate electrode, or an insulating film including conductive nano dots. More specifically, the charge storage layer (CL) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a laminated trap layer One can be included.

The tunnel insulating film TIL may be one of materials having a bandgap larger than that of the charge storage film CL and may be formed using one of chemical vapor deposition or atomic layer deposition techniques. For example, the tunnel insulating film TIL may be a silicon oxide film formed using one of the deposition techniques described above. In addition, the tunnel insulating layer (TIL) may further experience a predetermined heat treatment step performed after the deposition process. The heat treatment step may be an annealing process performed in an atmosphere containing Rapid Thermal Nitridation (RTN) or at least one of nitrogen and oxygen.

The first and second blocking insulating layers BIL1 and BIL2 may be formed of different materials. One of the first and second blocking insulating layers BIL1 and BIL2 may be smaller than the tunnel insulating layer TIL, It may be one of materials having a band gap larger than the charge storage film CL. In addition, the first and second blocking insulating films BIL1 and BIL2 may be formed using one of chemical vapor deposition or atomic layer deposition techniques, and at least one of them may be formed through a wet oxidation process . According to one embodiment, the first blocking insulating layer BIL1 is one of high-k films such as an aluminum oxide layer and a hafnium oxide layer, and the second blocking insulating layer BIL2 has a dielectric constant smaller than that of the first blocking insulating layer BIL1. Lt; / RTI > According to another embodiment, the second blocking insulating film BIL2 may be one of the high-k films, and the first blocking insulating film BIL1 may be a material having a smaller dielectric constant than the second blocking insulating film BIL2. According to a modified embodiment, in addition to the first and second blocking insulating films BIL1 and BIL2, at least one additional blocking insulating film (not shown) interposed between the charge storage film CL and the conductive pattern 230 May be further formed.

The capping layer CPL may be a material capable of providing etch selectivity to the charge storage layer CL or the sacrificial layer 130. For example, when the sacrificial layer 130 is a silicon nitride layer, the capping layer CPL may be a silicon oxide layer. In this case, in the process of removing the sacrificial layer 130 to form the recessed regions 210, the capping layer CPL may be an etch stop layer to prevent etching damage of the charge storage layer CL Function. On the other hand, when the capping layer CPL remains between the conductive pattern 230 and the charge storage layer CL as shown in FIGS. 28, 33, 35, 36, 41 and 43, CPL may be formed of a material that can contribute to preventing leakage of charge stored in the charge storage film CL (e.g., back-tunneling). For example, the capping layer (CPL) may be one of a silicon oxide layer and a high-k dielectric layer.

[Modified Examples ]

44 to 46 are sectional views for explaining the three-dimensional semiconductor devices according to the modified embodiments.

44 to 46, at least one upper select line USL may be formed between the upper wiring 270 and the horizontal structures HS. The upper select line USL may be used as a gate electrode of the upper select transistor for controlling the flow of current through the upper wiring 270 and the semiconductor pattern SP. The upper select transistor may be a MOS field effect transistor. In this case, a top gate insulating layer UGI may be interposed between the upper select line USL and the semiconductor pattern SP, as shown in FIG. The upper select line USL may be arranged in a direction intersecting the upper wiring 270 (for example, in a direction parallel to the horizontal structure HS or the conductive pattern 230) .

According to some embodiments, the upper select line USL may be formed using a different process than the conductive pattern 230 forming the horizontal structure HS. According to some other embodiments, the upper select line USL and the conductive pattern 230 may be formed using substantially the same material by being formed using the same process.

Also, according to some embodiments, the upper gate insulating layer UGI is formed using the same process as one of the horizontal pattern 220 and the vertical pattern 155, so that substantially the same material and the same . Alternatively, the upper gate insulating layer UGI may include a thin film constituting one of the horizontal pattern 220 and the vertical pattern 155. According to another embodiment, the upper gate insulating layer UGI may be formed independently of the horizontal pattern 220 and the vertical pattern 155 through a manufacturing process.

45 and 46, an upper semiconductor pattern USP may be interposed between the upper wiring 270 and the semiconductor pattern SP, and the upper select line USL may be formed between the upper semiconductor pattern SP USP). ≪ / RTI > According to one embodiment, the upper semiconductor pattern USP may be of the same conductivity type as the semiconductor pattern SP. In addition, a pad (PAD) may be further formed between the upper semiconductor pattern USP and the upper plug 260.

As shown in FIG. 46, at least one lower select line LSL may be formed between the substrate 10 and the horizontal structures HS. A lower semiconductor pattern LSP may be interposed between the substrate 10 and the semiconductor pattern SP and the lower select line LSL may be formed around the lower semiconductor pattern LSP. The lower selection line LSL may be used as a gate electrode of the lower selection transistor for controlling the flow of current through the impurity region 240 and the semiconductor pattern SP. A lower gate insulating layer LGI may be interposed between the lower select line LSL and the lower semiconductor pattern LSP.

47 and 48 are perspective views for explaining three-dimensional semiconductor devices according to other modified embodiments. Figs. 47 and 48 are perspective views for explaining variations of the three-dimensional semiconductor devices described with reference to Figs. 22 and 25, respectively.

Referring to FIGS. 47 and 48, a metal pattern 255 connected to the impurity region 240 may be formed in the trench 200. In addition, trench spacers 245 may be further formed on the sidewalls of the trenches 200 for electrical separation between the metal patterns 255 and the conductive patterns 230.

The metal pattern 255 may be formed of a metallic material such as tungsten and a barrier metal film may be formed between the impurity region 240 and the metal pattern 255. For example, ) Or a silicide film (not shown) may be further formed. The trench spacers 245 may be one of the insulating materials (e.g., a silicon oxide film).

The metal pattern 255 and the trench spacer 245 may be formed after the step of forming the impurity region 240 described with reference to FIG. 9 or 20. More specifically, the trench spacer 245 may be formed by exposing an upper surface of the impurity regions 240 by anisotropically etching an insulating film covering the inner wall of the trench 200 in a conformal manner. In addition, the metal pattern 255 may be formed by filling the trench 200 formed with the trench spacer 245 with a metal film, and then planarizing and etching the trench.

The metal pattern 255 and the trench spacer 245 may be formed to horizontally cross the semiconductor patterns SP as well as penetrate the conductive patterns 230 vertically. According to one embodiment, the thickness (i.e., z-direction length) and length (i.e., y-direction length) of the metal pattern 255 may be substantially the same as those of the trench 200.

Since the metal pattern 255 has a specific resistance lower than that of the impurity region 240 and is connected to the impurity region 240, the metal pattern 255 can contribute to improve the transfer speed of an electrical signal via the impurity regions 240 have. In addition, since the upper surface of the metal pattern 255 is located higher than the upper surface of the uppermost layer of the conductive patterns 230, the technical difficulty in the wiring formation process for the electrical connection to the impurity region 240 is reduced. . In addition, since the metal pattern 240 can function as a shielding layer between the conductive patterns 230, it is possible to reduce the capacitive coupling between the adjacent conductive patterns 230 . As a result, disturbance problems in the program and read operations can be alleviated.

[ Comparative Examples ]

49 and 50 are perspective views for explaining the three-dimensional semiconductor devices according to the comparative examples.

The punch-and-plug technique can be used to implement a flash memory device three-dimensionally, including a charge storage film as a memory element. In this case, the punch-and-plug technique is divided into a storage-first way and a plug-first way according to the formation order between the films for storing information and the semiconductor plug used as an active region ). 49 and 50 show cross-sectional views of a three-dimensional NAND flash memory device to which a storage priority scheme and a plug priority scheme are applied, respectively.

49, the tunnel insulating film TIL, the charge storage film CL, and the blocking insulating film BLL used as memory elements are all formed so as to cover the inner wall of the opening 105 in the storage priority mode. 50, the tunnel insulating film TIL, the charge storage film CL, and the blocking insulating film BLL used as the memory element are all formed on the surface of the conductive pattern 230 Respectively.

According to the storage priority scheme, the step of forming the opening 105 is performed after the step of depositing the word line WL. In this case, due to the difficulty in the process of forming the openings 105, the word line WL according to the storage preference mode is formed of doped polycrystalline silicon having a relatively high resistivity as compared with metal. According to embodiments of the present invention, as described with reference to FIG. 9 or 20, the word line WL (i.e., the conductive pattern 230) is formed after forming the opening 105 . Accordingly, in the embodiments of the present invention, the conductive pattern 230 may be formed of a metallic material without being constrained by the constraint in the storage priority scheme.

According to the plug-first method, after the recessed regions 210 are formed between the insulating films 120, the memory elements and the films constituting the conductive pattern 230 are formed in the recessed regions 210, And deposited on the inner wall in turn. 50, all the films constituting the memory element (i.e., the tunnel insulating film TIL, the charge storage film CL, and the blocking insulating film BLL) are formed in the recessed regions 210 The thickness t2 of the conductive pattern 230 is smaller than the thickness t1 of the recessed region 210. [ This reduction in thickness may cause technical problems such as an increase in the vertical distance between the conductive patterns 230 or an increase in the resistance of the conductive pattern 230, and these problems may be exacerbated with an increase in the degree of integration. Alternatively, in accordance with embodiments of the present invention, a portion of the films constituting the memory element (i.e., the horizontal pattern 220) fill the recessed regions 210, Technical problems can be suppressed.

[ Undercut  Methods of forming regions and structures therefor]

A three-dimensional semiconductor device in which the undercut region 77 defines the bottom surface of the vertical pattern 155 has been exemplarily described with reference to Fig. Hereinafter, embodiments of the present invention relating to methods of forming the undercut region 77 and structures of the three-dimensional semiconductor device according to the present invention will be described.

On the other hand, the method of forming the undercut region 77 to be described below and the structure therefor is not limited to the structure exemplarily shown in FIG. 24, but may be applied to the three-dimensional semiconductor devices or their modifications Can be applied. Nevertheless, those of ordinary skill in the art will appreciate that, in view of the ease of application of the technical ideas associated with the undercut region 77, which will be described below for an extended implementation of the previously described embodiments, Descriptions for such an extended implementation are omitted. In addition, each of the manufacturing methods described below can be applied in place of the steps of the manufacturing method described with reference to Figs. 3 to 6 or 13 and 14, and other steps except for the above- May be performed based on subsequent steps (e.g., the steps described with reference to Figures 7-11 or 15-21) or variations thereof.

Figs. 51 to 64 are cross-sectional views showing specific embodiments for forming the undercut region 77 described with reference to Fig. More specifically, Figs. 51 to 54 show a first embodiment for forming the undercut region 77, Figs. 55 and 56 show a second embodiment for forming the undercut region 77, Figs. 57 to 62 show a third embodiment for forming the undercut region 77, and Fig. 63 and Fig. 64 show a fourth embodiment for forming the undercut region 77. Fig. For the sake of brevity of description, in the descriptions of the second to fourth embodiments, description of the technical features overlapping with the first embodiment may be omitted.

51, a mold structure 100 including an insulating layer 121 and a sacrificial layer 131 is formed on a substrate 10, and the upper part of the substrate 10 is penetrated through the mold structure 100, A vertical film 150 and a first semiconductor film 160 are sequentially formed on the inner wall of the opening 105. [

The mold structure 100 may be substantially the same as that of the embodiment described with reference to Fig. That is, the illustrated insulating layer 121 and the sacrificial layer 131 illustrate a part of the mold structure 100, and the mold structure 100 may include more insulating layers and sacrificial layers .

The opening 105 may have a hole shape as shown in FIG. 2 or may be formed to include a hexahedral portion as shown in FIG. According to this embodiment, during formation of the opening 105, the upper surface of the substrate 10 may be recessed to a predetermined depth. In this case, the bottom surface of the opening 105 may be lower than the top surface of the substrate 10 on which the bottom surface of the insulating film 121 contacts. This recess of the substrate 10 may be the result of over-etching that may be required for stable formation of the opening 105. In addition, this recess of the substrate 10 may be intentionally implemented since it may contribute to improving the structural stability of the vertical pattern 155.

The vertical film 150 and the first semiconductor film 160 may be formed to substantially conformally cover the sidewalls and the bottom surface of the opening 105. The sum of the deposition thicknesses of the vertical film 150 and the first semiconductor film 160 may be less than half the width of the opening 105. [ That is, the opening 105 may not be completely filled with the vertical film 150 and the first semiconductor film 160.

The vertical film 150 and the first semiconductor film 160 may be formed to constitute the vertical structure VS disclosed in any one of the embodiments described with reference to FIGS. For example, the vertical film 150 may include a capping layer (CPL), a charge storage layer (CL), and a tunnel insulating layer (TIL), which are sequentially deposited as shown in FIG. 51. May be substantially the same as in the embodiment described with reference to Figs. In addition, the first semiconductor layer 160 may be a polycrystalline silicon layer.

Referring to FIG. 52, the first semiconductor layer 160 and the vertical layer 150 are anisotropically etched to expose the upper surface of the substrate 10 at the bottom of the opening 105, dent PD. The step of forming the penetration grooves PD may be performed by a method of plasma dry etching using the mold structure 100 as an etch mask, as described with reference to FIG.

As a result of the anisotropic etching on the first semiconductor film 160, a semiconductor spacer SP is formed to cover the inner wall of the vertical pattern 155. The penetration groove PD is formed to penetrate the vertical film 150 covering the bottom surface of the opening 105 so that the vertical pattern 150 having sidewalls exposed by the through- 155 are formed. 51, the capping layer CPL, the charge storage layer CL, and the tunnel insulating layer TIL are formed so as to penetrate through the opening 105 in the vicinity of the bottom of the opening 105. In other words, in the embodiment having the thin film structure described with reference to FIG. And has sidewalls exposed by the grooves PD.

Referring to FIG. 53, the exposed charge storage layer CL is isotropically etched to form a first undercut region UC1. The first undercut region UC1 may be a gap region extending from the penetration groove PD and is formed to partially expose the surfaces of the capping layer CPL and the tunnel insulating layer TIL.

According to some embodiments, the charge storage film CL may be a silicon nitride film. In this case, the first undercut region UC1 may be formed through a wet etching process using an etchant containing phosphoric acid. However, according to other embodiments, the first undercut UC1 may be formed through a method of isotropic dry etching.

Referring to FIG. 54, a second undercut region is formed by isotropically etching the capping layer CPL and the tunnel insulating layer TIL exposed by the first undercut region UC1. The second undercut region is formed by a portion of the surface of the substrate 10 defining the opening 105 and a portion of the surface of the semiconductor spacer SP which are covered by the capping layer CPL and the tunneling insulating layer TIL, The bottom and bottom surfaces of the outer wall are exposed, and the undercut region 77 can be formed together with the first undercut region UC1.

The step of forming the second undercut region may be performed using at least one of wet etching or isotropic dry etching methods. In the case of the wet etching method, an etching solution containing hydrofluoric acid or sulfuric acid may be used.

Next, a second semiconductor film 170 is formed in the undercut region 77 to connect the substrate 10 and the semiconductor spacer SP. The second semiconductor film 170 may be a semiconductor material (e.g., polycrystalline silicon) formed using one of the deposition techniques. In this case, as shown, the second semiconductor film 170 may extend from the undercut region 77 to cover the inner wall of the semiconductor spacer SP. In addition, as a result of this deposition process, the second semiconductor film 170 may have a seam 88 in the undercut region 77.

According to the second embodiment of forming the undercut region 77, the step of forming the first undercut region UC1 described with reference to FIG. 53 is the same as the step of forming the undercut region 77, And may include isotropically etching the tunnel insulating film (TIL). The capping layer CPL and the tunneling insulation layer TIL may be formed using at least one of wet etching or isotropic dry etching methods. In the case of the wet etching method, an etching solution containing hydrofluoric acid or sulfuric acid may be used.

56, the bottom surface of the charge storage film CL may be further extended from the bottom surface of the opening 105 than the bottom surface of at least one of the capping layer CPL and the tunnel insulating layer TIL. It can be far apart. 53, when the charge storage layer CL is etched first, at least one bottom surface of the capping layer CPL and the tunnel insulating layer TIL is etched by the charge storage layer May be further away from the bottom surface of the opening 105 than the bottom surface of the membrane CL.

According to the third embodiment of forming the undercut region 77, as shown in FIG. 57, after forming the first semiconductor film 160, a protective film spacer PS is formed in the opening 105 More steps can be carried out. The protective film spacer PS may be formed of a material having etching selectivity with respect to the first semiconductor film 160. According to some embodiments, the passivation spacer (PS) may be a silicon oxide film or a silicon nitride film formed using atomic layer deposition techniques. In addition, the protective film spacer PS is formed to have a thickness thinner than half of the difference between the half of the width of the opening 105 and the deposition thickness of the vertical film 150 and the first semiconductor film 160 . That is, the opening 105 may not be completely filled with the protective film spacer PS.

Thereafter, a through-hole (PD) penetrating a part of the thin films constituting the vertical film (150) is formed. For example, as shown in Fig. 58, the penetration groove PD may be formed so that the capping layer CPL remains under the penetration groove PD. 59, the semiconductor spacer SP exposed by the penetration groove PD is isotropically etched to form an extended undercut region UC0. As shown in FIGS. 61 and 62, The vertical film 150 is isotropically etched to complete the undercut region 77. Although Figs. 61 and 62 illustratively illustrate an embodiment to which the method described with reference to Fig. 53 is applied, the undercut region 77 is formed by the first and second embodiments May be formed using manufacturing methods according to one of the examples. In addition, the passivation spacer (PS) may be removed while the vertical film 150 is isotropically etched. For example, when the protective film spacer PS is formed of a silicon nitride film, it can be removed in the step of etching the charge storage film CL described with reference to FIG. Alternatively, when the protective film spacer PS is formed of a silicon oxide film, the tunnel insulating film TIL and the capping film CPL described with reference to FIG. 54 may be removed.

On the other hand, the height difference between the vertical pattern 155 and the bottom surfaces of the semiconductor spacer SP by the extended undercut region UC0 is substantially the same as the height difference between the first and second Can be reduced than that of the embodiments. That is, as shown in Fig. 62, the undercut region 77 can be expanded more than that of the first and second embodiments described with reference to Figs. 54 and 56. [ This extension of the undercut region 77 may make it easier for the second semiconductor film 170 to conformally cover the inner wall of the undercut region 77. In addition, voids 89 that are not completely filled with the second semiconductor film 170 can be formed in the undercut region 77 by the extension of the undercut region 77.

According to the fourth embodiment of forming the undercut region 77, the penetration groove PD may be formed to expose the upper surface of the substrate 10 through the vertical film 150. 63, the upper surface of the substrate 10 exposed by the penetrating grooves PD is etched together while forming the extended undercut region UC0, so that the vertical pattern 155 An extended through groove PDe can be formed. The cavity 89 may be formed in the second semiconductor film 170 and the cavity 89 may be formed in the upper cavity 89a formed in the undercut region 77. [ And a lower void 89b formed in the extended through-hole PDe. According to alternative embodiments, the voids 89 may be completely or partially filled with an insulating material (e.g., a silicon oxide film).

According to the modified embodiments, after the second semiconductor film 170 is formed, a recrystallization process for the semiconductor spacer SP and the second semiconductor film 170 may be further performed. The density of crystal defects in the semiconductor spacer (SP) and the second semiconductor film (170) can be reduced by the recrystallization process. For example, when the semiconductor spacer SP and the second semiconductor film 170 are formed of polycrystalline silicon, the recrystallization process can increase their grain size or unite their crystal structure . The recrystallization process may be performed using at least one of thermal processing techniques, laser annealing techniques, and epitaxial techniques. Nevertheless, when the substrate 10 is a single crystal wafer, on average, the substrate 10 may have fewer crystal defects than the semiconductor spacer SP and the second semiconductor film 170.

65 and 66 are cross-sectional views for explaining and comparing three-dimensional semiconductor devices according to embodiments of the present invention. More specifically, Figs. 65 and 66 show the current path in the three-dimensional semiconductor device described with reference to Figs. 1 to 21 and the three-dimensional semiconductor device described with reference to Figs.

As shown in FIG. 65, in the case of the three-dimensional semiconductor device described with reference to FIGS. 1 to 21, because of the presence of the vertical pattern 155 inserted at a predetermined depth in the upper surface of the substrate 10, The current path P1 via the impurity region 240 becomes long. In addition, in order to complete the current path P1, it is required that an inversion region is created in the substrate 10, but the vertical pattern 155 hinders the generation of the inversion region. In particular, the resistance of the inversion region increases exponentially as the straight line distance from the lowermost conductive line 230 increases, in that the inversion region is formed by the voltage applied to the lowermost conductive line 230. According to the inventors' simulation, when the depth of the vertical pattern 155 inserted into the substrate 10 increased from 0 nm to 70 nm, the resistance increased 1010 times.

66, since the second semiconductor film 170 or the semiconductor body portion 175 can be formed adjacent to the lowermost conductive line 230 by the undercut region 77, The current path P2 can be implemented adjacent to the lowermost conductive line 230 as compared to the current path P1 shown in Fig. Thus, according to this embodiment, the lengthening of the current path as in the current path Pl and the exponential increase of the electrical resistance can be prevented.

67 is a block diagram briefly showing an example of a memory card 1200 having a flash memory device according to the present invention. Referring to FIG. 67, a memory card 1200 for supporting a high capacity data storage capability mounts a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

According to the above flash memory device and memory card or memory system of the present invention, it is possible to provide a reliable memory system through the flash memory device 1210 with the erase characteristics of the dummy cells improved. In particular, the flash memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) device which is actively in progress. In this case, a reliable memory system can be realized by blocking read errors caused by the dummy cells.

68 is a simplified block diagram illustrating an information processing system 1300 for mounting a flash memory system 1310 in accordance with the present invention. 68, the flash memory system 1310 of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, a user interface 1350, . The flash memory system 1310 will be configured substantially the same as the memory system or flash memory system mentioned above. The flash memory system 1310 stores data processed by the central processing unit 1330 or externally input data. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention can be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. It is clear to those who have learned.

Further, the flash memory device or memory system according to the present invention can be mounted in various types of packages. For example, the flash memory device or the memory system according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

100 Mold structure 105/106 opening
120 insulating film 130 sacrificial film
155 Vertical Pattern 165 Semiconductor Spacer
175 Semiconductor body part 185 Embedding pattern
200 Trench 220 Horizontal pattern
230 conductive pattern 240 impurity region
BIL1 / 2 blocking insulating film CPL capping film
CL charge storage film HS horizontal structure
SP semiconductor pattern TIL tunnel insulating film
VS vertical structure 255 metal pattern

Claims (10)

Forming a mold structure on a substrate;
Forming an opening through the mold structure to recess the upper surface of the substrate to a predetermined depth;
Forming a vertical film covering the inner wall of the opening and a first semiconductor film in order;
Forming a through-hole through the first semiconductor film and the vertical film at the bottom of the opening to expose the upper surface of the substrate again;
Forming an undercut region exposing a side wall of the substrate recessed by the opening by isotropically etching the vertical film exposed through the through hole; And
And forming a second semiconductor film in the undercut region to connect the substrate and the first semiconductor film. The method according to claim 1,
Wherein the vertical film and the first semiconductor film are formed so as to sequentially cover the inner wall of the opening portion with a uniform thickness and the sum of the deposition thicknesses of the vertical film and the first semiconductor film is smaller than half the width of the opening,
The step of forming the through-
Anisotropically etching the first semiconductor film to form a semiconductor spacer exposing an upper surface of the vertical film at the bottom of the opening; And
And anisotropically etching the vertical film exposed by the semiconductor spacer. The method of claim 2,
The step of forming the penetration groove may further include forming a protective film spacer exposing a bottom surface of the first semiconductor film on an inner wall of the first semiconductor film before anisotropically etching the first semiconductor film,
The protective film spacer is formed of a material having etching selectivity with respect to the first semiconductor film and is formed to have a thickness thinner than half of a difference between half of the width of the opening and the sum of the vertical film and the deposition thickness of the first semiconductor film A method of manufacturing a three-dimensional semiconductor device. The method of claim 3,
Further comprising the step of isotropically etching the first semiconductor film using the protective film spacer as an etching mask before forming the undercut region. The method of claim 3,
Wherein the protective film spacer is removed during the step of forming the undercut region. The method according to claim 1,
Wherein the vertical film includes a capping film, a charge storage film, and a tunnel film that sequentially cover an inner wall of the opening,
The step of forming the undercut region
Forming a first undercut region exposing the capping film and the tunnel film by isotropically etching the charge storage film exposed by the penetration groove; And
And forming a second undercut region by isotropically etching the capping film and the tunnel film exposed by the first undercut region. The method according to claim 1,
Wherein the vertical film includes a capping film, a charge storage film, and a tunnel film that sequentially cover an inner wall of the opening,
The step of forming the undercut region
Forming a first undercut region exposing the charge storage film by isotropically etching the tunnel film and the capping film exposed by the through hole; And
And forming a second undercut region by isotropically etching the charge storage film exposed by the first undercut region. A conductive structure including conductive patterns sequentially stacked on a substrate;
A semiconductor pattern perpendicular to the substrate, the semiconductor pattern penetrating through the conductive structure and being inserted into an upper surface of the substrate; And
And an insulating film structure which is perpendicular to the substrate and interposed between the semiconductor pattern and the conductive structure,
Wherein a part of the semiconductor pattern covers the bottom surface of the insulating film structure and is in direct contact with the substrate. The method of claim 8,
Wherein the substrate comprises a semiconductor material having crystal defects less than the semiconductor pattern. The method of claim 8,
Wherein the semiconductor pattern includes a semiconductor spacer covering an inner wall of the insulating film structure and a semiconductor body covering an inner wall of the semiconductor spacer,
Wherein a bottom surface of the semiconductor spacer is inserted deeper into the substrate than a bottom surface of the insulating film structure and the semiconductor body portion horizontally extends under the insulating film structure to directly contact the side wall of the substrate.

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