KR101639524B1

KR101639524B1 - Multi-layer capacitor, method of manufacturing the multi-layer capacitor and capacitor package including the multi-layer capacitor

Info

Publication number: KR101639524B1
Application number: KR1020150068663A
Authority: KR
Inventors: 서수정; 김태유; 나영일; 박정갑; 박정호; 박화선; 백승빈; 송영일; 신진하; 안병욱; 윤숙영; 이정우; 조영래; 홍두표
Original assignee: 성균관대학교산학협력단
Priority date: 2015-05-18
Filing date: 2015-05-18
Publication date: 2016-07-13

Abstract

The purpose of the present invention is to provide a stacked capacitor, in which a voltage is stably provided from the outside while a maximum area of capacitor electrodes is secured, and capacitor efficiency is improved by maximizing a stacked structure of an electrode and a dielectric layer. The present invention relates to the stacked capacitor, a method of manufacturing the stacked capacitor, and a capacitor package including the stacked capacitor. The stacked capacitor comprises: a base metal layer; a first surface dielectric layer which is formed on an upper surface of the base metal layer; a second surface dielectric layer which is formed on a lower surface of the base metal layer; at least two upper capacitor electrodes which are sequentially stacked on the first surface dielectric layer and have the same area that is less than an area of the first surface dielectric layer; upper dielectric layers which are formed between the upper capacitor electrodes, respectively; upper connection electrodes which are respectively connected to the upper capacitor electrodes and are respectively disposed on one side of each of the upper capacitor electrodes; at least two lower capacitor electrodes which are sequentially stacked on a surface opposed to one surface of the second surface dielectric layer in contact with the base metal layer and have the same area that is less than an area of the second surface dielectric layer; and lower dielectric layers which are formed between the lower capacitor electrodes, respectively; and lower connection electrodes which are respectively connected to the lower capacitor electrodes and are respectively disposed on one side of each of the lower capacitor electrodes.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multilayer capacitor, a method of manufacturing the same, and a capacitor package including the same. 2. Description of the Related Art Multi-

The present invention relates to a laminated capacitor, a method of manufacturing the same, and a capacitor package including the laminated capacitor. More particularly, the present invention relates to a laminated capacitor having a high and highly stable capacitor structure, a method of manufacturing the same, and a capacitor package including the laminated capacitor.

The capacitor is a basic structure and includes two electrodes and a dielectric layer interposed therebetween. When a voltage is applied to the capacitor, an electric attraction is generated by the positive charge induced in the positive electrode and the induced electrons in the negative electrode, so that electrons and positive charges accumulate and energy is stored. In recent years, a laminated capacitor including at least three electrodes and a plurality of dielectric layers sandwiched between at least three electrodes is widely used due to the demand for miniaturization, high power, and the like.

In the laminated capacitor, electrodes are connected in parallel to apply a voltage. For this purpose, it is necessary to reduce the area of the electrode gradually as the distance from the silicon substrate is increased with respect to the lower electrode formed on the silicon substrate. That is, the area of the upper electrode located farthest from the lower electrode is smaller than the area of the lower electrode, and the efficiency of the stacked capacitor is lowered due to the reduction of the electrode area. In this structure, when an external terminal for connecting electrodes in parallel is formed, there arises an additional problem that the lower electrode is damaged by external pressure.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems. An object of the present invention is to provide a semiconductor device which can stably provide an external voltage while securing a maximum area of a capacitor electrode, maximizes a lamination structure of an electrode and a dielectric layer, And to provide an improved laminated capacitor.

Another object of the present invention is to provide a method of manufacturing the above-described laminated capacitor.

Still another object of the present invention is to provide a capacitor package for stably connecting the laminated capacitor to an external terminal.

A laminated capacitor for one purpose of the present invention comprises a base metal layer, a first surface dielectric layer formed on an upper surface of the base metal layer, a second surface dielectric layer formed on a lower surface of the base metal layer, At least two upper capacitor electrodes laminated with the first surface dielectric layer and having an area smaller than that of the first surface dielectric layer and upper dielectric layers respectively formed between the upper capacitor electrodes and connected to the upper capacitor electrodes Wherein the first surface dielectric layer and the second surface dielectric layer are sequentially stacked on the opposite surface of one surface of the second surface dielectric layer and in contact with the base metal layer, At least two lower capacitor electrodes, and a plurality of lower capacitor electrodes Connection of the lower dielectric layer is formed and, with the bottom capacitor electrode, respectively, and includes a lower connection electrode disposed on one side of the lower capacitor electrode.

In one embodiment, an upper insulating layer covering the edges of the upper capacitor electrodes is formed on the first surface dielectric layer, and a lower insulating layer covering the edges of the lower capacitor electrodes may be formed on the second surface dielectric layer .

The upper insulating layer may include holes for exposing the upper connecting electrodes, and the lower insulating layer may include holes for exposing the lower connecting electrodes.

In one embodiment, each of the upper dielectric layers is in contact with an edge of an upper connecting electrode connected to an upper capacitor electrode disposed directly below the upper dielectric layer, and each of the lower dielectric layers includes a lower And may contact the edge of the lower connecting electrode connected to the capacitor electrode.

In one embodiment, the upper connection electrodes are arranged in a line spaced on the first surface dielectric layer, and the lower connection electrodes may be arranged in a line spaced on the second surface dielectric layer.

In one embodiment, the upper connection electrodes and the lower connection electrodes may be formed symmetrically with respect to the base metal layer.

In one embodiment, two or more of the upper connection electrodes are arranged so as to overlap with each other, and two or more of the lower connection electrodes may be arranged so as to overlap with each other.

In one embodiment, the upper connection electrodes are divided into at least two groups and arranged so as to overlap with each other, and the lower connection electrodes are divided into at least two groups and arranged so as to overlap each other vertically.

At this time, through holes may be formed through the upper connecting electrodes in one group arranged to overlap with each other, and through holes may be formed through the lower connecting electrodes in one group arranged to overlap with each other.

In one embodiment, the base metal layer comprises aluminum, and each of the first surface dielectric layer and the second surface dielectric layer may comprise aluminum oxide.

A method of manufacturing a laminated capacitor for another purpose of the present invention includes the steps of: a first anodizing both sides of an aluminum foil; a first anodizing step of forming a first upper metal layer on the first surface dielectric layer formed on the first surface of the aluminum foil, And forming a first upper connection electrode connected to the first upper metal layer, forming a first lower metal layer and a first lower metal layer on the second surface dielectric layer formed on the second surface of the aluminum foil through a first anodization process, Forming an upper first connection electrode, a first upper connection electrode, and a second upper connection electrode, wherein the first upper connection electrode and the second connection electrode are connected to each other; Forming a lower capacitor electrode and a first lower dielectric layer, forming a second upper metal layer and a second upper metal layer on the first upper dielectric layer formed through a second anodization process, Forming a second lower connection electrode connected to the second lower metal layer and the second lower metal layer on the first lower dielectric layer formed through the second anodization process; The second upper and lower connection electrodes are masked and the second upper and lower metal layers are third anodized to form a second upper capacitor electrode, a second upper dielectric layer, a second lower capacitor electrode, .

In one embodiment, the first anodizing process comprises dipping the aluminum foil in an electrolytic solution to simultaneously anodize both sides of the aluminum foil to form a base metal layer made of aluminum, and a second surface dielectric layer And forming the second surface dielectric layer, wherein the second anodizing process simultaneously anodically oxidizes the first upper and lower metal layers by immersing the base metal layer in which the first upper and lower metal layers are formed in the electrolyte, The oxidation process can simultaneously anodize the second upper and lower metal layers by immersing the base metal layer in which the second upper and lower metal layers are formed in the electrolyte solution.

According to another aspect of the present invention, there is provided a capacitor package comprising: the laminated capacitor described above; and a laminated capacitor including the laminated capacitor in an inner space formed by a bottom portion and side portions connected to the bottom portion, A first inner electrode connected to the upper connection electrodes and the lower connection electrodes, and a second inner electrode separated from the first inner electrode and connected to the upper and lower connection electrodes of the second group do.

In one embodiment, the upper and lower connection electrodes of the first group are vertically overlapped with each other, and the upper connection electrodes and the lower connection electrodes of the second group are also arranged in a region other than the first group Wherein the package housing comprises a first penetrating electrode penetrating the upper and lower connecting electrodes of the first group and having a lower end in contact with the first inner electrode, And a second penetrating electrode penetrating the connecting electrodes and having a lower end in contact with the second internal electrode.

In one embodiment, the upper and lower connection electrodes of the first group and the upper and lower connection electrodes of the second group may be exposed to the outside on the same side to face the side of the package housing.

In one embodiment, the first internal electrode and the second internal electrode each include a first electrode portion directly contacting the exposed side surfaces of the upper and lower connection electrodes and formed on a side surface of the package housing, And a second electrode part connected to the bottom of the package housing.

In one embodiment, the capacitor package includes a first external terminal connected to the first internal electrode and connected to the outside through a bottom portion of the package housing, and a second external terminal connected to the second internal electrode, And a second external terminal connected to the second external terminal.

In one embodiment, the first inner electrode and the second inner electrode may be spaced apart from each other at the bottom of the package housing.

According to the laminated capacitor of the present invention, the method of manufacturing the same, and the capacitor package including the capacitor electrode, a connecting electrode extending from the capacitor electrode is formed at the periphery of the capacitor region to secure the maximum area of the capacitor electrodes, So that the efficiency of the laminated capacitor can be maximized. In addition, since such a laminated capacitor results in two dielectric layers and two electrodes formed simultaneously in one anodization process, it can be manufactured through a simple process.

In addition, it is possible to provide a package housing of a structure capable of stably supplying a voltage from the outside and a capacitor package of a stable structure including the laminated capacitor.

1 is a plan view for explaining a laminated capacitor according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line I-I 'and II-II' of FIG.
FIGS. 3 to 9 are views for explaining a method of manufacturing the laminated capacitor shown in FIGS. 1 and 2. FIG.
10 is a plan view for explaining a laminated capacitor according to another embodiment of the present invention.
11 is a cross-sectional view taken along lines III-III 'and IV-IV' of FIG.
12 is a view for explaining a package housing according to an embodiment of the present invention.
13 is a plan view for explaining a capacitor package according to an embodiment of the present invention.
14 is a cross-sectional view taken along lines V-V 'and VI-VI' of FIG.
15 is a plan view for explaining a capacitor package according to another embodiment of the present invention.
16 is a plan view for explaining the package housing of Fig. 15;
17 is a cross-sectional view taken along line VII-VII 'of FIG.
FIG. 18 is a cross-sectional view taken along the line VIII-VIII 'of FIG. 15; FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the term "comprises" or "having" is intended to designate the presence of stated features, elements, etc., and not one or more other features, It does not mean that there is none.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

FIG. 1 is a plan view for explaining a laminated capacitor according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line I-I 'and II-II' of FIG.

1 and 2, a stacked capacitor 501 includes a base metal layer 110, a first surface dielectric layer 120, a second surface dielectric layer 130, a plurality of upper capacitor electrodes 212a, 222a, 232a, A plurality of lower dielectric layers 214b, 224b, and 234b, a plurality of lower dielectric layers 214a, 224a, and 234a, a plurality of lower capacitor electrodes 212b, 222b, 232b, and 300b, CE21, CE31, CE41 and first through fourth lower connection electrodes CE12, CE22, CE32, CE42.

The base metal layer 110 may be a metal layer made of aluminum. The base metal layer 110 may be high purity aluminum made of aluminum, or aluminum alloy partially containing other metals.

A first surface dielectric layer 120 is formed on the first surface of the base metal layer 110 and a second surface dielectric layer 130 is formed on the second surface that is the opposite surface of the first surface. Each of the first and second surface dielectric layers 120, 130 may be a porous layer of aluminum oxide. For example, fine irregularities may be formed in opposite portions of portions of the first and second surface dielectric layers 120 and 130 that are in contact with the base metal layer 110, respectively. Each of the first and second surface dielectric layers 120 and 130 may be formed to have an area substantially equal to the surface area of the base metal layer 110.

Hereinafter, the first surface will be referred to as the upper surface and the second surface will be referred to as the lower surface with reference to the base metal layer 110 for convenience of explanation. The "upper part of the second surface" means a direction away from the second surface of the base metal layer 110, not a direction facing upward from the ground, and means the same direction as a downward direction with respect to the ground surface. Further, the "bottom" of the components arranged on the second surface means a portion close to the second surface of the base metal layer 110. [

Each of the plurality of upper capacitor electrodes 212a, 222a, 232a and 300a and the plurality of lower capacitor electrodes 212b, 222b, 232b and 300b may be aluminum electrodes. At this time, the aluminum electrode may be high purity aluminum made of aluminum, or aluminum alloy partially containing another metal.

The upper capacitor electrodes 212a, 222a, 232a, and 300a are formed on one region of the base metal layer 110 on the side facing the first surface, and are stacked on top of each other. The lower capacitor electrodes 212b, 222b, 232b, and 300b are formed on one region of the base metal layer 110 facing the second surface, and are stacked on top of each other. The upper capacitor electrodes 212a, 222a, 232a and 300a and the lower capacitor electrodes 212b, 222b, 232b and 300b may be stacked on top of each other in the vertical direction of the base metal layer 110. [ The upper capacitor electrodes 212a, 222a, 232a and 300a are formed of first, second, third and fourth upper capacitor electrodes 212a, 222a, 232a and 300a sequentially stacked from the first surface dielectric layer 120, . The lower capacitor electrodes 212b, 222b, 232b and 300b are formed of first, second, third and fourth lower capacitor electrodes 212b, 222b, 232b, and 232b sequentially stacked from the second surface dielectric layer 130, 300b.

Hereinafter, a region where the upper capacitor electrodes 212a, 222a, 232a, and 300a and the lower capacitor electrodes 212b, 222b, 232b, and 300b are formed will be referred to as a "capacitor region" CE21, CE31, and CE41 and the first through fourth lower connection electrodes CE12, CE22, CE32, and CE42 among the peripheral portions, and the other region is referred to as a "peripheral portion & Will be referred to as "electrode forming portion ". In the laminated capacitor 501, the first to fourth upper connection electrodes CE11, CE21, CE31, and CE41 and the first to fourth lower connection electrodes CE12, CE22, CE32, Are stacked so as to overlap each other in the vertical direction of the metal layer (110).

The upper dielectric layers 214a, 224a, and 234a are disposed between the upper capacitor electrodes 212a, 222a, 232a, and 300a. A first upper dielectric layer 214a is disposed between the first and second upper capacitor electrodes 212a and 222a and a second upper dielectric layer 224a is provided between the second and third upper capacitor electrodes 222a and 232a. And a third upper dielectric layer 234a is disposed between the third and fourth upper capacitor electrodes 232a and 300a. The upper capacitor electrode formed directly below the upper dielectric layer may be entirely covered. Substantially, the top dielectric layers 214a, 224a, and 234a are formed integrally with the top capacitor electrodes 212a, 222a, and 232a formed directly below the top dielectric layer. That is, the metal layer remaining on the surface of one metal layer is anodized to become the capacitor electrode, and the anodized portion becomes the dielectric layer.

The lower dielectric layers 214b, 224b and 234b are disposed between the lower capacitor electrodes 212b, 222b, 232b and 300b and may cover the lower capacitor electrode formed directly below the upper dielectric layer. The lower dielectric layers 214b, 224b, and 234b are also formed integrally with the lower capacitor electrodes 212b, 222b, 232b, and 300b. A first lower dielectric layer 214b is disposed between the first and second lower capacitor electrodes 212b and 222b and a second lower dielectric layer 224b is provided between the second and third lower capacitor electrodes 222b and 232b. And a third lower dielectric layer 234b is disposed between the third and fourth lower capacitor electrodes 232b and 300b.

The first upper connection electrode CE11 is connected to the first upper capacitor electrode 212a, the second upper connection electrode CE21 is connected to the second upper capacitor electrode 222a, the third upper connection electrode CE31, Is connected to the third upper capacitor electrode 232a. In addition, the fourth upper connection electrode CE41 is connected to the fourth upper capacitor electrode 242a. At this time, the first upper connection electrode CE11 is in contact with the edge of the first upper dielectric layer 214a, and the second upper connection electrode CE21 is in contact with the edge of the second upper dielectric layer 224a. Also, the third upper connecting electrode CE31 contacts the edge of the third upper dielectric layer 234a. This is because in the manufacturing process, the first to fourth upper connection electrodes CE11, CE21, CE31, and CE41 are not anodized and keep their thickness continuously, so that the first to third upper connection electrodes The edges of the grooves 214a, 224a, and 234a are in contact with them.

The first lower connection electrode CE12 is connected to the first lower capacitor electrode 212b and the second lower connection electrode CE22 is connected to the second lower capacitor electrode 222b. The third lower connection electrode CE32 is connected to the third lower capacitor electrode 232b and the fourth lower connection electrode CE42 is connected to the fourth lower capacitor electrode 234b. At this time, the first lower connection electrode CE12 is in contact with the edge of the first lower dielectric layer 214b, and the second lower connection electrode CE22 is in contact with the edge of the second lower dielectric layer 224b. Also, the third lower connection electrode CE32 is in contact with the edge of the third lower dielectric layer 234b.

A lower insulating layer IL2 is formed on the peripheral portion except for the capacitor region and the electrode forming portion. The upper insulating layer IL1 is formed on the first surface dielectric layer 120 and the first to fourth upper connection electrodes CE11, CE21, CE31, and CE41 are spaced apart from each other in the peripheral portion of the first surface And at least one of them is formed on the upper insulating layer IL1. The lower insulating layer IL2 is formed on the second surface dielectric layer 130 and the first through fourth lower connection electrodes CE12, CE22, CE32, CE42 are also spaced apart from each other in the peripheral portion of the second surface And at least one of them is formed on the lower insulating layer IL2. Each of the upper and lower insulating layers IL1 and IL2 includes an insulating material and may be formed of, for example, polyimide. Each of the upper and lower insulating layers IL1 and IL2 may be configured by stacking a plurality of insulating layers FL, SL, TL, and FOLs 4 to 9 as shown in FIG.

The upper insulating layer IL1 includes electrode exposures EP exposing the first through fourth upper connection electrodes CE11, CE21, CE31, and CE41, respectively. The lower insulating layer IL2 also includes electrode exposed portions that expose the first through fourth lower connection electrodes CE12, CE22, CE32, and CE42, respectively. The first to fourth upper connection electrodes CE11, CE21, CE31 and CE41 and the first to fourth lower connection electrodes CE1, CE2, CE3, and CE41 through the electrode exposed portions EP of the upper and lower insulating layers IL1, IL2 CE12, CE22, CE32, and CE42 can receive a voltage from the outside. The electrode exposed portions EP may be filled with an electrode material connected to the external electrode.

In one embodiment, the first upper connecting electrode CE11 is formed on the first surface dielectric layer 120 and the second, third and fourth upper connecting electrodes CE21, CE31 and CE41 are formed on the upper insulating layer IL1. &Lt; / RTI > The thickness of the upper insulating layer IL1 under the second upper connecting electrode CE21 is greater than the thickness of the upper insulating layer IL1 under the third upper connecting electrode CE31 and the fourth upper connecting electrode CE41 It can be thin. The edges of the first to fourth upper capacitor electrodes 212a, 222a, 232a and 300a and the first to third upper dielectric layers 214a, 224a and 234a formed in the capacitor region are connected to each other by the upper insulating layer IL1 Can be enclosed.

Since the first upper capacitor electrode 212a and the first upper dielectric layer 214a are formed and then the second upper connection electrode CE21 is formed, a step with the first surface dielectric layer 120 occurs. Since the second upper capacitor electrode 222a and the second upper dielectric layer 224a are formed and then the third upper connection electrode CE31 is formed, the step difference with the first surface dielectric layer 120 becomes larger and gradually As the electrode is further formed, defects such as disconnection of the electrode may occur during the process of forming the connection electrode. However, by forming the upper insulating layer IL1, such a step can be minimized.

The lower insulating layer IL2 is also formed on the first to fourth lower capacitor electrodes 212b, 222b, 232b and 242b and the first to fourth lower dielectric layers 214b, 224b, 234b and 244b, It is possible to minimize a step with the second surface dielectric layer 130 in the process of forming the lower connection electrodes CE12, CE22, CE32, and CE42.

2, the first upper connection electrode CE11 is arranged to face the fourth lower connection electrode CE42, and the second, third and fourth upper connection electrodes CE21, CE31 and CE41 are arranged in the third, The first upper and lower connection electrodes CE11 and CE12 are opposed to each other and the second upper connection electrodes CE11 and CE12 are disposed opposite to each other. And the lower connection electrodes CE21 and CE22 may face each other.

FIGS. 3 to 9 are views for explaining a method of manufacturing the laminated capacitor shown in FIGS. 1 and 2. FIG.

Referring to FIGS. 3 and 4 together with FIGS. 1 and 2, first an aluminum foil is prepared and first anodized to form a base metal layer 110, first and second surface dielectric layers 120 and 130 do. The first anodizing step can be carried out by immersing the aluminum foil as a whole in a reaction vessel containing an electrolyte, and applying a voltage. The both surfaces of the aluminum foil are respectively anodically oxidized and the remaining portion made of aluminum becomes the base metal layer 110 and the anodized portions become the first and second surface dielectric layers 120 and 130, respectively.

The first anodizing step may be carried out in two anodizing steps. In the two anodizing steps, different types of electrolytes can be used. A first electrolyte containing sulfuric acid, phosphoric acid, oxalic acid, or the like may be used as the first liquid, and a second electrolyte containing boric acid, citric acid, or the like may be used as the second liquid. The pore layer containing the pores and the dense layer are formed in the step of using the first electrolyte and the pore size of the pore layer is reduced and the thickness of the dense layer is thickened in the step of using the second electrolyte.

On the other hand, before the first and second surface dielectric layers 120 and 130 are formed, a step of forming a concave-convex structure on the surface of the aluminum foil can be further performed. For example, a concavo-convex structure may be formed on both sides of an aluminum foil by physical methods such as sanding, polishing, and imprinting, or a concavo-convex structure may be formed by a chemical method such as surface etching . As the request structure is formed, the effective surface area of the first and second surface dielectric layers 120, 130 can be increased.

A first insulating layer FL is formed on the base metal layer 110 on which the first and second surface dielectric layers 120 and 130 are formed. A first insulating layer FL is formed in each of the first and second surface dielectric layers 120 and 130. The first insulating layer FL may be formed in a region of the capacitor region and the peripheral portion excluding the region where the first upper and lower connection electrodes CE11 and CE12 are to be formed.

Referring to FIGS. 5, 6 and 7, first and second lower and upper capacitor electrodes 212a and 212b, a first lower and an upper dielectric layer 214a are formed on a base metal layer 110 on which a first insulating layer FL is formed. , 214b, and first and second connection electrodes CE11, CE12.

A first upper metal layer 210a is formed on a first surface of the capacitor region and a second lower metal layer (not shown) is formed on a second surface of the capacitor region. The electrode formation portion is connected to the first upper metal layer 210a A first upper connection electrode CE11 and a first lower connection electrode CE12 connected to the lower metal layer are formed. Each of the first upper metal layer 210a and the first lower metal layer may be formed to be narrower than the plane of the base metal layer 110.

Next, as shown in FIG. 7, in order to protect the first upper and lower connection electrodes CE11 and CE12, the second anodization process is performed by immersing the first and the upper connection electrodes CE11 and CE12 in the electrolyte ASOL in a masked state. The masking can be performed by blocking the electrolyte ASOL from contacting the first upper and lower connection electrodes CE11 and CE12 using the masking resin REL.

A part of the first upper metal layer 210a is anodically oxidized to form the first upper dielectric layer 214a and the first upper capacitor electrode 212a by the second anodic oxidation process, A lower dielectric layer 214b and a second lower capacitor electrode 214a are formed. The second anodizing process is substantially the same as the first anodizing process described with reference to Figs. 3 and 4, and the anodizing process may be performed in one or two steps.

After the first upper and lower dielectric layers 214a and 214b are formed, a second dielectric layer SL is formed on the first upper dielectric layer 214a and the first lower dielectric layer 214b, respectively. The second insulating layer SL is formed in the peripheral portion excluding the electrode forming portions of the first upper and lower connection electrodes CE11 and CE12 and the second upper and lower connection electrodes CE21 and CE22. The surfaces of the first upper connection electrode CE11 and the first upper dielectric layer 214a may be exposed by the second insulation layer SL and the surfaces of the first lower connection electrode CE12 and the first lower dielectric layer 214b may be exposed. The surface may be exposed. The first insulating layer FL of the electrode forming portions of the second upper connecting electrode CE21 and the second lower connecting electrode CE22 may be exposed by the second insulating layer SL. The second insulating layer SL may be formed of the same material as the first insulating layer FL.

Referring to FIG. 8, second upper and lower capacitor electrodes 222a and 222b, second upper and lower dielectric layers 224a and 224b, and second and third lower electrode layers 224a and 224b are formed on a base metal layer 110 on which a second insulating layer SL is formed. 2 upper and lower connection electrodes CE21 and CE22.

A second upper metal layer (not shown) is formed on the first surface of the capacitor region, and a second lower metal layer (not shown) is formed on the second surface. In addition, a second upper connection electrode CE21 connected to the second upper metal layer and a second lower connection electrode CE22 connected to the second lower metal layer are formed in the electrode formation portion.

Next, while the second upper and lower connection electrodes CE21 and CE22 are protected, the second upper and lower metal layers are subjected to a third anodization to form second upper and lower capacitor electrodes 222a and 222b, To form upper and lower dielectric layers 224a and 224b. Since the third anodization process is the same as at least one of the first and second anodization processes described above, a detailed description will be omitted.

After forming the second upper and lower dielectric layers 224a and 224b, a third insulating layer TL is formed. The third insulating layer TL may be formed of the same material as the first and second insulating layers FL and SL.

The third insulating layer TL is formed on the first surface except the electrode forming portions of the first to third upper connection electrodes CE11, CE21, and CE31, and on the second surface, CE12, CE22, and CE32, except for the electrode forming portion. The surface of the first to third upper connection electrodes CE11, CE21, CE31 and the surface of the second upper dielectric layer 224a may be exposed by the third insulating layer TL, The surfaces of the connection electrodes CE12, CE22, CE32 and the second lower dielectric layer 224b may be exposed. In addition, the second insulating layer SL of the electrode forming portions of the third upper and lower connecting electrodes CE31 and CE32 can be exposed by the third insulating layer TL.

Referring to FIG. 9, the third upper and lower capacitor electrodes 232a and 232b, the third upper and lower dielectric layers 234a and 234b, and the third upper and lower dielectric layers 234a and 234b are formed on the base metal layer 110 on which the third insulating layer TL is formed. And the lower connection electrodes CE31 and CE32 are formed, and then a fourth insulation layer FOL is formed on each of the first and second planes.

The fourth insulating layer FOL is formed on the first surface except for the electrode forming portions of the first through fourth upper connecting electrodes CE11, CE21, CE31 and CE41, and on the second surface, the first through fourth CE22, CE32, and CE42, except for the electrode forming portions. The surface of the first to third upper connection electrodes CE11, CE21, CE31 and the surface of the third upper dielectric layer 234a may be exposed on the first surface by the fourth insulating layer FOL. The surfaces of the first through third lower connection electrodes CE12, CE22, CE32 and the surface of the third bottom dielectric layer 234b may be exposed on the second surface by the fourth insulating layer FOL. In addition, the third insulating layer TL of the electrode forming portions of the fourth upper and lower connecting electrodes CE41 and CE42 can be exposed by the fourth insulating layer FOL.

Referring to FIG. 9 together with FIG. 2, a fourth upper capacitor electrode 300a is formed on a first surface of a base metal layer 110 on which a fourth insulating layer (FOL) is formed, and a fourth lower capacitor electrode 300b. At this time, a fourth upper connection electrode CE41 connected to the fourth upper capacitor electrode 300a and a fourth lower connection electrode CE42 connected to the fourth lower capacitor electrode 300b are formed. A structure in which the first to third insulating layers FL, SL and TL are stacked is disposed under each of the fourth upper and lower connection electrodes CE41 and CE42. The first and second insulating layers FL and SL are disposed below the third upper and lower connection electrodes CE31 and CE32 and the first and second insulating layers FL and SL are formed under the second upper and lower connection electrodes CE21 and CE22. The thickness of the insulating layer IL disposed under the fourth upper and lower connection electrodes CE41 and CE42 is set to be greater than the thickness of the second upper and lower connection electrodes CE21 and CE22 and CE22, The thickness of the insulating layer IL which is thicker than the thickness of the insulating layer IL disposed under the upper and lower connecting electrodes CE31 and CE32 and disposed below the third upper and lower connecting electrodes CE31 and CE32 The thickness is thicker than the thickness of the insulating layer IL disposed under the second upper and lower connecting electrodes CE21 and CE22.

According to the above description, since the capacitor electrode and the dielectric layer can be formed on both sides of the metal layer by performing the one-step anodic oxidation process performed in the first or second step, a laminated capacitor having a high capacitor efficiency is provided, can do.

FIG. 10 is a plan view for explaining a laminated capacitor according to another embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along the line III-III 'and IV-IV' of FIG.

10 and 11, a stacked capacitor 502 includes a base metal layer 110, a first surface dielectric layer 120, a second surface dielectric layer 130, a plurality of upper capacitor electrodes 212a, 222a, 232a, A plurality of lower dielectric layers 214b, 224b, and 234b, a plurality of lower dielectric layers 214a, 224a, and 234a, a plurality of lower capacitor electrodes 212b, 222b, 232b, and 300b, CE21, CE31, CE41 and first through fourth lower connection electrodes CE12, CE22, CE32, CE42. In the laminated capacitor 502 of FIGS. 10 and 11, the first through fourth upper connection electrodes CE11, CE21, CE31, and CE41 and the first through fourth lower connection electrodes CE12, CE22, CE32, 1 and 2 except for the laminated structure of the laminated capacitor 501 of FIG. Therefore, redundant description will be omitted. In the following description, the first surface dielectric layer 120, the upper capacitor electrodes 212a, 222a, 232a, and 300a, the upper dielectric layers 214a, 224a, and 234a disposed on the first surface of the base metal layer 110, The position and structure relationship between the first to fourth upper connection electrodes CE11, CE21, CE31 and CE41 is the same as that of the second surface dielectric layer 130, the lower capacitor electrodes 212b, 222b, 232b CE21, CE31, and CE41 and the first through fourth lower connection electrodes CE12, CE22, CE32, CEb, and CEb, CE42), the structure on the first surface will be described, and the description on the structure on the second surface will be omitted.

11, the first upper connection electrode CE11 and the third upper connection electrode CE31 are arranged so as to face each other and are divided into a first group, and the second upper connection electrode CE21 and the fourth upper connection electrode CE31 are divided into a first group, The electrodes CE41 are arranged so as to face up and down and are divided into a second group. In addition, the first and third upper connection electrodes CE11 and CE31 are spaced apart from the second and fourth upper connection electrodes CE21 and CE41 by a predetermined distance in the left-right direction. That is, the first group of upper connection electrodes CE11 and CE31 and the second group of upper connection electrodes CE21 and CE41 are spaced apart from each other on the same plane. Likewise, the lower connection electrodes CE22 and CE42 of the first group and the lower connection electrodes CE12 and CE32 of the second group are disposed apart from each other on the same plane.

The upper and lower connecting electrodes CE11, CE31, CE22 and CE42 of the first group are penetrated by the first hole H1 and the upper and lower connecting electrodes CE21, Is penetrated by the second hole (H2). The first hole H1 and the second hole H2 are formed through the base metal layer 110 and the first and second surface dielectric layers 120 and 130, respectively. A first penetrating electrode IE1 is disposed in the first hole H1 and a second penetrating electrode IE2 is disposed in the second hole H2. Accordingly, the first and second connection electrodes CE11, CE31, CE22 and CE42 can be connected by the first penetrating electrode IE1 and the second connection electrode CE2 can be connected by the second penetrating electrode IE2, And the lower connection electrodes CE21, CE41, CE12, and CE32 may be connected. A voltage of a first polarity is applied to the first group, and a second voltage of the opposite polarity of the first polarity is applied to the second group.

On the other hand, the upper insulating layer IL1 is formed in the peripheral portion excluding the electrode forming portion. At least one of the first to fourth upper connection electrodes CE11, CE21, CE31 and CE41 may be formed on the insulating layer IL and the upper insulating layer IL1 may partially cover the electrode forming portion . The upper insulating layer IL1 may be formed to cover the edge of the electrode forming portion. At the same time, the upper insulating layer IL1 is interposed between the first upper connecting electrode CE11 and the third upper connecting electrode CE31, and between the second upper connecting electrode CE21 and the fourth upper connecting electrode CE41 .

The laminated capacitor 501 described with reference to FIGS. 10 and 11 can also be subjected to the one-step anodic oxidation process performed in one step or two steps to form the capacitor electrode and the dielectric layer on both sides of the metal layer, , Which can be easily produced.

The stacked capacitor 501 may be connected to an external terminal to easily apply a voltage. The structure for mounting the package in the package housing and the package housing will be described with reference to FIGS. 12 to 14. FIG.

12 is a view for explaining a package housing according to an embodiment of the present invention.

Sectional view taken along a line substantially the same as the line IV-IV 'of FIG. 10. Referring to FIG. 12, the package housing 401 is connected to the outside of the stacked capacitor 501 A bottom portion 420 facing the bottom surface of the stacked capacitor 501, a first internal electrode OE1, and a second internal electrode OE2 connected to the side portions 410 surrounding the wall.

The side portions 410 are connected to the bottom portion 420 to form an internal space, and the laminated capacitor 502 described in FIGS. 10 and 11 can be accommodated in the internal space. A pair of first and second inner electrodes OE1 and OE2 are disposed on the bottom part 420 and the first outer terminal SE1 connected to the first inner electrode OE1 is connected to the bottom part 420 and is connected to the outside. The second external terminal SE2 connected to the second internal electrode OE2 penetrates the bottom portion 420 and is connected to the outside. Voltages of opposite polarities are applied to the first and second external terminals SE1 and SE2.

The first internal electrode OE1 and the second internal electrode OE2 may be formed inside the package housing 401 by electroplating or electroless plating.

The first internal electrode OE1 extends along one direction of the bottom portion 420 and the second internal electrode OE2 extends in the same direction and is disposed apart from the first internal electrode OE1. The first internal electrode OE1 is directly in contact with and electrically connected to the first penetrating electrode IE1 of the stacked capacitor 502 and the second internal electrode OE2 is in direct contact with the second penetrating electrode IE2, Lt; / RTI >

FIG. 13 is a plan view for explaining a capacitor package according to an embodiment of the present invention, FIG. 14 is a cross-sectional view taken along line V-V 'and VI-VI' of FIG. 13, FIG. 7 is a plan view for explaining a capacitor package according to another embodiment. FIG.

The capacitor package 701 shown in Fig. 13 is a plan view showing a state in which the laminated capacitor 502 described with reference to Figs. 10 and 11 is mounted on the package housing 401 described in Fig. 12, and Fig. 13 with Fig. 14 and Fig. 15 The stacked capacitor 502 is electrically connected to the internal electrodes OE1 and OE2 of the package housing 401 via the first and second penetrating electrodes IE1 and IE2, The internal electrodes OE1 and OE2 are electrically connected to the external terminals SE1 and SE2. Thus, the laminated capacitor 502 can receive a voltage from the outside. When the laminated capacitor 502 is mounted in the package housing 401, a fixing member CAP is disposed on the top of the laminated capacitor 502 so that the laminated capacitor 502 is stably placed in the inner space of the package housing 401 .

At this time, in order to prevent the fourth lower capacitor electrode 300b from contacting with the first and second inner electrodes OE1 and OE2 to cause an electrical problem, the stacked capacitor 502 and the first and second An insulating member ISP may be disposed between the inner electrodes OE1 and OE2 and the insulating member ISP may be provided with first and second inner electrodes OE1 and OE2 and first and second penetrating electrodes IE1, and IE2) may be formed.

The stacked capacitor 502 is inserted into the package housing 401 and the first and second external electrodes SE1 and SE2 are formed by forming the first and second penetrating electrodes IE1 and IE2, It can be easily connected. The laminated capacitor 502 can be stably fixed in the package housing 401 with the fixing member CAP. Such a stacked capacitor package 701 can be easily assembled, and the structural stability can be improved.

FIG. 16 is a plan view for explaining the package housing of FIG. 15, FIG. 17 is a sectional view taken along the line VII-VII 'of FIG. 15, and FIG. 18 is a sectional view taken along the line VIII-VIII' .

16 to 18, the stacked capacitor package 702 includes a package housing 402 and a stacked capacitor 503. The laminated capacitor 503 shown in Figs. 16 and 18 is substantially the same as the laminated capacitor 502 described in Figs. 10 and 11 except for the structure of the peripheral portion and the connection relation of the package housing 402 and the laminated capacitor 503. [ The detailed description thereof will be omitted.

The first to fourth upper connection electrodes CE11, CE21, CE31 and CE41 and the first to fourth lower connection electrodes CE12, CE22, CE32 and CE42 of the laminated capacitor 503 are exposed to the side. These are electrically connected to the first and second external terminals SE1 and SE2 through the first and second internal electrodes OE1 and OE2 of the package housing 402. [ The stacked capacitor 503 is connected to the first through fourth upper connection electrodes CE11, CE21, CE31 and CE41 and through the first through fourth lower connection electrodes CE12, CE22, CE32, It is possible to manufacture a laminated capacitor by a simple process.

Side exposure is performed by forming the first to fourth upper connection electrodes CE11, CE21, CE31, CE41 and the first to fourth lower connection electrodes CE12, CE22, CE32, CE42, The upper and lower insulating layers IL1 and IL2 formed between the edge portions of the base metal layer 110 and the first and second surface dielectric layers 120 and 130 adjacent to the electrode forming portion are removed, CE21, CE31, CE41 and the first to fourth lower connection electrodes CE12, CE22, CE32, CE42, respectively.

The laminated capacitor package 702 may further include a fixing member CAP so that the fixing member CAP allows the laminated capacitor 503 to be stably fixed in the package housing 402. [

The first internal electrode OE1 includes a first electrode portion BE disposed on the bottom portion 420 of the package housing 402 and a second electrode portion BE connected to the first electrode portion BE to cover the side surface of the package housing 402 And a second electrode unit (WE) provided side by side with the first electrode unit (410). The second electrode portion WE of the first internal electrode OE1 can connect the first and second upper connection electrodes CE11, CE31, CE22 and CE42 and the first electrode portion BE is connected to the first And is connected to the external terminal SE1. For example, the first internal electrode OE1 may be L-shaped.

The first internal electrode OE1 and the second internal electrode OE2 may be formed inside the package housing 402 through electroplating or electroless plating.

The second inner electrode OE2 has substantially the same structure as the first inner electrode OE1 and the second electrode portion of the second inner electrode OE2 has the same structure as the first inner electrode OE1, The second internal electrode OE2 is connected to the second external terminal SE2 by direct contact with the electrodes CE21, CE41, CE12, and CE32.

10 to 18 illustrate the case where the total number of the upper connection electrodes and the lower connection electrodes is eight in total. However, before forming the fourth upper and lower capacitor electrodes 300a and 300b, The capacitor electrode and the dielectric layer may be stacked and the connection electrode connected thereto may be coupled to the package housing in the form of FIGS. 14, 17, and 18. FIG.

10 to 18, the connection electrodes are divided into two groups. However, a laminated capacitor may be formed to include five or more capacitor electrodes and connection electrodes, and three connection electrodes may be formed It is also possible to divide the design into groups.

The description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features presented herein.

501, 502, 503: stacked capacitors
401, 402: package housing
701, 702: Capacitor package
110: base metal layer
120, 130: first and second surface dielectric layers
212a, 222a, 232a, and 300a: first, second, third, and fourth upper capacitor electrodes
212b, 222b, 232b, and 300b: first, second, third, and fourth lower capacitor electrodes
214a, 224a, 234a: first, second and third top dielectric layers
214b, 224b, 234b: first, second, and third bottom dielectric layers
CE11, CE21, CE31, CE41: First, second, third, and fourth upper connecting electrodes
CE12, CE22, CE32, CE42: first, second, third, and fourth lower connecting electrodes
IL: insulation layer
FL, SL, TL, FOL: first, second, third and fourth insulating layers
IE1, IE2: first and second penetrating electrodes
OE1, OE2: first and second internal electrodes
SE1, SE2: first and second external terminals

Claims

A base metal layer;
A first surface dielectric layer formed on an upper surface of the base metal layer;
A second surface dielectric layer formed on a lower surface of the base metal layer;
At least two upper capacitor electrodes sequentially stacked on the first surface dielectric layer and having an area smaller than an area of the first surface dielectric layer;
Upper dielectric layers formed between the upper capacitor electrodes;
Upper connection electrodes respectively connected to the upper capacitor electrodes and disposed on one side of the upper capacitor electrodes;
At least two lower capacitor electrodes sequentially stacked on the opposite surface of one surface of the second surface dielectric layer in contact with the base metal layer and having an area smaller than that of the second surface dielectric layer;
Lower dielectric layers formed between the lower capacitor electrodes; And
And lower connection electrodes connected to the lower capacitor electrodes and disposed on one side of the lower capacitor electrodes,
Laminated capacitor.

The method according to claim 1,
An upper insulating layer covering an edge of the upper capacitor electrodes is formed on the first surface dielectric layer,
And a lower insulating layer covering an edge of the lower capacitor electrodes is formed on the second surface dielectric layer.
Laminated capacitor.

3. The method of claim 2,
Wherein the upper insulating layer includes holes for exposing each of the upper connection electrodes,
And the lower insulating layer includes holes for exposing each of the lower connection electrodes.
Laminated capacitor.

The method according to claim 1,
Each of the upper dielectric layers being in contact with an edge of an upper connecting electrode connected to an upper capacitor electrode disposed directly below the upper dielectric layer,
Wherein each of the lower dielectric layers is in contact with an edge of a lower connection electrode connected to a lower capacitor electrode disposed directly below the lower dielectric layer.

Laminated capacitor.

The method according to claim 1,
Wherein the upper connection electrodes are arranged in a line on the first surface dielectric layer,
And the lower connection electrodes are arranged in a line spaced on the second surface dielectric layer.
Laminated capacitor.

The method according to claim 1,
The upper connection electrodes and the lower connection electrodes
Wherein the base metal layer is formed symmetrically with respect to the base metal layer.
Laminated capacitor.

The method according to claim 1,
Two or more of the upper connection electrodes are arranged so as to overlap each other,
Wherein at least two of the lower connection electrodes are disposed so as to overlap with each other.
Laminated capacitor.

The method according to claim 1,
Wherein the upper connection electrodes are divided into at least two groups,
Wherein the lower connection electrodes are divided into at least two groups and are arranged so as to overlap with each other in the upper and lower directions.
Laminated capacitor.

9. The method of claim 8,
A through hole is formed through the upper connecting electrodes in one group arranged to overlap with each other,
Wherein a through hole is formed through the lower connection electrodes in one group arranged so as to overlap with each other,
Laminated capacitor.

The method according to claim 1,
Wherein the base metal layer comprises aluminum,
Wherein each of the first surface dielectric layer and the second surface dielectric layer comprises aluminum oxide.
Laminated capacitor.

A laminated capacitor according to any one of claims 1 to 10; And
A first inner electrode formed in the inner space and connected to the first and second upper connection electrodes and the lower connection electrodes, and a second inner electrode formed in the inner space, And a second internal electrode spaced from the first internal electrode and connected to the second group of upper connection electrodes and the lower connection electrodes.
Capacitor package.

12. The method of claim 11,
The first group of upper connection electrodes and the lower connection electrodes are arranged so as to overlap with each other in the vertical direction and the upper and lower connection electrodes of the second group are also vertically overlapped with each other in the region different from the first group Lt; / RTI &
A first penetrating electrode penetrating the upper and lower connecting electrodes of the first group and having a lower end in contact with the first inner electrode; And
And a second penetrating electrode penetrating the upper and lower connecting electrodes of the second group and having a lower end in contact with the second inner electrode.
Capacitor package.

13. The method of claim 12,
The upper and lower connection electrodes of the first group and the upper and lower connection electrodes of the second group
And the package housing is exposed to the outside at the same side to face a side portion of the package housing.
Capacitor package.

13. The method of claim 12,
The first and second internal electrodes
A first electrode part formed on a side surface of the package housing in direct contact with exposed side surfaces of the upper and lower connection electrodes; And
And a second electrode part connected to the first electrode part and formed on the bottom of the package housing.
Capacitor package.

12. The method of claim 11,
A first external terminal connected to the first internal electrode and connected to the outside through a bottom portion of the package housing; And
And a second external terminal connected to the second internal electrode and connected to the outside through a bottom portion of the package housing.
Capacitor package.

12. The method of claim 11,
The first inner electrode and the second inner electrode
Wherein the package housing is disposed at a bottom portion of the package housing,
Capacitor package.

A first anodizing both sides of the aluminum foil;
Forming a first upper metal layer and a first upper connection electrode connected to the first upper metal layer on a first surface dielectric layer formed on a first surface of the aluminum foil through a first anodization process;
Forming a first lower metal layer and a first lower connection electrode connected to the first lower metal layer on a second surface dielectric layer formed on a second surface of the aluminum foil through a first anodic oxidation process;
The first upper and lower metal layers are anodized to form a first upper capacitor electrode, a first upper dielectric layer, a first lower capacitor electrode, and a first lower dielectric layer in a state where the first upper and lower connection electrodes are masked step;
Forming a second upper metal layer on the first upper dielectric layer formed through a second anodization process and a second upper connection electrode connected to the second upper metal layer;
Forming a second lower metal layer on the first lower dielectric layer formed through a second anodic oxidation process and a second lower connection electrode connected to the second lower metal layer; And
The second upper and lower connection electrodes are masked and the second upper and lower metal layers are third anodized to form a second upper capacitor electrode, a second upper dielectric layer, a second lower capacitor electrode, &Lt; / RTI >
A method for manufacturing a laminated capacitor.

18. The method of claim 17,
Wherein the first anodizing step comprises dipping the aluminum foil in an electrolytic solution to anodically oxidize both surfaces of the aluminum foil at the same time to form a base metal layer made of aluminum and a second metal layer formed on the first surface dielectric layer and the second surface Forming a dielectric layer,
The second anodic oxidation process is a process of anodizing the first upper and lower metal layers by simultaneously anchoring the base metal layer formed with the first upper and lower metal layers into the electrolyte,
Wherein the third anodic oxidation process comprises dipping a base metal layer on which the second upper and lower metal layers are formed in an electrolyte to anodically oxidize the second upper and lower metal layers simultaneously,
A method for manufacturing a laminated capacitor.