KR101621560B1 - Test pattern of Liquid crystal display device - Google Patents

Abstract

According to the present invention, there is provided a liquid crystal display device including a liquid crystal display panel, a plurality of gate driving integrated circuits, a plurality of data driving integrated circuits, and first and second test patterns, The gate lines and the data lines are disconnected and the first and second test patterns are connected to the gate driving circuit and the data driving integrated circuit And a liquid crystal display test pattern electrically connected to the connected data line. Therefore, the present invention does not require a space for a separate test pattern, and can prevent damage to signal lines due to static electricity flowing into the panel during the manufacturing process.

Liquid crystal display, test, gate, data, inspection

Description

[0001] The present invention relates to a liquid crystal display device,

The present invention relates to a test pattern of a liquid crystal display device.

2. Description of the Related Art In general, a liquid crystal display device is fabricated by bonding a thin film transistor (hereinafter referred to as 'TFT') array substrate and a color filter substrate opposite to each other at regular intervals and filling a predetermined space between the two substrates with liquid crystal.

On the TFT array substrate, data lines and gate lines which are arranged in parallel in the vertical and horizontal directions are formed, and pixels are defined in a rectangular area where the data lines and the gate lines cross each other.

In addition, a switching element electrically connected to the gate lines and the data lines is provided in the pixel, and a gate scan signal supplied through the gate lines from the gate driver integrated circuit is applied to the gate lines When applied in units of lines, a switching element corresponding to the gate line is turned on, and a video signal supplied from the data driver circuit through the data lines is applied to the pixel.

The gate / data driving circuit receives a signal from a printed circuit board (PCB), converts the external signal into a signal suitable for operation of the liquid crystal display panel, Respectively.

As described above, when the liquid crystal display panel of the liquid crystal display device is completed, it is inspected whether a normal driving voltage or a data voltage is supplied to the gate pad and the data pad area from the gate driving circuit and the data driving circuit.

For this purpose, a separate test pattern is formed on the gate pad and the data pad area when manufacturing the TFT array substrate. The test pattern is electrically connected to the gate pad or the data pad to inspect the gate driving signal and the data signal through the test pattern.

However, in recent years, the liquid crystal display device is manufactured in a compact form with high-resolution characteristics, and it is difficult to secure a space for separately forming a test pattern.

Further, the test pattern is exposed from the outside and is likely to corrode. Since the test pattern is electrically connected to the gate line or the data line, there is a risk of damaging the signal lines of the liquid crystal display panel due to static electricity.

It is an object of the present invention to provide a liquid crystal display test pattern in which a test margin is secured by forming a test pattern so as to overlap a gate line or a data line in a link region connecting the pad region and the driving circuit.

It is another object of the present invention to provide a liquid crystal display test pattern in which signal lines and elements are protected from static electricity by disconnecting a gate line or a data line overlapping with a test pattern.

According to an aspect of the present invention, there is provided a liquid crystal display device test pattern comprising: a liquid crystal display panel defined by a plurality of data lines and a plurality of gate lines; A plurality of data driving integrated circuits mounted on one side of the liquid crystal display panel to supply data signals to the data lines; A plurality of gate driving integrated circuits mounted on the other side of the liquid crystal display panel to supply driving signals to the gate lines; A gate link portion connecting the gate driving integrated circuit and the gate lines; A data link unit connecting the data driving IC and the data lines; A first test pattern arranged to overlap with at least one of the gate lines of the gate link portion, respectively; And a second test pattern arranged to overlap with at least one or more data lines of the data link unit.

The test pattern of the liquid crystal display of the present invention is formed so as to overlap with at least one of the gate lines and the data lines, respectively, so that the design margin is secured.

In addition, the test pattern of the liquid crystal display of the present invention has the effect of preventing the damage of the signal lines from the static electricity by disconnection of the gate line or the data line formed under the test pattern.

In addition, the liquid crystal display device of the present invention can realize high resolution and miniaturization, and has the effect of accurately checking signal waveforms supplied to gate lines and data lines.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

Fig. 1 shows a test pattern of the liquid crystal display device of the present invention.

Referring to FIG. 1, an upper substrate 104 and a lower substrate 102 are bonded together such that the upper substrate 104 and the lower substrate 102 are opposed to each other. The data lines DL and the gate lines GL are arranged in parallel on the lower substrate 102 in the vertical and horizontal directions. The data lines DL and the plurality of data driving ICs 120 And a plurality of gate driving integrated circuits 140 for supplying gate pulses to the gate lines GL are mounted.

A color filter, a common electrode, a black matrix, and the like (not shown) are formed on the upper substrate 104. Here, the common electrode may be formed on the lower substrate.

The lower substrate 102 is provided with a plurality of data lines DL and a plurality of gate lines GL formed so as to intersect with each other and a plurality of gate lines GL formed in a region defined by a plurality of data lines DL and a plurality of gate lines GL. And a pixel electrode are formed.

The first test pattern Tp1 may be overlapped with at least one of the gate line 130 connecting the gate driving integrated circuit 140 and the gate lines 130 and the gate line 130 connected to the gate line 130, .

The second test pattern Tp2 may be overlapped with at least one of the data lines 110 connecting the data driving ICs 120 and the data lines 110, .

Here, the gate line and the data line overlapping with the first test pattern Tp1 and the second test pattern Tp2, respectively, are electrically disconnected in the overlapped region. The first test pattern Tp1 is electrically connected to one of the disconnected gate lines, and the second test pattern Tp2 is electrically connected to one of the disconnected data lines.

The data driving IC 140 converts a data signal into an image signal according to a data control signal and supplies the image signal to the data line DL through the plurality of data link units 110. The gate driving integrated circuit 140 generates a gate pulse in accordance with a gate control signal and generates a gate pulse through a plurality of gate links, To the line GL.

Upon completion of the liquid crystal display panel of the present invention, inspection is performed to see whether normal signal waveforms are supplied to the liquid crystal display panel. At this time, the first test pattern Tp1 and the second test pattern Tp2 region are welded with a laser, and then the disconnected gate line or data line is electrically connected.

Then, a test probe is contacted with the first test pattern Tp1 and the second test pattern Tp2 in the welding area to check whether the signal waveforms supplied to the gate line or the data line are normal.

Since the first test pattern Tp1 and the second test pattern Tp2 are located on the gate line and the data line, a space for a separate test pattern is not required. Therefore, a design margin can be ensured when a small-size liquid crystal display device of high resolution is manufactured.

In addition, since the gate lines or the data lines are patterned to be disconnected in the area overlapping the test patterns, it is possible to prevent the signal lines from being damaged due to the static electricity flowing into the panel during the manufacturing process.

In the present invention, a test pattern may be formed in the link portion region, and voltage waveforms (signal waveforms) output from the drive integrated circuits may be inspected. In the present invention, the gate driving integrated circuit and the data driving integrated circuit are all mounted on a substrate, but this is not fixed. Therefore, the output characteristics supplied from the system to the gate drive drive in the GIP (Gate In Panel) structure in which only the gate drive drive is mounted on the substrate or the output characteristics supplied from the gate drive drive to the gate line are formed as a test pattern .

Although the present invention has been described with reference to a liquid crystal display device, the present invention can be similarly applied to a flat panel display device such as an organic light emitting display device.

FIG. 2A is an enlarged view of a portion A in FIG. 1, and FIG. 2B is a cross-sectional view taken along a line I-I 'in FIG. 2A.

Referring to FIGS. 2A and 2B, a gate link portion is formed between the gate driving integrated circuit 140 and a gate pad (not shown) region. And the first test pattern Tp1 is disposed on at least one of the gate lines of the gate link portion.

The first test pattern Tp1 is electrically connected to any one of the disconnected gate lines GL through the contact portion C and the first test pattern Tp1 is electrically disconnected from the first test pattern Tp1, It is connected.

Referring to FIG. 2B, the gate line GL is electrically disconnected on the insulating substrate 100 under the first test pattern Tp1, and a gate insulating layer 131 and a protective layer (Not shown).

The contact portion C may be formed in a region where the gate line GL is exposed by removing the gate insulating film 131 and the protective film 135 when the contact hole is formed on the passivation film 135 during the lower substrate manufacturing process of the liquid crystal display device, to be. A part of the first test pattern Tp1 is electrically connected to the gate line GL through the contact portion C and the remaining portion of the first test pattern Tp1 is overlapped with the adjacent gate line GL, .

A first test pattern Tp1 overlapped with the gate line GL is welded with a laser to check whether a drive signal is normally supplied to the gate line GL from the gate drive integrated circuit 140. [ Thus, the first test pattern Tp1 and the lower gate line GL are electrically connected.

Therefore, the disconnected gate lines GL are connected to each other by the first test pattern Tp1.

In the present invention, since the test pattern is formed so as to overlap with at least one of the gate lines formed in the gate link region, there is an advantage that the test pattern can be formed even in a narrow space. Therefore, a small or thin liquid crystal display device having a high resolution can be realized.

The test pattern may be formed when the pixel electrode of the liquid crystal display device is formed. Accordingly, the test pattern may be formed of any one of ITO, ITZO, and IZO which are transparent insulating materials.

In addition, the test pattern is structurally exposed to the outside, and static electricity can be introduced through the test pattern. In order to prevent the gate line from being damaged, the gate line is electrically disconnected in the region overlapping with the test pattern.

FIG. 3A is an enlarged view of a portion B in FIG. 1, and FIG. 3B is a cross-sectional view taken along line II-II 'in FIG. 3A.

Referring to FIGS. 3A and 3B, a data link is formed between the data driving integrated circuit 120 and a data pad (not shown). The second test pattern Tp2 may be formed on at least one of the data lines of the data link portion.

The data line DL in the region overlapping the second test pattern Tp2 is disconnected and the second test pattern Tp2 is electrically connected to the disconnected data line DL through the contact portion C have.

3B, a gate insulating layer 131 is formed on the insulating substrate 100 on the insulating substrate 100 under the second test pattern Tp2. On the gate insulating layer 131, a data line DL ) Are electrically disconnected. A protective film 135 is formed on the data line DL.

The contact portion C is a region where the protective film 135 is removed and the data line DL is exposed to the outside. A part of the second test pattern Tp2 is electrically connected to the data line DL through the contact part C and the remaining part of the second test pattern Tp2 is overlapped with the adjacent broken data line GL, .

In order to check whether the data signal is normally supplied to the data line DL from the data driving integrated circuit 120, the second test pattern Tp2 overlapping the data line DL is welded with a laser, And is electrically connected to the data line DL.

As a result, the second test pattern Tp2 and the lower data line DL are electrically connected.

Therefore, the disconnected data lines DL are connected to each other by the second test pattern Tp2.

In the present invention, since the data line formed in the data link area is used as a signal line for testing, it is not necessary to secure a separate test pattern formation area. Therefore, a small or thin liquid crystal display device having a high resolution can be realized.

In addition, in the region where the test pattern is formed, the test pattern is exposed to the outside. As a result, static electricity may flow into the data line. In the present invention, the data line is electrically disconnected to prevent the static electricity.

Fig. 1 shows a test pattern of the liquid crystal display device of the present invention.

FIG. 2A is an enlarged view of a portion A in FIG.

2B is a sectional view taken along the line I-I 'in FIG. 2A.

Fig. 3A is an enlarged view of a portion B in Fig.

3B is a cross-sectional view taken along the line II-II 'in FIG. 3A.

 (Description of Reference Numbers to Main Parts of the Drawings)

100: insulating substrate 102: lower substrate

104: upper substrate 120: data driving integrated circuit

140: gate drive integrated circuit Tp1: first test pattern

Tp2: second test pattern

Claims (11)

A liquid crystal display panel defined by a plurality of data lines and a plurality of gate lines; A plurality of gate driving integrated circuits mounted on one side of the liquid crystal display panel to supply driving signals to the gate lines; A gate link portion connecting the gate driving integrated circuit and the gate lines; And And a first test pattern arranged to overlap with at least one or more gate lines of the gate link portion, A gate line in an area overlapping with the first test pattern is disconnected, Wherein the first test pattern is electrically connected to a gate line connected to the gate driving integrated circuit among the disconnected gate lines. A liquid crystal display panel defined by a plurality of data lines and a plurality of gate lines; A plurality of data driving integrated circuits mounted on one side of the liquid crystal display panel to supply data signals to the data lines; A data link unit connecting the data driving IC and the data lines; And And a second test pattern arranged to overlap with at least one of the data lines of the data link unit, A data line in an area overlapping with the second test pattern is disconnected, And the second test pattern is electrically connected to the data line connected to the data driving integrated circuit among the disconnected data lines. delete The liquid crystal display test pattern according to claim 1, wherein a gate line connected to the liquid crystal display panel among the disconnected gate lines is connected to the first test pattern by welding with the first test pattern by a laser. delete delete The liquid crystal display test pattern according to claim 2, wherein a data line connected to the liquid crystal display panel among the disconnected data lines is connected to the second test pattern by welding with the second test pattern by a laser. The method according to claim 1, Wherein the first test pattern includes a contact portion electrically connected to a gate line connected to the gate driving integrated circuit among the disconnected gate lines. 3. The method of claim 2, And the second test pattern includes a contact portion electrically connected to a data line connected to the data driving IC among the disconnected data lines. The method according to claim 1, Wherein the first test pattern is disposed at the same time when the pixel electrodes are disposed. 3. The method of claim 2, And the second test pattern is disposed at the same time when the pixel electrodes are disposed.

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