KR101616919B1 - Method for manufacturing thin film transistor array substrate - Google Patents

Abstract

A method of manufacturing a thin film transistor array substrate according to the present invention includes forming a gate electrode, a lower electrode of a storage capacitor, and a gate pad on a substrate, Forming a data line, a data pad, a source and a drain electrode, and a semiconductor pattern on the gate insulating film; forming a gate insulating film on the data line, the data pad, the source and drain electrodes, Forming a first contact hole exposing the gate pad, a second contact hole exposing the data pad, and a third contact hole exposing the drain electrode using the mask; And a third contact hole formed on the substrate, a pixel electrode, a storage capacitor Wherein the mask comprises a transmissive region for transmitting light, a transflective region for transmitting a portion of the light and blocking a portion of the light, and a blocking region for blocking light, And the third contact hole is formed through a semi-transmissive region disposed at a boundary between the transmissive region of the mask and the transmissive region.

Mask, contact hole

Description

[0001] The present invention relates to a thin film transistor array substrate,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display device, and more particularly, to a method of manufacturing a thin film transistor array substrate for a liquid crystal display device.

A liquid crystal display displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field.

A liquid crystal display device is formed by a color filter substrate on which a color filter array is formed and a thin film transistor substrate on which a thin film transistor array is formed. A plurality of pixel electrodes, to which data signals are individually supplied, are formed in a matrix form on the thin film transistor substrate. In the thin film transistor substrate, a thin film transistor for driving a plurality of pixel electrodes individually, a gate line for controlling the thin film transistor, and a data line for supplying a data signal to the thin film transistor are formed.

In the above-described thin film transistor substrate for a liquid crystal display, a mask process must be performed to pattern gate lines, data lines, gate electrodes, source and drain electrodes, or form drain contact holes and the like.

The masking process is a process in which an insulating layer such as a metal layer, a gate insulating film, or a protective film is formed by depositing or applying a material for forming patterns having a specific shape, for example, wiring or electrodes on a substrate, Forming a photoresist layer by applying a photoresist as a material and forming a transmissive region for transmitting light in the shape of a pattern to be formed on the photoresist layer or forming a blocking region for blocking light, The photoresist layer is exposed through a mask having a transmissive area and a blocking area, and after the exposing process, the photoresist layer is exposed to a developing solution to develop the photoresist layer, The part is left on the substrate or the light- Being a photo resist pattern is formed, and thus refers to a series of processes for forming such a wiring or an electrode or a contact hole, an insulating layer or metal layer exposed by the photoresist pattern on the outside of the substrate by etching.

In forming the drain contact hole or the gate or data pad contact hole on the protective layer, the shape of the contact hole is typically formed in a rectangular shape in the course of the mask process, 1, which is a plan view showing a part of the pattern corresponding to the contact hole of the contact hole, the mask 95 used in the exposure process for forming the rectangular contact hole also has the contact hole- The pattern 96 is formed in a rectangular shape, and the pattern 96 is formed as a blocking region BA for blocking light, and the other region is formed of a light- Or a transmissive area TA through which the rectangular pattern transmits light, as shown in FIG. 1, Configuration and the other region thereof is composed of a block area (BA).

On the other hand, recently, the size of the contact hole required in the device is gradually reduced, and the pattern of the mask corresponding to the contact hole is reduced to a fine size.

However, as shown in FIG. 1, when the contact hole is formed through the mask formed adjacent to the transmissive area TA and the blocking area BA, the distribution of the exposure dose becomes gentle and the overlapping effect with the neighboring area The photoresist may remain and the pattern may not be formed. There is a problem that the contact hole can not be formed in a desired region through this pattern.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a thin film transistor array substrate capable of forming a contact hole in a desired region.

According to another aspect of the present invention, there is provided a method of fabricating a thin film transistor array substrate, including: forming a gate electrode, a lower electrode of the storage capacitor, and a gate pad on a substrate; Forming a data line, a data pad, a source and a drain electrode, and a semiconductor pattern on the gate insulating film; forming a gate insulating film on the formed substrate by forming a data line, a data pad, a source and a drain electrode, A first contact hole exposing the gate pad, a second contact hole exposing the data pad, and a third contact hole exposing the gate electrode using the mask. A step of forming a hole on the substrate on which the first, second and third contact holes are formed, And forming a gate pad contact portion, wherein the mask comprises a transmissive region for transmitting light, a transflective region for transmitting a portion of the light and blocking a portion of the light, Wherein the third contact hole is formed through a semi-transmissive region disposed at a boundary between the transmissive region of the mask and the transmissive region.

The third contact hole is formed through a semi-transmissive region disposed at a boundary between the transmissive region and the transmissive region of the mask, the transmissive region and the semi-transmissive region of the mask being disposed on the protective film corresponding to the drain electrode Forming a photoresist pattern; and etching the passivation layer using the photoresist pattern to form a third contact hole.

According to another aspect of the present invention, there is provided a method of fabricating a thin film transistor array substrate including forming a gate electrode, a lower electrode of a storage capacitor, and a gate pad on a substrate, Forming a data line, a data pad, a source and a drain electrode, and a semiconductor pattern on the gate insulating film; forming a gate electrode on the data line, the data pad, the source and drain electrodes, Forming a protective film on the patterned substrate; forming a first contact hole exposing the gate pad to the protective film using a mask, a second contact hole exposing the data pad, and a third contact hole exposing the data pad, A step of forming a contact hole, a step of forming a contact hole on the substrate on which the first, second and third contact holes are formed Forming a pixel electrode, a storage capacitor top electrode, a data pad contact, and a gate pad contact, wherein the mask comprises a first transmissive region for transmitting light and a second transmissive region for transmitting only a portion of the light at the corners, A second transmissive region, and a blocking region for blocking light, and the third contact hole is formed through the second transmissive region of the mask.

Forming the third contact hole through the second transparent region of the mask includes disposing a second transparent region of the mask on the protective film corresponding to the drain electrode to form a photoresist pattern; And patterning the protective film to form a third contact hole.

The second transmissive region is formed as a transmissive region through which light is entirely transmitted through the central portion, and the corner portion is formed so as to protrude positively.

As described above, the method of manufacturing a thin film transistor array substrate according to the present invention has the effect of forming a contact hole in a desired region by forming a contact hole through a mask having a transmissive region and a neighboring semi-transmissive region.

In addition, the method of manufacturing a thin film transistor array substrate according to the present invention has the effect of forming a contact hole in a desired region by forming a contact hole through a mask in which a transmissive region with a sharp edge is disposed.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to the present invention will be described with reference to the accompanying drawings.

FIGS. 2A to 2F are flowcharts sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

A gate electrode 12a, a storage capacitor lower electrode 12b, and a gate pad 12c are formed on a substrate 10, as shown in Fig.

The substrate 10 includes a region G-Pad where a gate pad is formed, a region D-Pad where a data pad is formed, a region D-line where a data line is formed, a pixel region PXL, A region Cst in which a capacitor is formed, and a region in which a thin film transistor is formed (TFT).

The gate electrode 12a, the storage capacitor lower electrode 12b and the gate pad 12c are formed by sequentially forming a first metal layer and a photoresist on the substrate 10, To form a first photoresist pattern (not shown), and etching the first metal layer with an etching mask.

A gate insulating film 14 is formed on the substrate 10 on which the gate electrode 12a, the storage capacitor lower electrode 12b and the gate pad 12c are formed.

2B, a data line 18d, a data pad 18c, source and drain electrodes 18b and 18a, and a semiconductor pattern 16a are formed on a substrate 10 on which a gate insulating film 14 is formed. And a protective film 20 is formed on the substrate 10 on which the data line 18d, the data pad 18c, and the source and drain electrodes 18b and 18a are formed.

The semiconductor pattern 16a is formed under each of the data line 18d, the data pad 18c, and the source and drain electrodes 18b and 18a.

The method of forming the data line 18d, the data pad 18c, the source and drain electrodes 18b and 18a and the semiconductor pattern 16a will be described in more detail below.

First, a semiconductor layer, a second metal layer, and a second photoresist pattern are sequentially formed on a substrate 10 on which a gate insulating film 14 is formed.

At this time, the semiconductor layer is formed of an amorphous silicon layer and an n + amorphous silicon layer.

The second photoresist pattern is formed by photolithography using a second mask (not shown) after forming a photoresist on a substrate having the second metal layer formed thereon. At this time, the second mask uses a mask having three different transmissivities including a transmissive area for transmitting light, a transflective area for transmitting a part of light and blocking part of light, and a blocking area for blocking light. The photoresist remains as it is in the blocking region, and the photoresist remains in the transflective region at a lower thickness than the photoresist in the blocking region, and the photoresist does not remain in the transmissive region. Therefore, the blocking region is disposed in the region where the data pad is to be formed, the region in which the data line is to be formed, the region in which the source and drain electrodes are to be formed, the transflective region is disposed in the channel region of the thin film transistor, And the other area excluding the area in which the semi-transmissive area is disposed.

Next, the second metal layer and the semiconductor layer are etched using the second photoresist pattern as an etching mask to form the data line 18d, the data pad 18c, the semiconductor pattern 16a, and the source / drain electrode pattern on the substrate 10 .

Next, the second photoresist pattern is ashed to form a third photoresist pattern. At this time, the second photoresist pattern formed in the region where the channel is to be formed is removed in the ashing process, and the second metal layer of the source / drain electrode pattern formed in the region where the channel is to be formed is exposed.

Then, the source / drain electrodes 18b and 18a are formed by etching the second metal layer of the source / drain electrode pattern exposed with the etching mask.

Then, the third photoresist pattern is removed through a script process.

Next, as shown in FIG. 2C, a fourth photoresist pattern 22a is formed on the substrate 10 on which the protective film 20 is formed.

The fourth photoresist pattern 22a is formed by a photolithography process using a third mask 100 after forming a photoresist on the protective film 20. At this time, the third mask 100 includes a transmissive region P1 for transmitting light, a transflective region P2 for transmitting a part of light and blocking a part of the light, and a blocking region P3 for blocking light A mask having three different transmissivities is used.

At this time, the transmissive region P1 is arranged in a region corresponding to the region (G-Pad) where the gate pad is formed, the region (D-Pad) where the data pad is formed and the drain electrode of the thin film transistor The region P2 is disposed at a boundary portion of the transmissive region P1 arranged so as to correspond to the drain electrode of the thin film transistor TFT and the blocking region is a region excluding the region where the transmissive region P1 and the transflective region P2 are arranged And is disposed in the remaining area.

In particular, the transmissive region P1 and the transflective region P2 are disposed in a region corresponding to the drain electrode of the thin film transistor TFT, as shown in Fig. 4A, in order to form a contact hole thereafter.

2D, the passivation layer 20 is etched using the fourth photoresist pattern 22a formed on the substrate 10 to form first, second and third contact holes 24a, 24b, and 24c.

The first contact hole 24a exposes the drain electrode 18a by etching the passivation layer 20 and the data pad 18c is exposed by etching the passivation layer 20 by the second contact hole 24b, 3 contact hole 24c exposes the gate pad 18d by etching the gate insulating film 14 and the protective film 20.

At this time, since the first contact hole 24a is formed in a minute size, the transmissive area (P1 in FIG. 2C) of the mask 100 and the semi-transmissive area (P2 in FIG. Lt; / RTI >

In other words, if the blocking region (BA in Fig. 1) is disposed adjacent to the transmission region (TA in Fig. 1) as in the conventional case, the distribution of the exposure amount becomes gentle and the photoresist remains due to the overlapping effect with the neighboring portion, However, if the semi-transmissive areas P12 are provided on both sides of the transmissive area P1, even if the overlapping effect with the neighboring areas is caused, the photoresist in the semi-transmissive area A photoresist having a thickness smaller than the thickness of the first photoresist pattern 22a) is formed on the third photoresist pattern 22a.

Therefore, the first contact hole 24a formed through the fourth photoresist pattern 22a exposes the drain electrode 18a.

The etching for forming the first, second, and third contact holes 24a, 24b, and 24c is performed by dry etching.

Next, a strip process is performed on the substrate 10 on which the first, second and third contact holes 24a, 24b and 24c are formed to remove the fourth photoresist pattern 22a.

Next, as shown in FIG. 2E, a third metal layer 26a, which is a transparent metal layer, is formed on the substrate 10 on which the first, second and third contact holes 24a, 24b and 24c are formed, A fifth photoresist pattern 28 is formed on the metal layer 26a.

The fifth photoresist pattern 28 is formed by forming a photoresist on the third metal layer 26a and performing a photolithography process using the fourth mask on the photoresist.

Next, as shown in FIG. 2F, the third metal layer 26a is etched using the fifth photoresist pattern 28 as an etching mask on the substrate 10 to form the pixel electrode 26b, the storage capacitor upper electrode 26c ), A data pad contact portion 26d, and a gate pad contact portion 26e.

Next, a strip process is performed on the substrate 10 on which the pixel electrode 26b, the storage capacitor upper electrode 26c, the data pad contact portion 26d, and the gate pad contact portion 26e are formed to form the fifth photoresist pattern 28, The present process is completed.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention will be described.

3A to 3C are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

First, as shown in FIG. 3A, a gate electrode 20a, a storage capacitor lower pattern 20b, a gate insulating film 14, a data line 18d, a data pad 18c, Drain electrodes 18b and 18a, a semiconductor pattern 16a, and a protective film 20 are formed.

The gate electrode 20a, the storage capacitor lower pattern 20b, the gate insulating film 14, the data line 18d, the data pad 18c, the source and drain electrodes 18b and 18a, the semiconductor pattern 16a, (20) are formed through the same processes as those of FIGS. 2A and 2B of the first embodiment of the present invention, and a description thereof will be omitted.

Next, as shown in FIG. 3B, a fourth photoresist pattern 22b is formed on the substrate 10 having the protective film 20 formed thereon.

The fourth photoresist pattern 22b is formed by a photolithography process using the third mask 100 after forming a photoresist on the protective film 20. The third mask 100a includes a first transmissive area P1 for transmitting light, a second transmissive area P11 for transmitting all the light at the center and only a part of light at the corners, A mask having three different transmissivities including the region P3 is used.

In this case, the first transmission region P1 has a region G-Pad where a gate pad is formed, a region D-Pad where a data pad is formed, and a second transmission region P11 is a thin film transistor (TFT) And the blocking region P3 is disposed in a region other than the region where the first transmission region P1 and the second transmission region P11 are disposed.

In particular, the second transmissive area P11, which transmits all of the light at the center and only a part of the light at the corners, is then formed as a transmissive area, as shown in Figure 4B, to form a contact hole, It is formed so as to protrude very much.

3C, the protective film 20 is etched using the fourth photoresist pattern 22b formed on the substrate 10 by using the etching mask to form the first, second and third contact holes 24a, 24b, and 24c.

The first contact hole 24a exposes the drain electrode 18a by etching the passivation layer 20 and the data pad 18c is exposed by etching the passivation layer 20 by the second contact hole 24b, 3 contact hole 24c exposes the gate pad 18d by etching the gate insulating film 14 and the protective film 20.

At this time, since the first contact hole 24a is formed in a minute size, the first contact hole 24a is formed through the second transmission region P11 formed to protrude from the corner portion.

In other words, if the blocking region (BA in Fig. 1) is disposed adjacent to the transmission region (TA in Fig. 1) as in the conventional case, the distribution of the exposure amount becomes gentle and the photoresist remains due to the overlapping effect with the neighboring portion, However, as shown in Fig. 4B, if the corner portion of the transmissive region is formed to protrude slightly, there is no overlapping effect with the neighboring portion, so that a photoresist is formed in the contact hole forming region And the fourth photoresist pattern 22b which does not remain is formed.

Therefore, the first contact hole 24a formed through the fourth photoresist pattern 22b exposes the drain electrode 18a.

The etching for forming the first, second, and third contact holes 24a, 24b, and 24c is performed by dry etching.

Next, a strip process is performed on the substrate 10 on which the first, second and third contact holes 24a, 24b and 24c are formed to remove the fourth photoresist pattern 22a.

3D, a pixel electrode 26b, a storage capacitor upper electrode 26c, and data (not shown) are formed on a substrate 10 on which first, second and third contact holes 24a, 24b and 24c are formed. The pad contact portion 26d and the gate pad contact portion 26e are formed to complete the present process.

Since the pixel electrode 26b, the storage capacitor upper electrode 26c, the data pad contact portion 26d and the gate pad contact portion 26e are formed through the same processes as those of FIGS. 2e and 2f of the first embodiment of the present invention, A description thereof will be omitted.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Therefore, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

1 is a view showing a mask for forming a contact hole according to the prior art;

FIGS. 2A to 2F are flow charts sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

FIGS. 3A to 3C are flow charts sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

4A is a view showing a mask for forming a contact hole according to the first embodiment of the present invention

4B is a view showing a mask for forming a contact hole according to a second embodiment of the present invention

Claims (5)

delete delete Forming a gate electrode, a storage capacitor lower electrode, and a gate pad on the substrate; Forming a gate insulating film on the substrate on which the gate electrode, the lower electrode of the storage capacitor, and the gate pad are formed; Forming a data line, a data pad, a source and a drain electrode, and a semiconductor pattern on the gate insulating layer; Forming a protective film on the data line, the data pad, the source and drain electrodes, and the substrate on which the semiconductor pattern is formed; Forming a first contact hole exposing the gate pad on the protection layer using a mask, a second contact hole exposing the data pad, and a third contact hole exposing the drain electrode, Forming a pixel electrode, a storage capacitor upper electrode, a data pad contact, and a gate pad contact on a substrate on which the first, second, and third contact holes are formed, Wherein the mask comprises a first transmitting region for transmitting light, Using a mask including a second transmissive region provided in a transmissive region through which light is entirely transmitted through the central portion of the mask and a corner portion protruding sharply, and a blocking region blocking light, And the third contact hole is formed through a second transmission region of the mask. The method of claim 3, wherein the third contact hole is formed through a second transmissive region of the mask Forming a photoresist pattern by disposing a second transparent region of the mask on the protective film corresponding to the drain electrode; And forming a third contact hole by etching the protective film using the photoresist pattern. delete

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