KR101542209B1 - Solar cell and method for fabricating the same - Google Patents

Abstract

Disclosed are a solar cell battery and a manufacturing method thereof. According to the present invention, the solar cell battery comprises: a substrate (100) on which a unit solar cell battery section (A, B) comprising a unit cell section (A) and a wired line section (B) are arranged; a first semiconductor layer (310) which is formed on the substrate (100) and in which a first trench (T1) is formed on the wired section (B) of the substrate (100); a second semiconductor layer (320) which is formed on the first semiconductor layer (310) and exposes a portion of the first semiconductor layer (310) as a second trench (T2) is formed on the wired line section (B) of the substrate (100); a third semiconductor layer (330) which is formed on the second semiconductor layer (320) and exposes a portion of the second semiconductor layer (320) as a third trench (T3) is formed on the wired line section (B) of the substrate (100); and an electrode layer (400) which is formed on the third semiconductor layer (330) and is connected to the first semiconductor layer (310) through the second trench (T2).

Description

SOLAR CELL AND METHOD FOR FABRICATING THE SAME

The present invention relates to a solar cell and a manufacturing method thereof. More particularly, the present invention relates to a solar cell capable of simplifying a patterning process and a series connection structure, and a manufacturing method thereof.

In the conventional thin film solar cell, the photoelectric conversion efficiency is only about 10% or less, and thus various difficulties have been encountered in actual commercialization. To solve this problem, a technique has been developed in which a plurality of photoelectric elements are electrically connected in series to realize excellent photoelectric conversion efficiency.

Such a serial type solar cell is a method of obtaining required electric power by serially connecting a plurality of horizontally arranged photoelectric elements to an electrode (wiring).

However, in order to manufacture a conventional solar cell of the serial type, a process of repeatedly inverting the substrate is performed in order to perform the etching (pattern) process at least three times, so that the process and equipment are complicated, There is a problem that interference may occur and defects are generated.

In addition, the conventional solar cell has a complicated structure because a unit cell solar cell composed of photoelectric elements in which a plurality of semiconductor layers are stacked between a lower electrode and an upper electrode is connected in series with each other.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a solar cell capable of performing a plurality of etching processes on the entire surface of a substrate, and a manufacturing method thereof.

Another object of the present invention is to provide a solar cell which does not require a separate lower electrode when connected in series and a manufacturing method thereof.

It is another object of the present invention to provide a solar cell capable of forming a suitable structure according to an antireflection layer and a method of manufacturing the same.

The above object of the present invention is achieved by a solar cell module comprising: a substrate on which a unit solar cell region composed of a unit cell region and a wiring region is arranged; A first semiconductor layer formed on the substrate and having a first trench formed on the wiring region on the substrate; A second semiconductor layer formed on the first trench and the first semiconductor layer and having a second trench formed on the wiring region on the substrate to expose a portion of the first semiconductor layer; A third semiconductor layer formed on the second semiconductor layer and having a third trench formed on the wiring region on the substrate to expose a portion of the second semiconductor layer; And an electrode layer formed on the third semiconductor layer and connected to the first semiconductor layer through the second trench.

At this time, an anti-reflection layer may be further formed between the substrate and the first semiconductor layer.

The anti-reflection layer may include a structure in which the first trench is extended.

The anti-reflection layer may be silicon nitride (SiN _x ) or titanium nitride (TiN _x ).

The first, second and third semiconductor layers may be n, i, p or p, i, n.

According to another aspect of the present invention, there is provided a method of manufacturing a solar cell, comprising the steps of: (a) providing a substrate on which unit solar cell regions composed of a unit cell region and a wiring region are arranged; (b) forming a first semiconductor layer on the substrate; (c) a first etching step of etching the first semiconductor layer on the wiring region to form a first trench to be separated from another adjacent unit solar cell region; (d) sequentially forming a second semiconductor layer and a third semiconductor layer on the substrate including the first semiconductor layer; (e) forming a first mask layer on the third semiconductor layer, etching the third semiconductor layer and the second semiconductor layer simultaneously on the wiring region using the first mask layer, A second etch step of forming a second trench exposing a portion; (f) removing the first mask layer and forming an electrode layer on the substrate including the third semiconductor layer; (g) forming a second mask layer on the electrode layer, etching the electrode layer and the third semiconductor layer simultaneously on the wiring region using the second mask layer to expose a portion of the second semiconductor layer, A third etching step of forming a trench; And (h) removing the second mask layer. [0013] According to another aspect of the present invention, there is provided a method of manufacturing a solar cell,

The method may further include forming an anti-reflection layer between the substrate and the first semiconductor layer.

The antireflection layer may etch simultaneously with the first semiconductor layer by the first etching step to extend the first trench.

The anti-reflection layer may be formed of silicon nitride (SiN _x ) or titanium nitride (TiN _x ).

The first trench may be etched by a laser scribing method.

The second trench and the third trench may be etched in a wet manner.

The first, second, and third etching steps may be performed on top of the substrate.

The electrode layer may be formed of a transparent conductive material, a metal material, or a laminated structure thereof.

The first, second, and third semiconductor layers may be formed of n, i, p, or p, i, n.

According to the present invention, since a plurality of etching processes can be performed all over the substrate, it is not necessary to reverse the substrate (turn over), so that the process and equipment can be shortened and the occurrence of defects can be prevented.

In addition, according to the present invention, a separate lower electrode is not required for series connection, and the structure and process can be shortened.

Further, according to the present invention, a suitable structure can be formed according to the antireflection layer, and the photoelectric conversion efficiency can be improved.

FIGS. 1 to 9 are views sequentially illustrating a manufacturing process of a solar cell according to an embodiment of the present invention.
FIGS. 10 and 11 are views sequentially illustrating a manufacturing process of a solar cell according to another embodiment of the present invention.
12 and 13 are views showing a detailed configuration of a photoelectric element unit according to an embodiment of the present invention.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views, and length and area, thickness, and the like may be exaggerated for convenience.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

[Preferred Embodiment of the Present Invention]

In this specification, the unit cell region A is a region in which the photoelectric elements (including the first semiconductor layer, the second semiconductor layer and the third semiconductor layer) are located between the electrodes (between the first semiconductor layer and the electrode layer) Means a region on the substrate where photoelectric conversion of the solar cell is performed.

Note that, in this specification, the wiring region B refers to a region on the substrate which is located between the unit cell regions A and performs the function of separating the unit cells from one another and electrically connecting (for example, serially connecting) Quot; region ", which can be understood as a dead region in which photoelectric conversion of the solar cell does not substantially take place.

One unit cell area A and one wiring area B constitute the unit solar cell areas A and B and the unit solar cell areas A and B are formed in the embodiment of the present invention. A unit solar cell capable of performing both photoelectric conversion and wiring functions is formed.

For example, a plurality of unit solar cell region on the substrate (A, B) is may be arranged in the row and the column direction, n-th (n is a natural number) in a random line-by-line solar cell area unit cell area (A _n) And a wiring region B _n .

At this time, n-th unit solar cell area (A _n, B _n) and adjacent the one side region, the n + 1-th unit solar cell area [unit cell area (A _{n + 1)} and the wiring region (B _{n + 1)],} which, the unit solar cell regions may be arranged in the order of the ( _{n + 2} ) th unit solar cell region (unit cell region (A _{n + 2} ) and wiring region (B _{n + 2} )

The n-1 th unit solar cell region (unit cell region (A _n-1 ) and wiring region (B _n-1 )) is connected to the n-th unit solar cell region, (The unit cell area (A _n-2 ) and the wiring area (B _n-2 )).

In the following embodiments, for the sake of convenience, the cross-sectional view of the n-th unit solar cell region (unit cell region A _n and wiring region B _n ) among a plurality of unit solar cell regions on the substrate is described .

FIGS. 1 to 9 are views sequentially illustrating a manufacturing process of a solar cell according to an embodiment of the present invention.

1, a substrate 100 on which unit solar cell regions A and B including a unit cell region A and a wiring region B are arranged can be provided. The substrate 100 may be made of a transparent glass substrate, but the present invention is not limited thereto. For example, the substrate 100 may be made of glass, a transparent material such as plastic or an opaque material such as silicon or metal (for example, stainless steel) according to the direction of receiving light.

Texturing may then be performed on the surface of the substrate 100. In the present invention, texturing is intended to prevent a phenomenon in which light incident on a substrate surface of a solar cell is reflected and is optically lost, thereby deteriorating its characteristics. That is, the surface of the substrate is roughened to form an uneven pattern (not shown) on the substrate surface. For example, if the surface of the substrate is roughened by texturing, light reflected once on the surface can be reflected again toward the solar cell, thereby reducing loss of light, increasing the amount of trapped light and increasing the photoelectric conversion efficiency Can be improved.

At this time, as a typical texturing method, a sandblasting method can be used. The sandblasting in the present invention includes both dry blasting in which etching particles are sprayed with compressed air and etching, and wet blasting in which etching particles are sprayed with the liquid to etch. On the other hand, the etchant particles used in the sandblasting of the present invention can be used without limitation, such as sand or small metal, which can form irregularities on the substrate by physical impact.

Next, the anti-reflection layer 200 may be formed on the substrate 100. The antireflection layer 200 serves to prevent the solar cell incident on the substrate 100 from being absorbed by the optoelectronic device (semiconductor layer) to be formed thereafter and to be reflected directly to the outside, thereby lowering the efficiency of the solar cell . In one embodiment of the present invention, the material of the antireflection layer 200 may be, but is not necessarily limited to, silicon nitride (SiN _x ) including antireflection function and insulation.

The reflection ring layer may be formed by a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method.

Meanwhile, in another embodiment of the present invention, the material of the antireflection layer 200 may be titanium nitride (TiN _x ). In the case of such a titanium nitride (TiN _x ), it includes an excellent antireflection function. As shown in FIGS. 10 and 11, when the first semiconductor layer 310 to be formed later is patterned, The first trench T1 is formed by etching to provide a series type solar cell capable of preventing electrical interference (insulation) between unit cells.

The first semiconductor layer 310 may be formed on the entire upper surface of the antireflection layer 200. The first semiconductor layer 310 may be a conductive semiconductor doped with impurities to have conductivity, and may be, for example, p-type or n-type. Hereinafter, the first, second, and third semiconductor layers 310, 320, and 330 may function as a photoelectric element portion capable of converting light energy into electrical energy. The material of the first semiconductor layer 310 may be silicon (Si), which is commonly used, but is not limited thereto, and known semiconductor materials can be used without limitation.

The first semiconductor layer 310 may include a chemical vapor deposition method such as PECVD or LPCVD. The first semiconductor layer 310 may function as a lower electrode using a conductive property. In addition, the first semiconductor layer 310 can perform a part of a photoelectric device that receives light in the unit cell region A to produce electric power by a subsequent process.

Referring to FIG. 2, a first trench T1 is formed by first etching a part of the first semiconductor layer 310 on the wiring region B on the substrate 100 .

More specifically, the plurality of unit solar cell regions A and B constituted by the unit cell region A and the wiring region B can be separated from each other by the first etching process P1. For example, the n-th unit solar cell region (unit cell region A _n and wiring region B _n ) is connected to the n + 1th unit solar cell region (unit cell region A _{n + 1} ) and a wiring region (B _{n + 1)]} and the other side region of the n-1-th unit solar cell area [unit cell area (a _n-1) and the wiring region (B _n-1)] and physically, to be electrically separated have.

As a method of the first etching process (P1), a laser scribing method using a laser may be used. For example, the laser may be an ultraviolet or green wavelength laser.

  However, the present invention is not limited thereto, and an etching method including a known photolithography method can be used without limitation. In the laser scribing method, the irradiation direction of the laser may be irradiated on the upper side or the lower side of the substrate 100, but in the present invention, it is preferable that the patterning process is performed from the upper side of the substrate 100 as shown in FIG. Do.

Referring to FIG. 3, the second and third semiconductor layers 320 and 330 may be sequentially formed on the substrate 100 including the first trench T1 and the first semiconductor layer 310 have.

The second semiconductor layer 320 may be an i-type semiconductor, which is an intrinsic semiconductor that is not doped with impurities. The third semiconductor layer 330 may be a conductive semiconductor having conductivity by doping impurities. For example, the p- Or n-type. The first semiconductor layer 310 having the lower conductivity than the first and third semiconductor layers 310 and 330 is buried in the first trench T1 to function as a lower electrode. Can be electrically disconnected.

The material of the second and third semiconductor layers 320 and 330 may be silicon (Si), which is commonly used, but is not limited thereto and known semiconductor materials can be used without limitation.

The second and third semiconductor layers 320 and 330 may be formed by a chemical vapor deposition method such as PECVD or LPCVD. The unit cell region A receives light and generates electric power It is possible to perform some functions of the photoelectric element, more specifically, it will be understood by the following detailed description with reference to FIG. 12 and FIG.

Next, referring to FIG. 4, a first mask layer 10 may be formed on the third semiconductor layer 330. The first mask layer 10 may be a resin, for example, a known photoresist used in a photolithography process.

A first mask layer 10 having a predetermined pattern can be formed by patterning a part of the first mask layer 10 on the wiring region B on the substrate 100. [ The patterning of the first mask layer 10 may be laser or ink-jet patterning, but not limited thereto, and various known patterning methods may be used.

5, the second semiconductor layer 320 and the third semiconductor layer 330 are etched by a first mask layer 10 having a predetermined pattern on the wiring region B, The second trench T2 exposing a portion of the first semiconductor layer 310 may be formed.

As a method of the second etching process P2, the first mask layer 10 of the present invention, which is made of resin, is used to etch only the first semiconductor layer 310 without damaging, However, the present invention is not limited thereto, and a known etching method including dry etching can be used without limitation.

Then, a process of removing the first mask layer 10 may be performed, and known resin strip process techniques may be used without limitation.

6, the electrode layer 400 may be formed on the substrate 100 including the second trenches T2 and the third semiconductor layer 330. Referring to FIG. The material of the electrode layer 400 may be any conductive material. For example, transparent It is possible to use the TCO when the conductive layer, AZO (ZnO: Al), ITO (Indium-Tin-Oxide), GZO (ZnO: Ga), BZO (ZnO: B) , and FTO (SnO _2: F). In the case of the opaque conductive layer, a conventional metal material may be used. Examples of the material include metals such as aluminum (Al), silver (Ag), gold (Au), copper (Cu), zinc (Zn), titanium . ≪ / RTI >

In addition, the electrode layer 400 may be formed of a stacked structure of a transparent conductive layer and a metal layer, for example, BZO (ZnO: B) / Al.

Examples of the method for forming the electrode layer 400 include physical vapor deposition (PVD) such as thermal evaporation, E-beam evaporation, sputtering, and LPCVD, PECVD, And CVD (Chemical Vapor Deposition) such as metal organic chemical vapor deposition (MOCVD).

Meanwhile, the electrode layer 400 can perform the function of the upper electrode using the conductive property in the unit cell region A.

Next, referring to FIG. 7, a second mask layer 20 may be formed on the electrode layer 400. This second mask layer 20 may be patterned to have a predetermined pattern in the same manner as the first mask layer 10 of the detailed description with reference to Fig.

8, the electrode layer 400 and the third semiconductor layer 330 are etched by a third etching (that is, by a width of P3) by a second mask layer 20 having a predetermined pattern on the wiring region B. Next, referring to FIG. 8, A third trench T3 exposing a portion of the second semiconductor layer 320 may be formed.

As a method of the third etching process P3, the second mask layer 20 of the present invention, which is made of resin, is used to etch only the second semiconductor layer 320 without damage, However, the present invention is not limited thereto, and a known etching method including dry etching can be used without limitation.

Finally, referring to FIG. 9, a process for removing the second mask layer 20 may be performed, and known resin strip process techniques may be used without limitation.

Therefore, the electrode layer 400 may be formed by a series-type solar cell that electrically connects the first semiconductor layer 310 exposed by the second trench T2 and the third semiconductor layer 330 on another neighboring unit solar cell region Can be implemented.

For example, one of the electrode layer 400 is an n-th unit solar cells area can be connected to the line area the first semiconductor layer 310 through the second trench (T2) on the (B _n) of the (A _n, B _n) have. The other end of the electrode layer 400 is connected to the upper part of the third semiconductor layer 330 on the unit cell area A _n-1 of the adjacent n-1 th unit solar cell area A _n-1 , B _n- Can be connected.

Thus, the nth unit solar cells A _n and B _n can be connected in series with the ( _n-1 ) th unit solar cells A _n-1 and B _n-1 adjacent to one side region, The solar cell may be connected in series with the adjacent n + 1th unit solar cells A _{n + 1} and B _{n + 1} to realize a solar cell of the serial type.

As described above, the solar cell of the present invention can sequentially perform laser scribing and etching processes (for example, wet etching) at the top of the substrate 100, thereby reducing process and processing equipment .

In addition, since the series connection can be realized without a separate lower electrode, the structure and the process can be shortened.

Further, a suitable structure can be formed according to the material of the antireflection layer, and a solar cell having excellent photoelectric conversion efficiency can be realized.

Configuration of photoelectric device part

12 and 13 are views showing a detailed configuration of a photoelectric element unit according to an embodiment of the present invention.

Referring to FIG. 12, the photoelectric element portion 300 may include three layers of amorphous silicon layers 310, 320, and 330, for example. More specifically, a first amorphous silicon layer 310 may be formed on the substrate 100, a second amorphous silicon layer 320 may then be formed on the first amorphous silicon layer 310, A third amorphous silicon layer 330 may be formed on the amorphous silicon layer 320 to form one photoelectric device. At this time, the first, second, and third amorphous silicon layers 310, 320, and 330 may be formed by a chemical vapor deposition method such as PECVD or LPCVD.

Next, referring to FIG. 13, the photoelectric element portion 300 may be formed of three layers of polycrystalline silicon layers 311, 321, and 331, for example. More specifically, a first polycrystalline silicon layer 311 may be formed on the substrate 100, a second polycrystalline silicon layer 321 may be formed on the first polycrystalline silicon layer 311, A third polycrystalline silicon layer 331 may be formed on the polycrystalline silicon layer 321 to form one photoelectric device.

As a method of forming the first, second and third polycrystalline silicon layers 311, 321 and 331, the first, second and third amorphous silicon layers 310, 320 and 330 shown in FIG. 13 are crystallized Can be performed. That is, the first amorphous silicon layer 310 is a first polycrystalline silicon layer 311, the second amorphous silicon layer 320 is a second polycrystalline silicon layer 321, and the third amorphous silicon layer 330 is a 3 polycrystalline silicon layer 331, respectively.

The crystallization method of the first, second, and third amorphous silicon layers 310, 320, and 330 may include Solid Phase Crystallization (SPC), Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization ), And MILC (Metal Induced Lateral Crystallization). Since the above-described method of crystallizing amorphous silicon is well known in the art, a detailed description thereof will be omitted herein.

In the above description, the first, second and third amorphous silicon layers 310, 320 and 330 are all formed and then crystallized simultaneously. However, the present invention is not limited thereto. For example, the crystallization process may be separately performed for each one amorphous silicon layer, and the two amorphous silicon layers may simultaneously undergo a crystallization process, and the remaining one amorphous silicon layer may be crystallized separately.

As a result, on the substrate 100, the photoelectric elements composed of the first, second and third amorphous silicon layers 310, 320 and 330 or the first, second and third polycrystalline silicon layers 311, 321 and 331 . However, the present invention is not limited thereto, and if necessary, an optoelectronic device composed of a microcrystalline silicon layer may be used. In addition, as a material of the light absorbing layer of the solar cell, known materials other than silicon may be used without limitation.

Such a photoelectric device may be a p-i-n diode structure in which p-type, i-type, and n-type silicon layers are stacked in order to produce power by photovoltaic power generated by receiving light. Here, i means intrinsic in which no impurity is doped. Further, it is preferable that the n-type or p-type doping is doped in an in situ manner at the time of forming the amorphous silicon layer. Boron (B) is used as an impurity in the P-type doping, and phosphorus (P) or arsenic (As) is used as an impurity in the n-type doping. However, the present invention is not limited thereto.

On the other hand, the photoelectric device can be formed of p +, i, n + type, n, i, p type (especially n +, i, p + ) Or a silicon layer of n, n, p type (particularly, n +, n-, p +). Here, the meaning of + and - indicates the relative difference in doping concentration and means that the doping concentration is higher than + -. For example, n + means heavily doped than n-. If there is no indication of + or -, it means that there is no particular limitation on the doping concentration. The semiconductor layer located between the p-type and the n-type functions as a light absorbing layer (for example, i-type).

On the other hand, in order to further improve various characteristics of the first polycrystalline silicon layer 311, the second polycrystalline silicon layer 321 and the third polycrystalline silicon layer 331, these polycrystalline silicon layers are further subjected to heat treatment at a predetermined temperature, And a hydrogen passivation process in which the polycrystalline silicon layer is subjected to a hydrogen plasma treatment to remove dangling bonds present in the polycrystalline silicon layer.

As another example, the photoelectric element portion 300 may be a laminated structure (i.e., a tandem structure) in which another photoelectric element is further formed on one photoelectric element. That is, the photoelectric element unit 300 may have a structure in which a polycrystalline photoelectric element layer and an amorphous photoelectric element layer are stacked, a structure in which a microcrystalline photoelectric element layer and an amorphous photoelectric element layer are stacked, It should be understood that the meaning is inclusive.

Referring to FIG. 9, the present invention is applied as follows. If the photoelectric elements disposed at the bottom are referred to as first, second, and third semiconductor layers, and the photoelectric elements disposed at the top are referred to as fourth, fifth, and sixth semiconductor layers, The first semiconductor layer is disposed, the second, third, fourth, and fifth semiconductor layers are disposed on the semiconductor layer 320, and the sixth semiconductor layer is disposed on the semiconductor layer 330 to form a tandem structure Can be achieved.

Meanwhile, a connection layer (not shown), which is a transparent conductor, may be additionally formed between one photoelectric element and another photoelectric element in the photoelectric element portion 300 having a tandem structure. The connection layer may serve to improve the photoelectric conversion efficiency of the solar cell by causing ohmic contact between the stacked photoelectric devices (for example, between the polycrystalline photoelectric device and the amorphous photoelectric device). The connection layer is preferably made of AZO (ZnO: Al) in which a small amount of Al is added to ZnO, but it is not always limited thereto and a transparent conductive material such as ITO, ZnO, IZO, FTO (SnO ₂ : F) Can be used without restrictions.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, And it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

100: substrate
200: antireflection layer
310: first semiconductor layer (first amorphous silicon layer)
311: first polycrystalline silicon layer
320: second semiconductor layer (second amorphous silicon layer)
321: second polycrystalline silicon layer
330: third semiconductor layer (third amorphous silicon layer)
331: third polycrystalline silicon layer
400: electrode layer

Claims (14)

A substrate on which a unit solar cell region composed of a unit cell region and a wiring region is arranged;
A first semiconductor layer formed on the substrate and having a first trench formed on the wiring region on the substrate;
A second semiconductor layer formed on the first trench and the first semiconductor layer and having a second trench formed on the wiring region on the substrate to expose a portion of the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer and having a third trench formed on the wiring region on the substrate to expose a portion of the second semiconductor layer; And
An electrode layer formed on the third semiconductor layer and connected to the first semiconductor layer through the second trench,
And a second electrode. The method according to claim 1,
And an anti-reflection layer is further formed between the substrate and the first semiconductor layer. 3. The method of claim 2,
Wherein the antireflection layer comprises a structure in which the first trench is extended. 3. The method of claim 2,
Wherein the antireflection layer is silicon nitride (SiN _x ) or titanium nitride (TiN _x ). The method according to claim 1,
Wherein the first, second and third semiconductor layers are n, i, p or p, i, n. (a) providing a substrate on which unit solar cell regions composed of a unit cell region and a wiring region are arranged;
(b) forming a first semiconductor layer on the substrate;
(c) a first etching step of etching the first semiconductor layer on the wiring region to form a first trench to be separated from another adjacent unit solar cell region;
(d) sequentially forming a second semiconductor layer and a third semiconductor layer on the substrate including the first semiconductor layer;
(e) forming a first mask layer on the third semiconductor layer, etching the third semiconductor layer and the second semiconductor layer simultaneously on the wiring region using the first mask layer, A second etch step of forming a second trench exposing a portion;
(f) removing the first mask layer and forming an electrode layer on the substrate including the third semiconductor layer;
(g) forming a second mask layer on the electrode layer, etching the electrode layer and the third semiconductor layer simultaneously on the wiring region using the second mask layer to expose a portion of the second semiconductor layer, A third etching step of forming a trench; And
(h) removing the second mask layer
And a second electrode formed on the second electrode. The method according to claim 6,
And forming an anti-reflection layer between the substrate and the first semiconductor layer. 8. The method of claim 7,
Wherein the antireflection layer is etched simultaneously with the first semiconductor layer by the first etching step to extend the first trench. 8. The method of claim 7,
Wherein the antireflection layer is formed of silicon nitride (SiN _x ) or titanium nitride (TiN _x ). The method according to claim 6,
Wherein the first trench is etched by a laser scribing method. The method according to claim 6,
Wherein the second trench and the third trench are etched in a wet manner. The method according to claim 6,
Wherein the first, second, and third etching steps are performed on an upper portion of the substrate. The method according to claim 6,
Wherein the electrode layer is formed of a transparent conductive material or a metal material or a laminated structure thereof. The method according to claim 6,
Wherein the first, second, and third semiconductor layers are formed of n, i, p, or p, i, n.

Images