KR101451738B1 - Apparatus and method of liquid crystal display device - Google Patents

Abstract

The present invention relates to a technique for preventing a source-out-enable signal and a frame-source-out-enable signal from being generated adjacent to each other in a liquid crystal display device so that a flashing phenomenon occurs in a first line of a screen. The present invention predicts a situation where a source-out enable signal generated in a horizontal or vertical blank interval and a source-out enable signal generated in a frame interval are generated adjacent to each other at an end of a vertical-blank interval, A timing controller for interrupting a source-out enable signal; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel in response to a source-out enable signal supplied from the timing controller.

Source out enable signal, blank time

Description

TECHNICAL FIELD [0001] The present invention relates to a driving circuit and a method of a liquid crystal display device,

The present invention relates to a driving technique of a liquid crystal display, and more particularly, to a driving method of a liquid crystal display device, in which a source-out enable signal generated in a horizontal or vertical blank interval and a source-out enable signal generated in a frame interval are generated adjacent to each other, And more particularly, to a driving circuit and a driving method of a liquid crystal display device.

In recent years, as information technology (IT) has evolved, display has become more important as a visual information delivery medium. In order to prevail in the future, it is necessary to meet requirements such as low power consumption, thinning, light weight, and high image quality.

2. Description of the Related Art A liquid crystal display (LCD), which is a typical display device of a flat panel display, is an apparatus for displaying an image using optical anisotropy of a liquid crystal. Because of its advantages such as thinness, small size, low power consumption and high picture quality, Ray Tube (CRT)).

2. Description of the Related Art In general, a liquid crystal display device is a display device that supplies image information individually to pixels arranged in a matrix form, and can display a desired image by adjusting light transmittance of the pixels. Therefore, the liquid crystal display device includes a liquid crystal panel in which pixels, which are minimum units for realizing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. In addition, since the liquid crystal display device can not emit light by itself, a backlight unit for supplying light to the liquid crystal display device is provided.

FIG. 1 is a block diagram of a control signal generating unit included in a timing controller of a liquid crystal display apparatus. As shown in FIG. 1, a gate control signal generating unit for generating gate control signals GSP, GSC, and GOE for controlling driving of a gate driving unit (11); And a data control signal generator 12 for generating a data control signal SOE for controlling the driving of the data driver. The operation of the data control signal generator 12 will now be described with reference to FIG.

The gate control signal generator 11 generates a gate control signal based on an input data enable signal DE and a clock signal DCLK. As the gate control signals, there are a gate start pulse (GSP), a gate shift clock (GSC), a gate-out enable (GOE), and the like.

The data control signal generator 12 generates a data control signal based on the data enable signal DE and the clock signal DCLK. (SSP), a source shift clock (SSC), a source-out enable (SOE), and a polarity signal (POL) as the data control signals.

2 is a waveform diagram showing a principle of generating a source-out enable (SOE) on the basis of the data enable signal DE_LV in the data control signal generator 12. [

That is, the data control signal generator 12 generates a frame source-out enable signal SOE in synchronization with the horizontal blank H-blank of the data enable signal DE_LV.

The data control signal generation unit 12 generates a blank source enable signal SOE in a V-blank period in which a low level of the data enable signal DE_LV lasts for a predetermined time or more, .

However, sometimes the time (interval length) of the H-blank or V-blank changes in the system. In such a case, a blank source-out enable signal SOE and a frame source-out enable signal SOE may be generated adjacent to each other.

In other words, the source-out enable signal generated in the horizontal or vertical blank interval and the source-out enable signal generated in the frame interval can be generated in a contiguous manner.

Normally, the two adjacent blank source-out enable signals SOE and the frame-source-out enable signal SOE are generated at a normal separation distance, so that the output data Data Output of the first line of the second frame becomes "+ + "Polarity, which often occurs when they occur adjacent to each other and thus do not recognize the rear frame source-out enable signal SOE. In this case, as shown in FIG. 2, the output data (Data Output) of the first line of the second frame is not determined as the "++" polarity but is determined as the "+" polarity. As a result, only the first line of the frame has different charging characteristics, so that the line is sparkled.

As described above, in the conventional liquid crystal display device, the blank-source-out enable signal and the frame-source-out enable signal are generated adjacent to each other in the portion where the vertical-blank interval ends and the horizontal-blank interval starts. There is a problem that a screen glare phenomenon occurs due to a charging time difference in the first line of the frame.

Accordingly, it is an object of the present invention to provide a method and apparatus for controlling a vertical blanking interval and a horizontal blanking interval, wherein a source-out enable signal generated in a horizontal or vertical blank interval and a source- And to prevent a single source-out enable signal from being output.

According to an aspect of the present invention, there is provided a method for generating a frame enable signal, the method comprising: generating a source enable signal including a gate control signal, a blank source enable signal, and a frame source enable signal, When the blank source out enable signal and the frame source out enable signal generated in the vertical blank interval of the data enable signal are generated adjacent to each other at the end of the vertical blank interval, A timing controller for interrupting one of the frame source-out enable signals and outputting the source-out enable signal; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel in response to the gate control signal; And a data driver for outputting a pixel signal to each data line of the liquid crystal panel in response to the source-out enable signal.

According to another aspect of the present invention, there is provided a method of detecting a vertical blank interval of a data enable signal, Counting the vertical blank interval based on a time when the vertical blank interval is detected, and outputting a vertical blank interval count value; Comparing the vertical blank interval count value with a reference value, and outputting a generation control signal according to the comparison result; And outputting or interrupting a frame source output enable signal at the end of the vertical blank interval according to the generation control signal.

In the present invention, a source-out enable signal generated in a horizontal or vertical blank interval and a source-out enable signal generated in a frame interval are generated adjacent to each other in a portion where a vertical-blank interval ends and a horizontal- Out signal is not output from the first line of the frame, it is possible to reliably prevent the occurrence of a screen jitter phenomenon due to the difference in the charging time in the first line of the frame.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram illustrating a driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention. As shown in FIG. 3, the gate driving unit 120 and the data driving unit 130, And outputs a signal GDC and a data control signal DDC and predicts a situation in which a source-out enable signal generated in a horizontal or vertical blank interval and a source-out enable signal generated in a frame interval are generated adjacent to each other A timing controller 110 for interrupting one of the source-out enable signals; A gate driver 120 for outputting gate signals to the gate lines GL1 to GLn of the liquid crystal panel 140 in response to a gate signal control signal GDC supplied from the timing controller 110; A data driver 130 for supplying a pixel signal to each data line DL1 to DLm of the liquid crystal panel 140 in response to a data signal control signal DDC supplied from the timing controller 110; And a liquid crystal panel 140 for displaying an image by providing liquid crystal cells driven by the gate signal and the pixel signal in a matrix form.

The timing controller 110 includes a vertical blank section detector 111A for detecting a vertical blank section in the data enable signal and outputting a vertical blank section detection signal corresponding to the vertical blank section detection signal to the vertical blank section counter 111B; A vertical blank interval counter 111B for counting a vertical blank interval based on a time when the vertical blank interval detection signal is input from the vertical blank interval detection unit 111A; A source-out enable signal generation control section 111C for outputting the first and second generation control signals to the source-out enable signal generation section 111D based on the vertical blank interval count value of the vertical blank interval counter section 111B; ; Generates a blank source-out enable signal (Blank SOE) when the first generation control signal is input from the source-out enable signal generation control section 111C, and generates a blank source-out enable signal (Blank SOE) at the end of the vertical blank section And a source-out enable signal generator 111D for outputting or interrupting a frame source-out enable signal SOE.

The operation of the present invention thus constructed will be described in detail with reference to FIGS. 2, 4 and 5.

The timing controller 110 generates a gate control signal GDC for controlling the gate driving unit 120 and a data driving unit 130 using the vertical and horizontal synchronizing signals Hsync and Vsync and the clock signal DCLK supplied from the system, And outputs a data control signal (DDC) At the same time, the timing controller 110 samples digital pixel data (RGB) input from the system, rearranges the digital pixel data, and supplies the same to the data driver 130.

The gate control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate-out enable signal GOE. The data control signal DDC includes a source start pulse SSP, (SSC), a source-out enable (SOE), and a polarity signal (POL).

The gate driver 120 sequentially supplies the gate signal to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 110, ) Are turned on. Accordingly, the pixel signals supplied through the data lines DL1 to DLm are stored in the respective storage capacitors C _ST through the thin film transistors TFT.

In more detail, the gate driver 120 shifts the gate start pulse GSP according to the gate shift clock GSC to generate a shift pulse. In response to the shift clock, the gate driver 120 supplies a gate signal composed of a gate on / off period (signal) to the corresponding gate line GL for each horizontal period. In this case, the gate driver 120 supplies a gate-on signal only in an enable period in response to the gate-on enable signal GOE, and supplies a gate-off signal (gate-low signal) in other periods.

The data driver 130 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray level value in response to the data control signal DDC input from the timing controller 110 , And supplies the converted pixel signals to the data lines DL1 to DLm on the liquid crystal panel 140. [

To be more specific, the data driver 130 generates the sampling signal by shifting the source start pulse SSP according to the source shift clock. The data driver 130 sequentially receives and latches the pixel data RGB in units of a predetermined unit in response to the sampling signal. The data driver 130 converts the latched pixel data RGB into analog pixel signals and supplies the analog pixel signals to the data lines DL1 to DLm.

The liquid crystal panel 140 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC (TFT) connected to each of the TFTs.

The thin film transistor TFT is turned on when a gate signal is supplied from the gate line GL and supplies a pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when a gate off signal is supplied through the gate line GL, so that the pixel signal charged in the liquid crystal cell C _LC is maintained. The liquid crystal cell C _LC includes a common electrode and a pixel electrode connected to the thin film transistor TFT via a liquid crystal. The liquid crystal cell C _LC further includes a storage capacitor C _ST to maintain the charged pixel signal stably until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In such a liquid crystal cell C _LC , the alignment state of the liquid crystal having dielectric anisotropy is varied according to the pixel signal charged through the thin film transistor (TFT), so that the light transmittance is adjusted to realize the gradation.

The gate control signal generator 112 of the timing controller 110 generates a gate start pulse GSP as the gate control signal GDC using the data enable signal DE and the clock signal DCLK, Shift clock GSC, and gate-out enable GOE, and outputs it to the gate driver 120. [

The data control signal generator 111 of the timing controller 110 generates a data control signal DDC by using a source start pulse SSP, a source shift clock SSC, a source-out enable SOE, POL, and the like. The generation process of the SOE will be described in detail as follows.

The vertical blank section detecting section 111A checks the data enable signal DE_LV as shown in FIG. 5A to detect the vertical blank section and outputs the vertical blank section detecting signal to the vertical blank section counter section 111B (S1, S2)

For example, the vertical blank section detecting section 111A counts a 'low' section of the data enable signal DE_LV and recognizes the result as a horizontal blank section if the final count value is not greater than a predetermined value, And outputs the detected vertical blank section detection signal to the vertical blank section counter 111B.

Accordingly, the vertical blank interval counter 111B outputs a clock signal DCLK (see FIG. 5B) as a reference when the vertical blank interval detection signal is input from the vertical blank interval detector 111A, ) Is used to count the vertical blank section (S3)

At this time, the source-out enable signal generation control unit 111C divides the vertical blank interval count value of the vertical blank interval counter 111B into the horizontal blank interval of the blank data enable signal Blank DE as shown in (c) And outputs a first generation control signal to the source-out-enable-signal generating unit 111D each time the value is reached.

Thus, whenever the first generation control signal is input from the source-out-enable-signal generating control section 111C, the source-out enable signal generating section 111D generates a blank- And outputs the generated blank SOE to the data driver 130.

In addition, the source-out enable signal generation control unit 111C compares the total count value of the vertical blank interval in the vertical blank interval counter 111B with a preset reference value, and outputs a second generated control signal to the source Output enable signal generator 111D. Here, the reference value is a value set on the basis of VESA (S4)

That is, when the total count value of the vertical blank interval in the vertical blank interval counter 111B is compared with the preset reference value by the source-on-enable signal generation controller 111C, And outputs a second generation control signal to prevent the signal generator 111D from generating a frame source out enable signal (Frame SOE). (S5)

Accordingly, the source-out enable signal generator 111D does not generate or mask the frame source-out enable signal SOE at the end of the vertical blank interval when the above conditions are satisfied, SOE) is not output.

In this case, the source-out-enable-signal generating unit 111D generates the source-out-enable-signal generating unit 111D from the frame-source-out period starting from the end of the vertical blank interval and reaching the first horizontal blank interval as shown in FIGS. And generates an enable signal SOE.

If the total count value of the vertical blank section is compared with a preset reference value and they do not coincide with each other, if the source-out enable signal generator 111D generates the frame source-out enable signal Frame SOE , Which is located at a position adjacent to the blank source out enable signal (Blank SOE) generated at the end of the vertical blank section, as in the dotted rectangle portion of Fig.

In consideration of this, the present invention does not generate or mask the frame source-out enable signal SOE when the above conditions are met.

Of course, when the total count value of the vertical blank interval in the vertical blank interval counter 111B is compared with a preset reference value by the source-out enable signal generation control unit 111C, And outputs a second generation control signal to the generation unit 111D to generate a frame source out enable signal (Frame SOE) (S6)

At this time, the source-out enable signal generator 111D generates the frame source-out enable signal SOE at the end of the vertical blank interval, and outputs the frame-source-out enable signal SOE to the data driver 130. The frame source-out enable signal SOE generated under such a condition maintains a sufficient distance from the blank-source-out enable signal Blank SOE, so that it does not interfere with normal operation of the system.

1 is a block diagram of a control signal generating unit provided in a timing controller of a conventional liquid crystal display device.

2 (a) - (e) are waveform diagrams of respective parts of Fig. 1. Fig.

3 is a block diagram of a driving circuit of a liquid crystal display according to the present invention.

4 is a control flow chart of a method of driving a liquid crystal display according to the present invention.

5 (a) - (g) are waveform diagrams of respective parts of the data control signal generation section.

DESCRIPTION OF THE REFERENCE SYMBOLS

110: Timing controller

111: Data control signal generation unit

111A: Vertical blank section detector

111B: Vertical blank interval counter unit

111C: a source-out enable signal generation control section

111D: a source-out-enable-

112: Gate control signal generator

120: Gate driver

130: Data driver

140: liquid crystal panel

Claims (6)

A blank source enable signal generated from a horizontal blank interval of a data enable signal, and a blanking enable signal generated from a blank source enable signal generated from a blank source enable signal and a frame source out enable signal, When the frame source out enable signal generated in the vertical blank interval of the enable signal is generated adjacent to the end of the vertical blank interval, one of the blank source out enable signal and the frame source out enable signal is blocked A timing controller for outputting the source-out enable signal; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel in response to the gate control signal; And And a data driver for outputting a pixel signal to each data line of the liquid crystal panel in response to the source-out enable signal. 2. The timing controller according to claim 1, A vertical blank section detecting section for detecting a vertical blank section of the data enable signal and outputting a vertical blank section detecting signal; A vertical blank interval counter for counting the vertical blank interval based on a time point at which the vertical blank interval detection signal is input and outputting a vertical blank interval count value; A source-out enable signal generation control unit for outputting a first generation control signal and a second generation control signal in accordance with the vertical blank interval count value; And Generating a blank source out enable signal in response to the first generation control signal and outputting or blocking the frame source out enable signal at an end of the vertical blank interval in accordance with the second generation control signal, And an enable signal generator for generating an enable signal for driving the liquid crystal display panel. 3. The method of claim 2, Wherein the source-out enable signal generation control unit is configured to compare the vertical blank interval count value output from the vertical blank interval counter unit with a VESA reference value, and output the second generation control signal according to the comparison result. A driving circuit of a display device. The method of claim 3, When the vertical blank interval count value matches the VESA reference value, the source-out-enable-signal control unit outputs the second generation control signal to output the frame-source-out enable signal, Wherein if the vertical blank interval count value does not match the VESA reference value, the source-out enable signal generation controller outputs the second generation control signal so as not to output the frame-source-out enable signal. Drive circuit of the device. Detecting a vertical blank interval of the data enable signal; Counting the vertical blank interval based on a time when the vertical blank interval is detected, and outputting a vertical blank interval count value; Comparing the vertical blank interval count value with a reference value, and outputting a generation control signal according to the comparison result; And And outputting or blocking a frame source out enable signal at the end of the vertical blank interval according to the generation control signal. 6. The method of claim 5, And the reference value is a VESA reference value.

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