KR101441393B1 - Light emitting display device - Google Patents

Abstract

The present invention relates to a light emitting display device capable of improving display quality by minimizing a pixel charging time and supplying an accurate data current to a pixel region of a display panel.

A light emitting display according to the present invention includes an active region including a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits formed in a region where a plurality of switching lines cross each other, and a plurality of data lines and at least one dummy gate A display panel in which a dummy area including dummy circuits formed in regions where lines intersect is formed; A gate driving circuit for supplying a gate signal to the gate line and supplying a switching signal to the switching line; A data driving circuit for supplying a first or second data current to the data line; A timing controller for supplying a control signal and a dummy control signal for controlling the gate driving circuit and the data driving circuit; And a dummy selector for supplying a control signal to the dummy gate line in accordance with a dummy control signal of the timing controller, wherein the dummy circuit includes: at least one dummy gate line parallel to the gate line; At least one dummy switching element connected to the dummy gate line and a data line extending in the dummy area and turned on in a precharging period in accordance with a dummy control signal of the dummy selector; And at least one dummy load for providing a load to the data line according to the state of the dummy switching element.

A data current, a data driving circuit,

Description

[0001] LIGHT EMITTING DISPLAY DEVICE [0002]

The present invention relates to a light emitting display device, and more particularly, to a light emitting display device capable of improving display quality by minimizing a pixel charging time and supplying an accurate data current to a pixel region of a display panel.

2. Description of the Related Art Generally, a light emitting display is a display device for electrically exciting a fluorescent organic compound to emit light. The N x M light emitting cells are voltage-written or current-written to express an image. 1, when a voltage is applied between the anode 10 and the cathode 20, electrons generated from the cathode 20 pass through the electron injection layer 50 and / And is moved toward the organic light emitting layer 30 through the electron transporting layer 60. The holes generated from the anode 10 move toward the organic light emitting layer 30 through the hole injection layer 70 and the hole transport layer 40. Accordingly, in the organic light emitting layer 30, electrons supplied from the electron transport layer 60 and the hole transport layer 40 collide with each other and recombine to generate light. The light is emitted to the outside through the anode 10 And an image is displayed.

There are a passive matrix method and an active matrix method using a thin film transistor (TFT) as a method of driving the light emitting cells. In the simple matrix method, an anode and a cathode are formed to be orthogonal to each other and a line is selected and driven. In the active driving method, a thin film transistor is connected to each ITO (indium tin oxide) pixel electrode and a capacitor capacity connected to the gate of the thin film transistor It is driven by the maintained voltage.

At this time, the active driving method is divided into a voltage programming method and a current programming method depending on the type of signal applied to write a voltage to the capacitor.

There is a problem that it is difficult to obtain a high gradation due to a variation in threshold voltage (Vth) and carrier mobility of a thin film transistor caused by the nonuniformity of the manufacturing process in the pixel circuit of the conventional voltage writing method. For example, when driving a thin film transistor of a pixel at 3 V, a voltage should be applied to the gate of the thin film transistor at an interval of 12 mV (= 3 V / 256) or less in order to express 8 bits (256) When the deviation of the threshold voltage of the thin film transistor due to the unevenness is 100 kV, it becomes difficult to express the high gray level.

On the contrary, the current writing type pixel circuit can obtain a uniform display characteristic even if the driving transistor in each pixel has non-uniform voltage-current characteristics, if a current source for supplying current to the pixel circuit is uniform throughout the panel.

2 is a schematic view of a conventional light emitting display.

2, the conventional light emitting display device includes a display panel 72 having pixels 84 arranged in the regions defined by the intersections of the gate lines GL and the data lines DL, A data driving circuit 74 and a data driving circuit 74 for driving the data lines DL of the display panel 72 and a gate driving circuit 74 for driving the gate lines GL of the display panel 72, And a timing controller 76 for controlling the flow path 78.

In the display panel 72, the pixels 84 are arranged in a matrix form. The display panel 72 is provided with a supply pad 72 for receiving a high potential voltage from an external high potential voltage source VDD and a base pad 82 for receiving a ground voltage from an external base voltage source GND do. (For example, the supply voltage source VDD and the ground voltage source GND may be supplied from the power supply unit). The high potential voltage supplied to the supply pad 80 is supplied to each of the pixels 84. The base low voltage supplied to the base pad 82 is also supplied to each of the pixels 84.

The gate driving circuit 78 supplies a gate signal to the gate lines GL to sequentially drive the gate lines GL.

The data driving circuit 74 converts the digital data signal input from the timing controller 76 into an analog data signal. The data driving circuit 74 supplies the analog data signal to the data lines DL each time the gate signal is supplied.

The timing controller 76 generates a data control signal for controlling the data driving circuit 74 and a gate control signal for controlling the gate driving circuit 78 using a plurality of synchronization signals. The data control signal generated by the timing controller 76 is supplied to the data driving circuit 74 to control the data driving circuit 74. The gate control signal generated in the timing controller 76 is supplied to the gate drive circuit 22 to control the gate drive circuit 22. [

Each of the pixels 84 receives a data signal from the data line DL when a gate signal is supplied to the gate line GL and generates light corresponding to the data signal. 3, each of the pixels 84 includes a light emitting element OLED having a cathode connected to a ground voltage source GND, a gate line GL, a data line DL, and a high potential And a cell drive circuit 86 connected to the voltage source VDD and connected to the anode of the light emitting element OLED to drive the light emitting element OLED.

The cell driving circuit 86 includes a switching TFT T1 having a gate terminal connected to the gate line GL, a source terminal connected to the data line DL and a drain terminal connected to the node N, A driving TFT T2 having a gate terminal connected to the high potential source VDD and a drain terminal connected to the light emitting element OLED, (C).

The switching TFT Tl is turned on when a gate signal is supplied to the gate line GL to supply a data signal supplied to the data line DL to the node N. [ The data signal supplied to the node N is charged to the capacitor C and supplied to the gate terminal of the driving TFT T2. The driving TFT T2 controls the amount of light emitted from the light emitting element OLED by controlling the amount of current I supplied from the high potential source VDD to the light emitting element OLED in response to the data signal supplied to the gate terminal.

Since the data signal is discharged from the capacitor C even when the switching TFT T1 is turned off, the driving TFT T2 supplies the current I from the high potential voltage source VDD until the data signal of the next frame is supplied And supplies the light to the light emitting device OLED so that the light emitting device OLED maintains the light emission. Here, the actual cell drive circuit 86 may be set in various structures other than the above-described structure.

The light-emitting display device of the current driving type configured as described above has a problem that when the current supplied through the data line is supplied to the first pixel portion and the last pixel portion is supplied due to a small driving current in the low gradation display, A problem of falling occurs. Therefore, in order to solve such a problem, a method of pre-charging by supplying a specific voltage in advance before the actual data signal is supplied to the data line is used. However, in the method of pre-charging, And additional circuits for supplying the precharging voltage are required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide a light emitting display device capable of improving display quality by minimizing a pixel charging time and supplying an accurate data current.

A light emitting display according to an embodiment of the present invention includes an active region including a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits formed in a region where a plurality of switching lines cross each other, A display panel in which a dummy region including dummy circuits formed in an intersecting region of one dummy gate line is formed; A gate driving circuit for supplying a gate signal to the gate line and supplying a switching signal to the switching line; A data driving circuit for supplying a first or second data current to the data line; A timing controller for supplying a control signal and a dummy control signal for controlling the gate driving circuit and the data driving circuit; And a dummy selector for supplying a control signal to the dummy gate line in accordance with a dummy control signal of the timing controller, wherein the dummy circuit includes: at least one dummy gate line parallel to the gate line; At least one dummy switching element connected to the dummy gate line and a data line extending in the dummy area and turned on in a precharging period in accordance with a dummy control signal of the dummy selector; And at least one dummy load for providing a load to the data line according to the state of the dummy switching element.

A light emitting display according to another embodiment of the present invention includes a display panel including an active region including a plurality of pixel circuits formed in a region where a plurality of data lines, a plurality of gate lines, and a plurality of switching lines cross each other; A gate driving circuit for supplying a gate signal to the gate lines and supplying a switching signal to the switching lines; A data driving circuit for supplying a first or second data current to the data line; And a timing controller for supplying a control signal and a dummy control signal for controlling the gate driving circuit and the data driving circuit, the dummy data line being connected to one side of the display panel, the dummy data line connected to the data line, A dummy panel in which a dummy circuit is formed; And a dummy selection section for supplying a dummy control signal to a dummy gate line of the dummy panel, wherein the dummy circuit includes: at least one dummy gate line parallel to the gate line; At least one dummy switching element connected to the dummy gate line and the dummy data line and turned on in a precharging period in accordance with a dummy control signal of the dummy selector; And at least one dummy load for providing a load to the data line according to the state of the dummy switching element.

The pixel circuit includes first and second switching elements for transferring a first data current supplied through the data line during a precharging period in accordance with a switching signal of the gate driving circuit; A driving thin film transistor driven by a data voltage corresponding to the first data current supplied from the first and second switching elements; A first storage capacitor for storing a data voltage corresponding to a first data current supplied by the first and second switching elements; A light emitting element for emitting light corresponding to a second data current applied from the driving switching element; And a third switching element for transmitting a second data current supplied from the driving thin film transistor to the light emitting element in response to a gate signal applied to the gate line.

delete

And each of the dummy loads is the same as the load of the pixel circuit responsive to a gate signal applied to the gate line.

And the first data current is supplied to a data line of the dummy area.

Wherein the first data current supplied to the data line includes a current (I) supplied to the pixel circuit selected by the gate signal in accordance with a current distribution law and a dummy load (N) of a dummy circuit selected by the dummy selector (I x (N + 1)).

And the second data current is supplied to the data line of the active region.

And at least one lookup table stored by making a current value of a first data current supplied to the pixel circuit and the dummy circuit of the dummy panel into a lock-up table.

The light emitting display according to the present invention is characterized in that the data current supplied to the pixel circuits of the active region connected to the respective data lines of the display panel is divided into data currents to be supplied to the dummy circuits connected to the data lines in the dummy region I (1 + N)) (where I is a current supplied to each pixel circuit and each dummy circuit, and N is the number of dummy gate lines), it is possible to supply an accurate data current to each pixel circuit , And the pixel charging time of each pixel circuit can be minimized (1 / N).

In implementing a low gradation in a large-sized display panel, a pre-charging voltage approximate to a data voltage of a target value to be realized when a current is applied to the first pixel circuit connected to the data line and the last pixel circuit is supplied The supply of accurate data current and the charging time of each pixel circuit are minimized, so that a low gradation can be realized in a large-area display panel and the display quality of the light-emitting display device can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

4 is a view illustrating a light emitting display according to a first embodiment of the present invention.

4, the light emitting display according to the first embodiment of the present invention includes a plurality of data lines DL1 to DLm, a plurality of gate lines GL1 to GLn, and a plurality of switching lines SW1 to SWn, And a plurality of data lines DL1 to DLm and at least one dummy gate line Dum1 to DumN intersect each other in a region where the data lines DL1 to DLm intersect with each other, A gate driving circuit 112 for supplying a gate signal and a switching signal to the gate line GL and a gate driving circuit 112 for supplying a gate signal and a switching signal to the gate line GL, A data driving circuit 110 for supplying a first or a second data current to the data driving circuits 110 and 112 and a timing controller 112 for supplying a control signal and a dummy control signal for controlling the gate driving circuit and the data driving circuits 110 and 112, (108) and timing And a dummy selection unit 114 for supplying a control signal to the dummy gate lines Dum1 to DumN in accordance with the dummy control signal Dum_CS of the controller 108. [

The display panel 106 includes an active region 102 in which an image is displayed and a dummy region 104 for controlling data current supply.

The active region 102 includes a plurality of pixel circuits 116 formed in a plurality of pixel regions where a plurality of data lines DL1 to DLm, a plurality of gate lines GL1 to GLn, and a plurality of switching lines SW1 to SWn cross each other. ). 1, when a voltage is applied between the anode 10 and the cathode 20, the electrons generated from the cathode 20 are injected into the light emitting element 120 formed in each pixel region, The electron transport layer 50 and the electron transport layer 60 to the emission layer 30. [ The holes generated from the anode 10 move toward the light emitting layer 30 through the hole injecting layer 70 and the hole transporting layer 40. Accordingly, in the light emitting layer 30, electrons supplied from the electron transporting layer 60 and the hole transporting layer 40 collide with each other and recombine with each other to generate light. The light is emitted to the outside through the anode 10 An image is displayed.

5, the pixel circuit 116 includes a gate driving circuit 112 for transferring a first data current Idata1 supplied through a data line DL during a precharging period in accordance with a switching signal of the gate driving circuit 112, 1 and second switching elements Tsw1 and Tsw2 and a driving thin film transistor Tdrv driven by a data voltage corresponding to a first data current supplied from the first and second switching elements Tsw1 and Tsw2, A first storage capacitor Csto for storing a data voltage corresponding to a first data current supplied by the first and second switching elements Tsw1 and Tsw2 and a second storage capacitor Csto for storing a data current corresponding to a second data current supplied from the drive switching element Tdrv A third switching part for transferring a second data current supplied from the driving thin film transistor Tdrv to the light emitting element 120 in response to a gate signal applied to the light emitting element 120 and the gate line GL, The element Tsw3 It is configured to hereinafter.

The dummy region 104 is a region in which a plurality of dummy gate lines Dum1 to DumN intersect with a data line DL extended from the plurality of data lines DL1 to DLm to the dummy region 104 of the active region 102 And a dummy circuit 118 formed in the dummy pixel region.

The dummy circuit 118 includes at least one dummy gate line Dum1 to DumN parallel to the gate line GL and dummy gate lines Dum1 to DumN and a dummy region 104, At least one dummy switching element 124 connected to the data line extended in the dummy switching element 124 and driven in accordance with the dummy control signal Dum_CS of the dummy selector 114, And at least one dummy load 122 for providing a load to the dummy load 122.

The data driving circuit 110 precharges the plurality of data lines DL1 to DLm to a voltage level corresponding to the first data current Idata1 and then charges the plurality of data lines DL1 to DLm with the second data current Idata2 ). In other words, the data driving circuit 110 includes a voltage source and a current source. In the precharging operation, the data driving circuit 110 connects the plurality of data lines DL1 to DLm to a voltage source and supplies a voltage level corresponding to the first data current Idata1 And the second data current Idata2 supplied through the current source to the plurality of data lines DL1 to DLm is supplied when the actual data is output. At this time, the first data current Idata1 output from the data driving circuit 110 is supplied to the data line DL connected to the dummy circuit 118 of the dummy region 104.

The gate driving circuit 112 sequentially applies a switching signal for selecting the pixel circuits 116 to the plurality of switching lines SW1 to SWn. The gate driving circuit 112 sequentially supplies a gate signal for controlling the light emitting period of the pixel circuit 116 to the plurality of gate lines GL1 to GLn.

The gate drive circuit 112 and the data drive circuit 110 may be electrically connected to the display panel 106 and may be electrically connected to the display panel 106 by a tape carrier package ) In the form of a chip or the like. It may also be mounted on a flexible printed circuit (FPC) or a film, which is bonded to the display panel 106 and electrically connected, in the form of a chip or the like. The gate driving circuit 112 and the data driving circuit 110 may be mounted directly on the glass substrate (not shown) of the display panel 106. [

The timing controller 108 arranges the source data (R, G, B) supplied from the outside into data signals suitable for driving the display panel 106 and supplies the aligned data signals to the data driving circuit 110. The timing controller 108 receives the data driving control signal DDS and the gate driving control signal DDS using the main clock DCLK, the data enable signal DE and the horizontal and vertical synchronizing signals Hsync and Vsync input from the outside. Signal GDS to control the driving timings of the data driver 110 and the gate driver 112, respectively.

The timing controller 108 supplies the dummy control signal Dum_CS to the dummy selector 114 in the precharging period supplied from the data driver 110 to the plurality of data lines DL1 to DLm.

The dummy selection unit 114 supplies a switching signal to at least one dummy switching element 122 connected to the dummy gate lines Dum1 to DumN in accordance with the dummy control signal Dum_CS supplied from the timing controller 108. [ The dummy selection unit 114 turns on at least one dummy switching device 124 when the first data current Idata2 is supplied to the plurality of data lines DL1 to DLm during the precharging period, So that at least one dummy load 122 can be connected to the data line DL. At this time, the load applied to the dummy load 112 of the dummy circuit 118 may be the same as the load applied to the pixel circuit 116.

5 to 7, a process of driving the pixel circuit 116 of the light emitting display device constructed as described above will be described in detail. First, a precharge operation (Pre) in which a data signal is supplied from the data driving circuit 110 -charging period, the first and second switching elements Tsw1 and Tsw2 are turned on by the switching signal of the switching line SWn, as shown in Fig.

The driving thin film transistor Tdrv is switched to the diode connection state by the first and second switching elements Tsw1 and Tsw2 and the first data supplied from the data driving apparatus 110 to the data line DL A data voltage corresponding to the current Idata1 is supplied through the first and second switching elements Tsw1 and Tsw2 and is stored in the storage capacitor Csto. At this time, the first data current Idata1 is supplied with a current of Ix (1 + N) in consideration of the data current supplied to the dummy circuit 118 to the current I supplied to the conventional pixel circuit 116, The current charging rate in the capacitor Csto is shortened to 1 / N or more as compared with the conventional case.

The first and second switching elements Tsw1 and Tsw2 are turned off when the charging of the data voltage to the storage capacitor Csto is completed and during the input of the real data, The third switching element Tsw3 is turned on by the gate signals of the gate lines GL1 to GLn. At this time, the second data current Idata is supplied to the light emitting element 120 through the third switching element Tsw3 so that the light emitting element 120 emits light.

The light emitting display device driven in this manner is configured to apply the data current supplied to the pixel circuit 116 of the active region 102 connected to each data line DL of the display panel 106 to the dummy region 104 (I × (1 + N)) (where I is a current supplied to each pixel circuit and each dummy circuit, and N is a dummy gate line connected to a data line DL) The correct data current can be supplied to each pixel circuit 116 and the pixel charging time of each pixel circuit 116 can be minimized (1 / N).

In implementing a low gradation in a large-sized display panel, a pre-charging voltage approximate to a data voltage of a target value to be realized when a current is applied to the first pixel circuit connected to the data line and the last pixel circuit is supplied The supply of accurate data current and the charging time of each pixel circuit are minimized, so that a low gradation can be realized in a large-area display panel and the display quality of the light-emitting display device can be improved.

8 is a view illustrating a light emitting display according to a second embodiment of the present invention.

8, the light emitting display according to the second embodiment of the present invention includes a plurality of data lines DL1 to DLm, a plurality of gate lines GL1 to GLn, and a plurality of switching lines SW1 to SWn, A display panel 204 including an active region including a plurality of pixel circuits 116 formed in the intersecting region; a display panel 204 including gate lines GL1 to GLn and gate lines SW1 to SWn; A data driving circuit 110 for supplying a first or second data current to the data line DL and a gate driving circuit 110 for supplying a switching signal to the data driving circuits 110 and 112 The dummy data lines Dum_DL1 to Dum_DLm connected to the data line DL and the dummy data lines Dum_DL1 to Dum_DLm connected to one side of the display panel 204 and the dummy data lines Dum1 to Dum_DLm, DumN) is formed in the intersection area with a dummy circuit A dummy selection section 114 and a pixel circuit 116 for supplying a dummy control signal Dum_CS to the dummy gate lines Dum1 to DumN of the dummy panel 206; Up table of the current value of the dummy circuit 118 of the panel 206 and the current value applied to the load 122 of the dummy circuit 118 in the first data current supplied is stored in the at least one lookup table 202).

The light emitting display device having such a structure is configured such that the display panel 204 in which the pixel circuit is formed in the active area and the dummy panel 206 are formed so as to be separable from each other and the current value of the data current supplied to the dummy panel 206 is looked up Except for the table lookup table 202, has the same configuration as that of the first embodiment of the present invention described above, so that the description of the same configuration will be replaced with the above description.

The display panel 204 includes a pixel circuit 116 formed in a plurality of pixel regions where a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn cross each other. At this time, a data pad unit (not shown) connected to the plurality of data lines DL1 to DLm is formed on one side of the display panel 204. [

The dummy panel 206 is formed to be connected to the plurality of data lines DL1 to DLm of the active area. The dummy panel 206 includes a dummy circuit 118 formed in a region where a plurality of dummy data lines Dum_DL1 to Dum_DLm and a plurality of dummy gate lines Dum1 to DumN cross each other. At this time, the dummy panel 206 includes a dummy data pad unit (not shown) for connecting the plurality of data lines DL1 to DLm of the display panel 204 to one side.

The data pad portion formed on one side of the display panel 204 is connected to the dummy data pad portion of the dummy panel 206 and is supplied with the data current supplied from the data driving circuit 110. At this time, an FPC 200 or the like is connected between the data pad portion of the display panel 204 and the data pad portion of the dummy panel 206.

The dummy circuit 118 is connected to the dummy gate lines Dum1 to DumN and the dummy data lines Dum_DL1 to Dum_DLm at least one dummy gate line Dum1 to DumN parallel to the gate line GL, At least one dummy switching element 124 which is driven according to a dummy control signal Dum_CS of the dummy switching element 114 and at least one dummy switching element 124 which provides a load to the data line DL in accordance with the state of the dummy switching element 124. [ (122).

The lookup table 202 measures data currents suitable for the data signals on the data lines DL and stores them in a look-up table. In other words, the lookup table 202 measures the value of the first data current Idata1 supplied to the data line DL in accordance with the data signal and supplies the current value stored in the lookup table 202 to the timing controller 108).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1 to 3 show a conventional light emitting display.

4 is a view illustrating a light emitting display according to a first embodiment of the present invention.

5 is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention.

6 illustrates a dummy load according to a first embodiment of the present invention.

7 is a waveform diagram according to the first embodiment of the present invention;

8 is a view illustrating a light emitting display according to a second embodiment of the present invention.

Description of the Related Art

102: active area 104: dummy area

106: display panel 108: timing controller

110: Data driving circuit 112: Date driving circuit

114: dummy selection unit 120: light emitting element

Claims (9)

An active region including a plurality of data lines, a plurality of pixel circuits formed in a region where a plurality of gate lines and a plurality of switching lines cross each other, and an active region formed in an intersection region of the plurality of data lines and the at least one dummy gate line A display panel on which a dummy area including dummy circuits is formed; A gate driving circuit for supplying a gate signal to the gate line and supplying a switching signal to the switching line; A data driving circuit for supplying a first or second data current to the data line; A timing controller for supplying a control signal and a dummy control signal for controlling the gate driving circuit and the data driving circuit; And And a dummy selector for supplying a control signal to the dummy gate line in accordance with the dummy control signal of the timing controller, The dummy circuit includes: At least one dummy gate line parallel to the gate line; At least one dummy switching element connected to the dummy gate line and a data line extending in the dummy area and turned on in a precharging period in accordance with a dummy control signal of the dummy selector; And at least one dummy load for providing a load to the data line according to a state of the dummy switching device. A display panel including an active region including a plurality of pixel circuits formed in a region where a plurality of data lines, a plurality of gate lines, and a plurality of switching lines cross each other; A gate driving circuit for supplying a gate signal to the gate lines and supplying a switching signal to the switching lines; A data driving circuit for supplying a first or second data current to the data line; And a timing controller for supplying a control signal and a dummy control signal for controlling the gate driving circuit and the data driving circuit, A dummy panel connected to one side of the display panel, the dummy panel being formed by intersecting a dummy data line connected to the data line and a dummy gate line; And a dummy selector for supplying a dummy control signal to a dummy gate line of the dummy panel, The dummy circuit includes: At least one dummy gate line parallel to the gate line; At least one dummy switching element connected to the dummy gate line and the dummy data line and turned on in a precharging period in accordance with a dummy control signal of the dummy selector; And at least one dummy load for providing a load to the data line according to a state of the dummy switching device. 3. The method according to claim 1 or 2, The pixel circuit includes: First and second switching elements connected between the switching line and the data line for transmitting a first data current supplied through the data line in the precharging period in accordance with a switching signal of the gate driving circuit; A first storage capacitor connected between the second switching device and a ground voltage source and storing a data voltage corresponding to a first data current supplied by the first and second switching devices; A driving thin film transistor connected to the first storage capacitor and driven by a data voltage corresponding to the first data current supplied from the first and second switching elements; A third switching element connected between the gate line and the driving thin film transistor, for transferring a second data current supplied from the driving thin film transistor in response to a gate signal applied to the gate line; And And a light emitting element which is connected between the third switching element and the high potential voltage source and emits light corresponding to a second data current supplied from the driving thin film transistor through the third switching element. Display device. delete The method of claim 3, Wherein each of the dummy loads is the same as the load of the pixel circuit in response to a gate signal applied to the gate line. The method of claim 3, Wherein the first data current is supplied to a data line of the dummy region. The method according to claim 6, Wherein the first data current supplied to the data line (Ix (N + 1)), taking into account the current (I) supplied to the pixel circuit selected by the gate signal and the dummy load (N) of the dummy circuit selected by the dummy selection section, Emitting display device. The method of claim 3, And the second data current is supplied to a data line of the active region. 3. The method of claim 2, And at least one lookup table stored in a lock-up table of a current value of a first data current supplied to the pixel circuit and a dummy circuit of the dummy panel.

Images