KR101327500B1 - Flash memory devices including multi-layer tunnel insulator and method of fabricating the same - Google Patents

Abstract

A flash memory device including a tunnel insulating film formed in multiple layers and a manufacturing method thereof are described. A flash memory device according to an embodiment of the present invention includes a lower tunnel insulating film formed on a substrate, an upper tunnel insulating film which is an amorphous oxide formed on a lower tunnel insulating film, a P-type floating gate formed on an upper tunnel insulating film, and a P-type floating gate. An inter-gate insulating film formed on the substrate, and a control gate formed on the inter-gate insulating film.

Flash Memory, Tunnel Insulation, Amorphous Silicon, Silicon-Rich-Oxide, P-type Gate

Description

Flash memory devices including multi-layer tunnel insulator and method of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash memory devices, and more particularly, to a flash memory device including a tunnel insulating film formed in multiple layers and a method of manufacturing the same.

Among the various items for evaluating the characteristics of the flash memory device, it is particularly important to evaluate the characteristics of the tunnel insulating film. The tunnel insulating film is an insulating film in which numerous electrons tunnel when writing information to the floating gate or deleting information stored from the floating gate, and is a very important film for evaluating the characteristics of a flash memory device. Tunneling insulating film should be considered comprehensively in terms of insulation, dielectric constant, thickness, flexibility, thermal stability, film bonding, and density, and more importantly, relatively inexpensive processes used in general semiconductor processes It must be compatible. For these reasons, a silicon oxide film has conventionally been used as the tunnel insulating film. This is because the silicon oxide film satisfies most of the consideration conditions that the tunnel insulating film must have above a certain level, and because it is an inexpensive process because it is a film quality widely used in semiconductor processes.

However, as the degree of integration of flash memory devices increases, the films and the structure of the flash devices are changing. For example, the conductor is gradually changed to a metallic material, the structure is also changed, and in particular, various film qualities are being used other than the silicon oxide film and silicon nitride film, which are widely used.

The tunnel insulating film should theoretically become thinner as the integration degree of the flash memory device increases. Increasing the density of flash memory devices reduces the size of each component, so that they must operate at low power to prevent degradation, and therefore must have stable programming, erasing, and information retention capabilities at low voltages and low currents. to be.

However, the problem of forming a thin tunnel insulating film is not easy. If the tunnel insulating film is too thin, first, the manufacturing process has a great difficulty, and from the electrical point of view, electrons stored in the floating gate leak through the tunnel insulating film to degrade information retention characteristics of the flash memory device. For this reason, the tunnel insulating film must have an appropriate thickness electrically. With conventional silicon oxide films, it is difficult to satisfy both characteristics at the same time that the tunneling of electrons is easy, so that programming and erasing is performed at low voltage, and that the information retention characteristic of maintaining stored information is also stabilized.

As a method for improving the characteristics of the tunnel insulating film, an insulating film having high dielectric properties such as hafnium oxide, aluminum oxide, titanium oxide, and tantalum oxide can be solved by forming a thin film, but widely used in semiconductor manufacturing processes. It is not a material to be formed, nor is it formed of a common material, so forming a film is an unstable and expensive process. In addition, the interface properties with silicon substrates and other conductor materials are poor, and most of all, they are susceptible to heat and are difficult to introduce into semiconductor manufacturing processes that frequently use high temperature processes.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a flash memory device including a multilayer tunnel insulating layer having excellent information retention while programming and erasing at a low voltage.

Another object of the present invention is to provide a method of manufacturing a flash memory device including a multilayer tunnel insulating film having excellent information retention capability while programming and erasing at a low voltage.

Another object of the present invention is to provide a flash memory device and a method of forming a multilayer tunnel insulating film with materials having various energy band gaps so that programming and erasing at low voltage is easy and information holding ability is excellent. .

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

Flash memory device according to an embodiment of the present invention for achieving the problem to be solved by the present invention, the lower tunnel insulating film formed on the substrate, the upper tunnel insulating film formed on the lower tunnel insulating film, P formed on the upper tunnel insulating film A type floating gate, an inter-gate insulating film formed on the P-type floating gate, and a control gate formed on the inter-gate insulating film.

Flash memory device according to another embodiment of the present invention for achieving the problem to be solved by the present invention, the lower tunnel insulating film formed on the substrate, the upper tunnel insulating film formed on the lower tunnel insulating film, the charge formed on the upper tunnel insulating film And a trapping insulating film, a blocking film formed on the charge trap insulating film, a P-type gate electrode formed on the blocking film, and an insulating capping film formed on the P-type gate electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a flash memory device, which includes forming a lower tunnel insulating film on a substrate and forming an upper tunnel insulating film on a lower tunnel insulating film. Forming a P-type floating gate on the upper tunnel insulating film, forming an inter-gate insulating film on the P-type floating gate, and forming a control gate on the inter-gate insulating film.

According to another aspect of the present invention, there is provided a method of manufacturing a flash memory device, wherein a lower tunnel insulating film is formed on a substrate, and an upper tunnel insulating film is formed on a lower tunnel insulating film. Forming a charge trap insulating film on the upper tunnel insulating film, forming a blocking film on the charge trap insulating film, forming a P-type gate electrode on the blocking film, and forming an insulating capping film on the P-type gate electrode. .

According to another aspect of the present invention, there is provided a flash memory device including a multilayer tunnel insulating film formed on a substrate, a first gate electrode formed on the multilayer tunnel insulating film, and a first gate electrode. And a second gate electrode formed on the inter-gate insulating film, wherein the multilayer tunnel insulating film includes a first tunnel insulating film having a first energy band gap, and a second energy different from the first energy band gap. And a second tunnel insulating film having a band gap.

According to another aspect of the present invention, there is provided a flash memory device including a multilayer tunnel insulating film formed on a substrate, a charge trap insulating film formed on a multilayer tunnel insulating film, and a charge trap insulating film. A blocking film formed, and a gate electrode formed on the blocking film, wherein the multilayer tunnel insulating film includes a first tunnel insulating film having a first energy band gap, and a second tunnel insulating film having a second energy band gap.

The details of other embodiments are included in the detailed description and drawings.

As described above, the flash memory device including the multilayer tunnel insulating layer according to the exemplary embodiments of the present invention may have stable programming and erasing characteristics at the programming and erasing voltage levels, and stable information retaining characteristics at the information holding voltage levels. Can be.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be embodied in various forms, and these embodiments are not intended to be exhaustive or to limit the invention to the precise forms disclosed, Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.

Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

In the present specification, when a non-insulating film, for example, an undoped silicon film is applied as the tunnel insulating film, it is described as an insulating film for convenience in order to make the technical spirit of the present invention easier to understand.

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a technique for improving the characteristics of a tunnel insulating film by adjusting an energy band gap of a tunnel insulating film through which charge tunnels in a flash memory device. This technique is called energy band gap engineering or energy barrier engineering. This technique is such that the energy barrier of the tunnel insulation layer is kept high when the flash memory device performs the read operation in the normal state, and the energy barrier of the tunnel insulation layer is lowered when the programming / erasing operation is performed.

Therefore, the information holding characteristic is excellent in the normal state, and the tunneling characteristic is improved in the programming / erasing operation state.

This technique involves forming tunnel insulating films that are relatively thick physically but relatively thin electrically.

Hereinafter, a flash memory device and a method of manufacturing the same according to embodiments of the present invention will be described with reference to the accompanying drawings.

1A and 1B are longitudinal cross-sectional views of a unit cell 100 of a flash memory device according to an embodiment of the present invention. In particular, FIG. 1A is a longitudinal sectional view of the XZ plane along the X and Z directions, and FIG. 1B is a longitudinal sectional view of the YZ plane along the Y and Z directions. The X, Y and Z directions may be perpendicular to each other.

Referring to FIG. 1A, a unit cell 100 of a flash memory device according to an exemplary embodiment may include a tunnel insulating layer 130 and a floating gate including a lower tunnel insulating layer 131 and an upper tunnel insulating layer 135. 140, an inter-gate insulating layer 150, a control gate 160, and a capping layer 170.

The lower tunnel insulating layer 131 may be formed on the substrate 110, the upper tunnel insulating layer 135 may be formed on the lower tunnel insulating layer 131, and the floating gate 140 may be formed on the upper tunnel insulating layer 135. The inter-gate insulating film 150 may be formed on the floating gate 140, the control gate 160 may be formed on the inter-gate insulating film 150, and the capping film 170 may be formed on the inter-gate insulating film 150. Surrounds an upper surface of the control gate 160, and a portion may be in contact with the substrate 110.

Referring to FIG. 1B, lower and upper tunnel insulating layers 131 and 135 may be formed between the device isolation regions 120. An end of the floating gate 140, an end of the inter-gate insulating layer 150, and a portion of the control gate 160 may contact the upper surface 120a and / or the side surface 120b of the device isolation regions 120. have. In the present embodiment, the device isolation regions 120 may be shallow trench isolation (STI) having a top surface protruding from the surface of the substrate 110.

The substrate 110 is a well known substrate for manufacturing a semiconductor device, and in this embodiment is a silicon substrate. In particular, the substrate 110 may be a substrate in which the surface or the entirety of the substrate 110 is single crystalline silicon.

The lower tunnel insulating layer 131 may be a crystalline silicon oxide layer in this embodiment. In the present exemplary embodiment, the lower tunnel insulating layer 131 may be formed by thermally oxidizing the surface of the substrate 110. For example, since the surface of the substrate 110 is crystalline silicon, it may be a silicon oxide film formed by oxidizing crystalline silicon. The lower tunnel insulating layer 131 may be in contact with the inter-gate insulating layer 150 in the X direction and may be in contact with the device isolation region 120 in the Y direction. A method of forming the lower tunnel insulating film 131 will be described later.

The upper tunnel insulating layer 135 may be a silicon oxide film formed by oxidizing amorphous silicon in this embodiment, and in particular, may be an amorphous oxide film. The upper tunnel insulating layer 135 may be in contact with the inter-gate insulating layer 150 in the X direction and may be in contact with the device isolation region 120 in the Y direction. A method of forming the upper tunnel insulating film 135 will be described later.

In the present exemplary embodiment, since the upper tunnel insulating layer 135 is a silicon oxide film in which amorphous silicon is oxidized, an energy band gap is larger than that of the silicon oxide film formed by oxidizing crystalline silicon such as the lower tunnel insulating film 131. In the present exemplary embodiment, since the upper tunnel insulating layer 135 is an amorphous silicon oxide film, and the lower tunnel insulating layer 131 is a silicon oxide layer formed by oxidizing the silicon, the upper tunnel insulating layer 135 is lower than the lower tunnel insulating layer 131. The energy band gap is large. Specifically, the upper tunnel insulating layer 135 has a larger energy band gap of about 0.15 eV than the silicon oxide film formed by oxidizing single crystal or polycrystalline silicon.

In the present embodiment, since the upper tunnel insulating layer 135 has a larger energy band gap than the silicon oxide film formed by oxidizing crystalline silicon, the information retention characteristic of the stored information may be improved in the EEPROM or the flash memory. In addition, the tunneling characteristics of the electrons may be excellent.

In addition, in FIG. 1B of the present embodiment, the total thickness of the lower and upper tunnel insulating layers 131 and 135 in the Z direction is the height of the portion where the device isolation regions 120 protrude above the surface 110a of the substrate 110. Although lower, the tunnel insulating layer 130 including the lower and upper tunnel insulating layers 131 and 135 may be the same height or higher than the upper surface 120a of the device isolation region 120.

Floating gate 140 may be a conductor for storing information. For example, it may be formed of conductive polycrystalline silicon. The floating gate 140 may overlap or contact a portion of the device isolation regions 120. Specifically, as shown in FIG. 1B, one end of the floating gate 140 may be in contact with a portion of the upper surface 120a and / or the side surface 120b of the device isolation region 120. In other words, the upper surface 140a of the floating gate 140 may be wider than the lower surface 140b. Alternatively, a portion of the lower surface 140b may overlap and / or contact the device isolation regions 120 to be narrower than the upper surface 140a.

In addition, the floating gate 140 is typically formed as an N-type gate, but may be formed as a P-type gate in a special case. Since the P-type gate has a larger work function (Φ) than the N-type gate, the information retention characteristic of the flash memory device may be established. This is because the Fermi level is lower than that of the N-type gate, and thus higher energy is required to pass electrons through the energy barrier of the tunnel insulating layer 130.

However, the P-type gate is known to have an erasing voltage of about 1 to 2 volts higher than that of the N-type gate. Therefore, the P-type gate is difficult to be used in a general flash memory device using a single-layer tunnel insulating film. This is because an increase in the erasing voltage adversely affects the durability of the tunnel insulating film and increases the time required for the erasing operation.

However, the multi-layer tunnel insulating film according to the embodiment of the present invention has better tunneling characteristics than the single-layer tunnel insulating film, so that the tunnel insulating film has excellent durability, and the time required for the erasing operation is reduced. In other words, a P-type gate that has not been applicable in the past when a single-layer tunnel insulating film is used can be applied.

Therefore, when the multilayer tunnel insulating film and the P-type gate according to the present invention are applied, the information retention characteristic of the flash memory device can be further improved without raising the erasing voltage.

The inter-gate insulating layer 150 electrically insulates the floating gate 140 from another conductor, for example, the control gate 160. In the present exemplary embodiment, the inter-gate insulating layer 150 may be formed of a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, but may be formed of a single layer structure using one material. In addition, the inter-gate insulating layer 150 may be formed on the side surface 140c as well as the top surface 140a of the floating gate 140. That is, the inter-gate insulating layer 150, the substrate 110, and the device isolation region 120 may be formed to surround the floating gate 140. In addition, the inter-gate insulating layer 150 may extend to the side surfaces 131a and 135a of the lower tunnel insulating layer 131 and the upper tunnel insulating layer 135. In addition, the top surface 120a of the device isolation regions 120 may extend. In addition, one end or both ends may be formed in contact with the surface 110a of the substrate 110. In addition, although illustrated as extending in the direction (X direction) of the surface 110a of the substrate 110, the substrate 110 may be formed so as not to extend in the surface direction (X direction) of the substrate 110. In other words, an end portion contacting the substrate 120 may be the same thickness as that formed on the side surfaces of the floating gate 140 or the tunnel insulating layers 131 and 135.

The control gate 160 is a conductor and may be formed of conductive polycrystalline silicon in this embodiment. The control gate 160 is formed on the inter-gate insulating layer 150, and the upper surface 140a and the side surface 140c of the floating gate 140 and / or the side surfaces of the lower and upper tunnel insulating layers 131 and 135 ( It may also be formed on the side of the inter-gate insulating film 150 formed on the 131a, 135a. In addition, it may be formed on the upper surface of the inter-gate insulating film 150 in contact with the substrate 110. In addition, the sidewalls of the inter-gate insulating layer 150 in contact with the substrate 110 may not be formed. In other words, the control gate 160 may not be in direct contact with the surface 110a of the substrate 110.

The capping film 170 may be formed of silicon oxide in the present embodiment. The capping layer 170 may be formed to surround the top surface 160a and the side surface 160b of the control gate 160. In addition, the X-direction may be formed to expose the inter-gate insulating film 150 and to contact the substrate 110 and a portion spaced apart from the tunnel insulating film 130. The capping film 170 may be formed to have a uniform thickness as a whole.

In this embodiment, the tunnel insulating layer 130 may be formed in one or more various shapes. For example, the unit cell 100 of FIG. 1A may be a charge trap flash (CTF) memory device. In the case of the charge trapping flash memory device, the lower insulating film 131 in the present embodiment may be applied as the tunnel insulating film. The charge trapping flash memory is generally formed in the structure of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon). In this case, the tunnel insulating layer 130 according to the present embodiment may be applied to the oxide layer below. In addition, TANOS (Tantalum-Aluminum oxide-Nitride-Oxide-Silicon) structure can also be applied to the lower oxide film. Tantalum (T) may be formed in an oxidized or nitrided form (TaO or TaN). N means a silicon nitride film, O means a silicon oxide film, and S can be understood to mean a silicon substrate. SONOS and TANOS are known and will not be described in further detail.

Examples of factors for determining the characteristics of the tunnel insulating layer 130 include thickness and band gap. Operations for storing information in the floating gate 140, that is, programming and erasing operations, operate at a level with a large potential difference compared to an operation for reading information. In detail, the erasing operation operates at a potential difference slightly larger than the programming operation. For example, operations for reading information operate at several volts voltage levels of 2 to 5 volts, and programming and erasing operations operate at tens of volts voltage levels of 12 to 18 volts. One of the programming and erasing operating voltages may be a negative voltage. The voltage level at which information should be maintained is below the operating voltage level for reading the information. Accordingly, the tunnel insulating layer 130 should be easy to tunnel at a relatively high voltage level, and have excellent information retention characteristics at a low voltage level.

The tunnel insulating layer 130 of the flash memory device according to the present exemplary embodiment has a higher band gap than the conventional single layer tunnel insulating layer, and may be formed to have a thin thickness. Therefore, the information retention characteristic is improved at the low voltage level.

2A and 2B are longitudinal cross-sectional views of a unit cell 200 of a flash memory device according to another embodiment of the present invention.

2A and 2B, a flash memory device according to another embodiment of the present invention is compared with a flash memory device according to an embodiment of the present invention shown and described with reference to FIGS. 1A and 1B. It is formed with three or more layers. In detail, an intermediate tunnel insulating layer 233 is formed between the lower tunnel insulating layer 231 and the upper tunnel insulating layer 235.

The intermediate tunnel insulating film 233 may be formed of amorphous silicon or a silicon-rich-oxide in which silicon is not completely oxidized in this embodiment. Impurities may not be injected into the intermediate tunnel insulating layer 233.

3A to 3C are energy band diagrams for explaining theoretically embodiments of the present invention. 3A and 3B, Egs1> Egr1> Egp1 and Egs2> Egr2> Egp2.

Referring to FIG. 3A, the energy band of the flash memory device 100 according to an embodiment of the present invention is a substrate 110, a lower tunnel insulating layer 131, and an upper tunnel in an equilibrium state where no voltage is applied. The energy bands of the insulating layer 135 and the floating gate 140 are in a thermal equilibrium state. Referring to FIG. 3A (a), it is assumed that the substrate 110 and the floating gate 140 have similar energy band gaps, and the band gap of the lower tunnel insulating layer 131 is larger than the two, and the upper tunnel insulating layer The band gap of 135 is described as being slightly larger than the lower tunnel insulating film 131. The energy barrier through which charges or electrons should tunnel may be described as the sum of the thicknesses of the tunnel insulating layers 131 and 135 in the horizontal direction.

The multilayer tunnel insulating layer 130 according to the embodiment of the present invention includes two or more tunnel insulating layers 131 and 135 having different energy band gaps. It may be formed to be larger than 131.

FIG. 3A (b) illustrates the shape of the energy band during the operation of the flash memory device 100 according to an embodiment of the present invention, that is, a read operation. During the read operation, a voltage that is not too high is applied, so that the energy band is slightly bent, so that the energy barrier required for tunneling can be kept to a sufficient thickness. Therefore, the information retention characteristic is improved.

3C illustrates a shape of an energy band in a flash memory device 100 according to an embodiment of the present invention in a programming and erasing operation region. In programming and erasing operation, a much higher voltage is applied than in read operation, so the energy band is bent relatively much, so that tunneling may occur sufficiently.

In other words, a relatively high energy barrier is maintained in a normal state in which a read operation is performed, and a relatively low energy barrier is maintained in a programming and erasing state.

Referring to (a) of FIG. 3B, the energy band of the flash memory device 200 according to another embodiment of the present invention is a substrate 210, a lower tunnel insulating layer 231, and an intermediate tunnel in an equilibrium state where no voltage is applied. The energy bands of the insulating layer 233, the upper tunnel insulating layer 235, and the floating gate 140 are in a thermal equilibrium state. Referring further to (a) of FIG. 3B, it is assumed that the substrate 210 and the floating gate 240 have similar energy band gaps, and the energy band gap of the lower tunnel insulating layer 231 is larger than the two, and the upper tunnel The energy band gap of the insulating film 235 is slightly larger than the lower tunnel insulating film 231, and the middle tunnel insulating film 233 has a lower energy band gap than the lower tunnel insulating film 231 and the upper tunnel insulating film 235. Can be. The energy barrier through which charge or electrons should tunnel can be described as the sum of the thicknesses of the tunnel insulating films 231, 233, and 235 in the horizontal direction.

The multilayer tunnel insulating layer 230 according to an exemplary embodiment of the present invention includes three or more tunnel insulating layers 231, 233, and 235 having different energy band gaps. In particular, the energy band gap of the lower tunnel insulating layer 231 may be formed to be smaller than the energy band gap of the upper tunnel insulating layer 235. The energy band gap of the intermediate tunnel insulating film 233 may be formed to be smaller than the energy band gap of the lower tunnel insulating film 231.

FIG. 3B (b) illustrates the shape of the energy band during the operation of the flash memory device 200 according to another embodiment of the present invention, that is, a read operation. In the read operation, a voltage that is not too high is applied, so the energy band is slightly warped, so that the energy barrier required for tunneling can be kept to a sufficient thickness. Therefore, the information retention characteristic is improved.

3B (c) illustrates a flash memory device 200 according to another embodiment of the present invention modeling the shape of an energy band in a programming and erasing operation region. In programming and erasing operation, a much higher voltage is applied than in read operation, so the energy band is bent relatively much, so that tunneling may occur sufficiently.

That is, the characteristics of maintaining a relatively high energy barrier in the normal state of the read operation, and a relatively low energy barrier in the programming and erasing operation state are further improved.

Therefore, the flash memory devices 100 and 200 according to the embodiments of the present invention have greatly improved information retention characteristics during a read operation.

In addition, when the intermediate tunnel insulating film 233 is silicon, particularly amorphous silicon, this operation may be smoother.

In conclusion, the flash memory devices 100 and 200 according to the embodiments of the present invention have better tunneling characteristics than the tunnel insulating film formed of the conventional single layer insulating film at the voltage level for programming and erasing operation, in particular, the erasing operation. .

When the intermediate tunnel insulating film 233 is a silicon-rich-oxide film, the energy band gap is larger than that of the silicon film, but the energy band gap is smaller than that of the complete insulating film. Therefore, the thin film may be electrically thinner and physically thicker than the tunnel insulating film is formed of a single insulating film. This means that the tunneling characteristics or information retention characteristics of the flash memory device can be selectively or both improved.

The silicon-rich-oxide film may be formed in the process of forming the upper tunnel insulating film 235 during the manufacturing process. Specifically, a process of forming a silicon film and oxidizing it from the upper surface, but not oxidizing all of the silicon film but proceeding to stop the oxidation reaction at an appropriate place, the closer to the upper surface, the more fully oxidized silicon oxide film, and closer to the lower surface. The more it is intact silicon, not oxidized. Therefore, the silicon film at this time is an incompletely oxidized silicon oxide film, and this film quality is a silicon-rich-oxide film.

On the other hand, since it can be physically formed to a thicker thickness, the process of forming the tunnel insulating film 230 is easier in the manufacturing process. Since the tunnel insulating film 230 may be formed to have a physical thickness thicker than the conventional single layer insulating film, and the upper tunnel insulating film 235 having a large band gap is formed at the voltage level at which the information is to be maintained electrically. The flash memory device according to the present embodiment has improved information retention characteristics.

3C is an energy band diagram for explaining that information retention characteristics can be improved for N-type gates and P-type gates according to embodiments of the present invention.

Referring to (a) and (b) of FIG. 3C, when the floating gate is N-type and P-type, Fermi levels En and Ep are respectively located at different locations. In detail, the Fermi level (En) of the N-type gate is located between the Fermi level (Ef) of the intrinsic semiconductor and the conduction band (Ec), and the Fermi level (Ep) of the P-type gate is the Fermi level ( Ef) is located between the valance band (Ev). Therefore, P-type gates require more energy for electrons (eg, arrow direction) to cross an energy barrier than N-type gates. Therefore, the P-type gate has better information retention characteristics than the N-type gate.

4A and 4B are cross-sectional views in the XZ direction showing an embodiment in which the technical idea of the present invention is applied to a charge trap flash such as SONOS or TANOS.

Referring to FIG. 4A, the charge trap flash memory device 300a according to an exemplary embodiment may include a multilayer tunnel insulating film 330a, a charge trap film 337, a blocking film 339, a gate electrode 360, and An insulating capping film 370 is included.

The multilayer tunnel insulating film 330a may be formed on the substrate 310, the charge trap film 337 may be formed on the multilayer tunnel insulating film 330a, and the blocking film 339 may be formed on the charge trap film 337. The gate electrode 360 may be formed on the blocking layer 339, and the insulating capping layer 370 may be formed on the gate electrode 360. In addition, the multilayer tunnel insulating layer 330a includes a lower tunnel insulating layer 331 and an upper tunnel insulating layer 335. The upper tunnel insulating layer 335 may be formed on the lower tunnel insulating layer 331.

The charge trap layer 337 may be formed of a silicon nitride layer and the blocking layer 339 may be formed of a silicon oxide layer. Descriptions of the charge trap film 337 and the blocking film 339 are well known, and thus detailed descriptions thereof will be omitted.

For a detailed description of the tunnel insulating film 330a, the tunnel insulating film 130 of FIGS. 1A and 1B may be referred to.

Referring to FIG. 4B, the charge trap flash memory device 300b according to another embodiment of the present invention may include a multilayer tunnel insulating film 330b, a charge trap film 337, a blocking film 330, a gate electrode 360, and an insulating property. Capping layer 370 is included.

The multilayer tunnel insulating film 330b may be formed on the substrate 310, the charge trap film 337 may be formed on the multilayer tunnel insulating film 330b, and the blocking film 339 may be formed on the charge trap film 337. The gate electrode 360 may be formed on the blocking layer 339, and the insulating capping layer 370 may be formed on the gate electrode 360. In addition, the multilayer tunnel insulating film 330b may include a lower tunnel insulating film 331, an intermediate tunnel insulating film 333 formed on the lower tunnel insulating film 331, and an upper tunnel insulating film 335 formed on the intermediate tunnel insulating film 333. Can be.

For a detailed description of the tunnel insulating film 330b, the tunnel insulating film 230 and its description of FIGS. 2A and 2B may be referred to.

In the charge trap flash memory devices 300a and 300b, an information retention characteristic may be improved by applying a P-type gate to the gate electrode 360. Since the description has already been mentioned, the description is omitted to avoid duplication.

In addition, in the charge trap flash memory devices 300a and 300b, when the entire gate electrode 360 is P-type, there is a concern that the conductivity and the like become low. In this case, the P-type gate layer can be solved by thinning it. For example, the thin filmed P-type conductive layer may be formed adjacent to the charge trap layer 337, the gate electrode 360 may be formed of the metal silicide layer, or the N-type gate may be formed after the metal silicide layer is interposed. have. A brief description of this is shown in FIGS. 5A and 5B.

5A and 5B are cross-sectional views illustrating a case where the gate electrode of the charge trap flash memory devices includes a P-type gate layer.

Referring to FIG. 5A, in the charge trap flash device 300c according to the present invention, the gate electrode 360 includes a P-type gate electrode 360p and a metal silicide layer 360m.

In this embodiment, since the P-type gate 360p is formed at a position adjacent to the charge trap film 337, the information retention characteristic is improved, and the metal silicide layer 360m is formed, so that the gate resistance is further lowered.

Referring to FIG. 5B, in the charge trap memory device 300d according to the present invention, the gate electrode 360 includes a P-type gate 360p, a metal silicide layer 360m, and an N-type gate 360n.

In this embodiment, since the P-type gate 360p is formed at a position adjacent to the charge trap film 337, the information retention characteristic is improved, and the metal silicide layer 360m and the N-type gate 360n are stacked so that the gate is low in resistance. An electrode 360 is formed.

The thicknesses of the tunnel insulation layers 130, 230, 330a, and 330b according to the present embodiments may be formed to have a physically thicker thickness compared to the thickness of the conventional single layer tunnel insulation layer. Electrically, however, they exhibit thinner thicknesses. Since the tunnel insulation layers 130, 230, 330a, and 330b according to the present embodiments have a low electrical thickness, they have good tunneling characteristics, are physically thicker, and have a higher energy barrier when considered as an energy band. Excellent information retention characteristics.

Next, a method of manufacturing a flash memory device according to embodiments of the present invention will be described.

6 to 10B are manufacturing process diagrams for describing a method of forming a cell of a flash memory device according to an embodiment of the present invention shown in FIGS. 1A and 1B. In detail, FIGS. 7A, 8A, 9A and 10A are sectional views along the XZ plane, and FIGS. 7B, 8B, 9B and 10B are sectional views along the YZ plane.

6, a first insulating film 131 ′ for forming the lower tunnel insulating film 131, a second insulating film 135 ′ for forming the upper tunnel insulating film 135, and a mask on the substrate 110. Form layer (M). The first insulating film 131 ′ and the second insulating film 135 ′ are insulating films 130 ′ for forming the tunnel insulating film 130.

First, a first insulating layer 131 ′ for forming the lower tunnel insulating layer 131 is formed on the substrate 110. Since the surface of the substrate 110 is single crystal silicon, the first insulating layer 131 ′ may be a silicon oxide film to which single crystal silicon is oxidized. The first insulating layer 131 ′ may be formed to be wide on the entire surface of the substrate 110. In the present embodiment, the first insulating film 131 ′ is formed by injecting H ₂ O or O ₂ gas and heating to a temperature of about 900 ° C. to generate H + radicals or O− radicals, for example, and thus the surface of the substrate 110. It can be formed by oxidizing. In this case, the first insulating layer 131 ′ may be formed to a thickness of about 30 μs to about 50 μs, but is not limited thereto. In this embodiment, the thermal oxidation method may be an example of a radical oxidation method. That is, other oxidation methods can also be used.

In addition, the surface of the first insulating film 131 ′ may be treated with ozone water (O ₃ water). When the surface of the first insulating film 131 ′ is treated with ozone water, the effect can be increased while reducing the incubation time for forming the second insulating film 135 ′. In this case, a high quality second insulating film 135 ′ may be formed thicker at the same time than when the surface of the first insulating film 131 ′ is not treated with ozone water. Therefore, since the second insulating film 135 'can be formed thicker, the surface roughness of the second insulating film 135' is improved.

In the method of treating the surface of the first insulating film 131` with ozone water, the wafer was immersed in ozone water (O ₃ water) having a concentration of about 50 ppm at room temperature (clean room temperature) for about 300 seconds. It is an example carried out to implement the technical idea of. The wafer can be processed at various times in various concentrations of ozone water.

In the present exemplary embodiment, the second insulating layer 135 ′ may be a silicon oxide layer in which amorphous silicon is oxidized. In detail, an amorphous silicon film may be formed on the first insulating film 131 ′ and oxidized to form a second insulating film 135 ′. Or an incompletely oxidized silicon-rich-oxide film. The silicon-rich-oxide film can be formed by forming a silicon film on the first insulating film 131 'and oxidizing it properly without oxidizing completely.

In order to form the second insulating film 135 ′, a step of forming an amorphous silicon film on the first insulating film 131 ′ includes SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , SiH ₂ Cl ₂ , SiCl ₄ , Si ₂ Cl ₆ or a combination of two or more gases as the source gas may be performed similar to the atomic layer deposition method (ALD-like). The similarity to the atomic layer deposition method is not an atomic layer deposition method, but it means that the step of forming a material film is formed by a method of depositing little by little in several steps. In the present exemplary embodiment, an amorphous silicon film may be formed by a low pressure chemical vapor deposition (LP-CVD) method. In this case, the amorphous silicon film may be formed thicker than the thickness shown.

However, other deposition methods are not excluded. An atomic layer deposition method may be used, and a physical deposition method (PVD) may be used. In addition, there is no need to proceed similarly to the ALD method. That is, the amorphous silicon film can also be formed by a general CVD method.

Next, as a method of oxidizing the amorphous silicon film, the amorphous silicon film may be thermally oxidized or radically oxidized, such as to form the first insulating film 131 ′. The description of this method may refer to the method of forming the first insulating film 131 ′.

Although the first insulating film 131 ′ and the second insulating film 135 ′ may be formed to a desired thickness in one process, a method of forming the second insulating film 135 ′ or the amorphous silicon film thicker than the desired thickness and removing the surface thereof. By lowering the thickness, the first insulating film 131 ′ and the second insulating film 135 ′ having a desired thickness can be finally formed. For example, the surface of the second insulating film 135 ′ may be formed thicker than a desired thickness, and then the surface may be partially removed by a hydrofluoric acid solution to form a desired thickness. In this case, the hydrofluoric acid solution used is a diluted hydrofluoric acid solution typically used in a semiconductor production line, and may be a hydrofluoric acid solution diluted and mixed with water at a volume ratio of 0.1% to 10%. In this case, the second insulating layer 135 ′ may be removed at about 0.3 μs / sec.

In an application embodiment of the present invention, the surface of the second insulating film 135 ′ may be partially removed using SC-1 rather than a diluted hydrofluoric acid solution. SC-1 contains liquid hydrogen peroxide, ammonia and water and is well known as a cleaning solution in semiconductor processes. The mixing ratio of SC-1 can be applied in a wide variety of applications and the mixing ratio is well known according to the use and purpose, and thus there is no need to disclose specific values.

In the present embodiment, when the second insulating film 135 ′ is formed sufficiently thick, it was found that the characteristics of the upper tunnel insulating film 135 tend to be improved. Therefore, the second insulating film 135 ′ may be formed thicker than the desired thickness to maximize the characteristics of the upper tunnel insulating film 135.

Finally, a mask layer M for patterning the first insulating layer 131 ′ and the second insulating layer 135 ′ into the lower tunnel insulating layer 131 and the upper tunnel insulating layer 135 is formed. In the present embodiment, the mask layer M may be a photoresist or a hard mask layer. In the case of a hard mask layer, it may be an inorganic material such as a silicon nitride film or a silicon oxynitride film.

Referring to FIG. 7A, the lower tunnel insulating layer 131, the upper tunnel insulating layer 135, and the floating gate 140 are formed by performing a photolithography process, and then the mask layer M is removed. The photolithography process is well known and detailed description thereof is omitted.

Referring to FIG. 7B, device isolation regions 120 are formed.

For example, a silicon nitride film (not shown) is formed on the tunnel insulating film 130, and a photolithography process is performed to form trenches for forming the device isolation regions 120, and to fill the insulator, followed by a CMP process. The device isolation regions 120 may be formed to separate the tunnel insulating layer 130. In this case, since the CMP process is performed, the tunnel insulating layer 130 is formed at a lower height than the device isolation regions 120 in the Z direction, but may be formed at the same height. If a buffer film (not shown) such as a silicon film is formed on the tunnel insulating film 130 and then a silicon nitride film is formed and the device isolation regions 120 are formed, the tunnel insulation layer 130 and the device isolation regions are formed. 120 may be formed at the same height. All such cases fall within the scope of the technical idea of the present invention.

In the previous step, when a hard mask is used as the mask layer M, a process of removing the mask layer M may not be introduced. That is, the process of forming the tunnel insulating film 130 by forming the mask layer M once and the process of forming the trench may be continued or simultaneously.

Thereafter, a conductive layer for forming the floating gate 140 is formed and a photolithography process is performed to form the floating gate 140 separated for each cell. Floating gate 140 may be conductive polycrystalline silicon. When conductivity is provided to the floating gate 140, a polycrystalline silicon film for forming the floating gate 140 is formed, a buffer layer (for example, a silicon oxide film, not shown) is formed, and B, P, or As ions are implanted. Can be. In the case of forming the N-type gate, ions containing P, As or ions thereof may be implanted, and in the case of forming a P-type gate, ions containing B ions may be implanted. As the ion implantation method, both an ion beam implantation method and a plasma ion implantation method may be used, and various gas combinations that may be used therein are well known.

The buffer layer may be removed before or after forming the floating gate 140. For example, the conductive layer for forming the floating gate 140 may be changed to polycrystalline silicon by first forming a single crystal silicon film and then annealing at about 800 ° C.

Referring to FIGS. 8A and 8B, an insulating layer 150 ′ for forming the inter-gate insulating film 150 is formed on the entire surface, and a conductive layer for forming the control gate 160 on the insulating layer 150 ′ ( 160 ').

In this embodiment, the insulating layer 150 ′ for forming the inter-gate insulating film 150 may have a triple layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film. In the case of forming a triple layer, an insulating layer 150 'for forming a silicon oxide film on the entire surface, a silicon nitride film on the silicon oxide film, and a silicon oxide film on the silicon nitride film to form the inter-gate insulating film 150. ). The inter-gate insulating film 150 having the triple layer structure may trap charges and thus may be applied as a flash trap device of a charge trapping method. The insulating layer 150a for forming the inter-gate insulating layer 150 may be formed by a deposition method, and in particular, may be formed by a chemical vapor deposition (CVD) method.

In this embodiment, the conductive layer 160a for forming the control gate 160 may be formed of conductive polycrystalline silicon. In addition, the conductive layer 160a for forming the control gate 160 may be formed of a metal silicide or a metal layer.

9A and 9B, an inter-gate insulating layer 150 and a control gate 160 are formed by performing a photolithography process. The inter-gate insulating layer 150 may be formed to be separated for each cell in the X direction. In the Y direction, as shown in the figure may be separated by cells, but may not be separated by cells. The control gate 160 may be formed to be separated for each cell in the X direction, and may be formed to extend for a long time without being separated for each cell in the Y direction. Since a method of forming the inter-gate insulating layer 150 and the control gate 160 by performing the photolithography process is well known, a detailed description thereof will be omitted.

10A and 10B, a capping layer 170 is formed on the control gate 160. In this embodiment, the capping film 170 may be formed of a silicon oxide film. In the drawing, the capping layer 170 may be formed to surround the top surface and both side surfaces of the control gate 160 in the X direction, and may be formed to contact the substrate 110. The Y direction may cover the top surface of the control gate 160. The capping layer 170 may be formed by a deposition method.

Thereafter, a silicon nitride film or the like is formed on the capping film 170, and a contact, a signal line, a via, and the like for signal transmission are formed to complete the flash memory.

A method of manufacturing a flash memory device according to another embodiment of the present invention is described.

11 and 12 are diagrams for describing a method of forming a tunneling insulating layer 230 of a flash memory device according to another embodiment of the present invention.

Referring to FIG. 11, a lower insulating film 231a for forming the lower tunnel insulating film 231 and an amorphous silicon film 233a for forming the intermediate tunnel insulating film 233 are formed on the substrate 210. Also in this embodiment, the intermediate tunnel insulating film 233 may be a silicon-rich-oxide film.

Also in this embodiment, after forming the lower insulating film 231 ′ for forming the lower tunnel insulating film 231, a process of treating the surface of the lower insulating film 231 ′ with ozone water may be performed.

Also, in this embodiment, the amorphous silicon film 233 'may be formed thicker than the lower insulating film 231' for forming the lower tunnel insulating film 231. FIG. The lower insulating layer 231 ′ for forming the lower tunnel insulating layer 230 may be formed by thermally or radically oxidizing the substrate 210. As described above, the amorphous silicon film 233 ′ for forming the intermediate tunnel insulating film 233 may be SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , SiH ₂ Cl ₂ , SiCl ₄ , Si ₂ Cl _6, or a combination of two or more thereof. By using the prepared gas as a source gas, it can be formed similarly to an atomic layer deposition method (ALD-like).

As mentioned above, in addition to the method of slowly performing the CVD method similarly to the atomic layer deposition method, a general CVD method, an ALD method, or a PVD method may be used as a method of forming an amorphous silicon film.

Referring to FIG. 12, an upper silicon insulating film 235 ′ for forming an upper tunnel insulating film 235 is formed by oxidizing the amorphous silicon film 233 ′. In the present exemplary embodiment, the upper insulating layer 235 ′ for forming the upper tunnel insulating layer 235 may be formed by oxidizing the surface of the amorphous silicon layer 233 ′ by a thermal oxidation method. When the amorphous silicon film 233 'is thermally oxidized for an appropriate time, the triple layer tunnel insulating film 230 according to the present embodiment can be formed. A method of thermally oxidizing the amorphous silicon film 233` is well known, and detailed description thereof will be omitted because process conditions such as temperature are very diverse.

Also in this embodiment, the entire thickness of the tunnel insulating film 230 is formed by forming an upper insulating film 235 'for forming the upper tunnel insulating film 235, and then partially removing the surface using a hydrofluoric acid solution or SC-1. The process of adjusting can be performed.

Next, effects according to various embodiments of the present invention will be described with reference to graphs.

FIG. 13 is a graph for explaining a trend of deposition thickness of an amorphous silicon film according to an embodiment of the present invention when the surface of the lower tunnel oxide film is not treated with ozone water and when the surface is treated. X axis is deposition time and Y axis is deposition thickness.

Referring to FIG. 13, it can be seen that when the surface of the lower tunnel oxide film is treated with ozone water, the deposition rate of amorphous silicon is faster than when the surface of the lower tunnel oxide film is not treated. That is, at the same time it can form thicker amorphous silicon. Referring back to FIG. 13, it can be seen that when the surface of the lower tunnel insulating film is treated with ozone water, a thickness difference of about 3.2 kW to 8.3 kW is maintained. Although a small difference over time, this deposition process results in a very large process capability difference when batched with tens or hundreds of wafers simultaneously processed.

14 is a graph measuring the erasing tunneling effect according to embodiments of the present invention. The X axis is the tunneling voltage V _E and the Y axis is the tunneling current I _E.

It is a graph in which the characteristics of various thicknesses are measured with A, B, C, and D, respectively, with the structure of the tunnel insulation layer having a lower, middle, and upper three-layer structure. Specifically, A has a total thickness of the tunnel insulating film is 72Å, the thickness of the lower, middle and upper tunnel insulating film is 32Å, 10Å, and 30Å, respectively, B is a total thickness of the tunnel insulating film is 90Å and the lower, middle and upper tunnel insulating film Are 40, 10Å, 40Å, C is the total thickness of the tunnel insulation film 100Å, the thickness of the lower, middle and upper tunnel insulation films is 45Å, 10Å, and 45Å respectively, and D is the total thickness of the tunnel insulation film. 110 kPa, and the thicknesses of the lower, middle, and upper tunnel insulating films are 40 kPa, 10 kPa, and 60 kPa. The conventional single-layer tunnel insulating film was set to a thickness of about 83 kPa in this experiment.

Referring to FIG. 14, it can be seen that the tunneling currents of the multi-layer tunnel insulating films according to the embodiments of the present invention are higher than the conventional single-layer tunnel insulating film at the same tunneling voltage. That is, it shows better characteristics even with a thicker thickness than the conventional single-layer tunnel insulating film. In other words, it is possible to operate at a lower voltage to obtain the same tunneling current, thereby achieving lower power.

FIG. 15 is a graph illustrating results converted into thicknesses according to electrical characteristics when the multilayer tunnel insulation layers and the conventional single layer tunnel insulation layer have the same or similar characteristics according to embodiments of the present disclosure. The X axis is various combinations of the multilayer tunnel insulating films A, B, C, and D, and the Y axis is the converted electrical thickness (T _OX (thickness of oxide)).

Referring to FIG. 15, the multilayer tunnel insulating layers according to various embodiments of the present disclosure may have thick physical thicknesses. Specifically, when the capacitance of the tunnel insulating film is measured and converted, it can be seen that the physical thickness is thick. If the capacitance value is low, the thickness is thick, and if the capacitance value is high, the thickness is thin. In this graph, the physical thickness of the converted tunnel insulation film means that the information retention characteristic is excellent.

16 is a graph measuring the erasing voltage characteristics of a multilayer tunnel insulating layer according to embodiments of the present invention. The X axis is the tunnel insulating film, and the Y axis is a graph measuring the voltage (V _E ), that is, the erasing voltage when tunneling occurs.

Referring to FIG. 16, the three points on the left side are the erasing voltage characteristics of the conventional single-layer tunnel insulating layer, and the points on the right side represent the erasing voltage characteristics of the multilayer tunnel insulating layer according to the embodiments of the present invention. That is, it can be seen that the erasing voltages of the multilayer tunnel insulating layers according to embodiments of the present invention are about 2V lower than the conventional erasing voltage. This means that the device can operate in a lower erasing voltage range than in the prior art. Operating the device in the lower erasing voltage range means that it consumes less power, and that coupling and device reliability and durability can be further enhanced.

In addition, as a result of measuring the endurance of the multilayer tunnel insulating layers according to various embodiments of the present invention, it can be seen that it has superior durability than the prior art. The reason for this is presumably because the tunnel insulating film is less physically stressed because the programming and erasing operations are performed at a lower voltage than the prior art. In addition, better properties were measured for longer periods of time, even under extreme conditions, and information retention was also measured.

FIG. 17 is a view illustrating tunneling current-voltage characteristics according to ozone water treatment of a multilayer tunnel insulating layer according to embodiments of the present invention. The X axis is the applied voltage and the Y axis is the current according to the voltage.

Referring to FIG. 17, multilayer tunnel insulating films according to embodiments of the present invention exhibit better characteristics than those of the conventional single layer tunnel insulating film. Specifically, it shows that the information retention characteristic is improved by showing a relatively lower current at the same voltage before tunneling occurs. In addition, when tunneling occurs, relatively more current flows at the same voltage. At this time, more important is the slope of the graph. At lower tunneling voltages, more current must flow, so the earlier the tunneling, the steeper the slope, the better the characteristics. In conclusion, the characteristics of the multilayer tunneling insulating films according to the embodiments of the present invention show better characteristics in all aspects than the single-layer tunnel insulating film according to the prior art. For reference, the single-layer tunnel insulating film according to the prior art was about 82 kW, the multilayer tunnel insulating film according to the embodiments of the present invention was 102 kPa when the ozone water treatment was not performed, and 112 kPa when the ozone water treatment was used.

FIG. 18 illustrates tunneling current-voltage characteristics when a surface of an upper tunnel insulating layer is partially removed with a hydrofluoric acid solution according to example embodiments. The X axis is the applied voltage and the Y axis is the current according to the voltage.

Referring to FIG. 18, when the surface of the upper tunnel insulating film is not partially removed with a hydrofluoric acid solution (D), about 15 ms is removed (F), rather than the characteristic (H) of the single-layer tunnel insulating film according to the prior art, and In the case of removing about 30Å (G) and all show excellent properties. It can also be seen that the characteristics shown in FIG. 17 are maintained as they are. Therefore, it can be seen that the thickness of the final multilayer tunnel insulating film can be adjusted to any extent.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1A and 1B are longitudinal cross-sectional views of a unit cell of a flash memory device according to an embodiment of the present invention.

2A and 2B are longitudinal cross-sectional views of a unit cell of a flash memory device according to another embodiment of the present invention.

3A to 3C are energy band diagrams for explaining theoretically embodiments of the present invention.

4A and 4B are cross-sectional views in the XZ direction showing an embodiment in which the technical idea of the present invention is applied to a charge trap flash such as SONOS or TANOS.

5A and 5B are cross-sectional views illustrating a case where the gate electrode of the charge trap flash memory devices includes a P-type gate layer.

6 to 10B are manufacturing process diagrams for describing a method of forming a cell of a flash memory device according to an embodiment of the present invention shown in FIGS. 1A and 1B.

11 and 12 are diagrams for describing a method of forming a flash memory device according to another exemplary embodiment of the present invention.

FIG. 13 is a graph for explaining a trend of deposition thickness of an amorphous silicon film according to an embodiment of the present invention when the surface of the lower tunnel oxide film is not treated with ozone water and when the surface is treated.

14 is a graph measuring the erasing tunneling effect according to embodiments of the present invention.

FIG. 15 is a graph illustrating results converted into thicknesses according to electrical characteristics when the multilayer tunnel insulation layers and the conventional single layer tunnel insulation layer have the same or similar characteristics according to embodiments of the present disclosure.

16 is a graph measuring the erasing voltage characteristics of a multilayer tunnel insulating layer according to embodiments of the present invention.

FIG. 17 is a view illustrating tunneling current-voltage characteristics according to ozone water treatment of a multilayer tunnel insulating layer according to embodiments of the present invention.

FIG. 18 illustrates tunneling current-voltage characteristics when a surface of an upper tunnel insulating layer is partially removed with a hydrofluoric acid solution according to example embodiments.

 DESCRIPTION OF THE REFERENCE NUMERALS (S)

100, 200, 300: flash memory device

110, 210, 310: substrate

120, 220: device isolation region

130, 230, 330: tunnel insulation film

131, 231, and 331: lower tunnel insulating film

233, 333: intermediate tunnel insulating film

135, 235, 335: upper tunnel insulating film

140, 240: floating gate

150, 250: inter-gate insulating film

160, 260: control gate

170, 270, 370: capping film

337: charge trapping film

339: blocking film

360: gate electrode

Claims (20)

A lower tunnel insulating film formed on the substrate, An upper tunnel insulating film formed on the lower tunnel insulating film, An amorphous silicon film formed between the lower tunnel insulating film and the upper tunnel insulating film, A P-type floating gate formed on the upper tunnel insulating film, An inter-gate insulating film formed on the P-type floating gate, and A control gate formed on the inter-gate insulating film, And the upper tunnel insulating layer is an amorphous oxide layer. delete delete The method of claim 1, And the upper tunnel insulating layer is a silicon-rich-oxide film. A lower tunnel insulating film formed on the substrate, An upper tunnel insulating film formed on the lower tunnel insulating film, A charge trap insulating film formed on the upper tunnel insulating film, A blocking film formed on the charge trap insulating film, A P-type gate electrode formed on the blocking film, and An insulating capping film formed on the P-type gate electrode, And the upper tunnel insulating layer is an amorphous oxide layer. 6. The method of claim 5, And an amorphous silicon film formed between the lower tunnel insulating film and the upper tunnel insulating film. 6. The method of claim 5, And a silicon-rich-oxide film formed between the lower tunnel insulating film and the upper tunnel insulating film. 6. The method of claim 5, And the upper tunnel insulating layer is a silicon-rich-oxide film. A multilayer tunnel insulating film formed on a substrate, A P-type floating gate electrode formed on the multilayer tunnel insulating film, An inter-gate insulating film formed on the P-type floating gate electrode, and A control gate electrode formed on the inter-gate insulating film; The multilayer tunnel insulating film, A first tunnel insulating film having a first energy band gap, A second tunnel insulating film having a second energy band gap different from the first energy band gap, and And an amorphous silicon film formed between the first tunnel insulating film and the second tunnel insulating film. A multilayer tunnel insulating film formed on a substrate, A charge trap insulating film formed on the multilayer tunnel insulating film, A blocking film formed on the charge trap insulating film, and P-type gate electrode formed on the blocking film, The multilayer tunnel insulating film, A first tunnel insulating film having a first energy band gap, A second tunnel insulating film having a second energy band gap different from the first energy band gap, and And an amorphous silicon film formed between the first tunnel insulating film and the second tunnel insulating film. delete delete delete delete delete delete delete delete delete delete

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