KR101298179B1 - Digital pulse generator of ultra wideband with gaussian pulse shaping - Google Patents

Abstract

PURPOSE: A digital pulse generator of ultrawide band having a Gaussian pulse shape is provided to generate impulse in all ultrawide frequency bands and change the bandwidth into an arbitrary signal. CONSTITUTION: A digital pulse generator comprises a time delay circuit (10), a latch circuit (20), a pulse sensing circuit (30), and a Gaussian envelope shaper (40). The time delay circuit generates multiple time delay pulses having a constant time delay by receiving a first clock pulse. The latch circuit receives the multiple time delay pulses from the time delay circuit and outputs the multiple time delay pulses by a second clock pulse, and controls each of outputs of the multiple time delay pulses by clear control signal. The pulse sensing circuit receives the multiple time delay pulses from the latch circuit, and outputs a pulse signal corresponding to a difference between signals delayed in the time delay circuit. The Gaussian envelope shaper outputs an impulse signal having a Gaussian shape by synthesizing the pulse signals output from the pulse sensing circuit. [Reference numerals] (AA) Time delay circuit

Description

Digital Pulse Generator of Ultra Wideband with Gaussian Pulse Form

The present invention relates to an ultra wideband (UWB) digital pulse generator having a Gaussian pulse shape used in a semiconductor integrated circuit.

In radar applications, the transmitter generates an impulse signal, which is difficult to implement in the form of a hybrid module due to the very fast signal. Therefore, a method of implementing an existing impulse generator as an integrated circuit has been proposed.

Conventional impulse generators can be broadly divided into structures using a voltage controlled oscillator (VCO) type and digital logic. In the case of the VCO type, an ultra-wideband VCO is required to generate a pulse by limiting an output time on a time axis in a frequency frequency region of the VCO. Therefore, the power consumption of the VCO is inevitably increased, and the magnitude of the output signal is determined according to the rising and falling of the on / off time for generating the pulse signal.

On the contrary, the pulse generator using the digital logic has an advantage of having a very small power consumption and size compared to the VCO type. The ultra-wideband impulse generator using the digital logic can be implemented in various ways. For example, a delay element can be used to generate a pulse train and then output to the output, or a pulse can be generated differentially with each phase difference to generate an impulse.

However, the impulse generator composed of the existing VCO type and digital logic has a disadvantage in that it is vulnerable to the characteristics of the variability of the operating frequency and the variability of the bandwidth (bandwidth). In particular, since the impulse generator of the VCO type has a limitation in bandwidth due to an on / off characteristic, there is a characteristic that the variability is lower than that of the digital type.

In addition, an impulse generator composed of a conventional VCO type and digital logic uses a pulse shaping filter or a bandpass filter to maintain an impulse shape, thereby requiring additional circuits or devices. Done.

Korean Registered Patent No. 0559769 (Registration Date: 2006.03.06)

The technical problem to be solved by the present invention to solve the above-described problems, not only can generate an impulse at all frequencies of the ultra wideband (UWB), but also the bandwidth (bandwidth) is variable through an arbitrary signal To present a possible ultra-wideband (UWB) digital pulse generator.

Another object of the present invention is to provide an ultra wideband (UWB) digital pulse generator capable of operating without an additional circuit such as a filter by generating a Gaussian type impulse.

Another object of the present invention is to provide an ultra wideband (UWB) digital pulse generator capable of implementing an ultrawideband impulse generator using digital logic.

In addition, another technical problem to be achieved by the present invention is to present an ultra-wideband (UWB) digital pulse generator that can freely implement the desired frequency bandwidth by controlling the number of pulses by randomly on / off each pulse There is.

Another object of the present invention is to provide an ultra wideband (UWB) digital pulse generator having a frequency characteristic having a low side lobe through a Gaussian pulse shape.

The solution to the problem of the present invention is not limited to those mentioned above, and other solutions not mentioned can be clearly understood by those skilled in the art from the following description.

As a means for solving the above technical problem, the ultra-wideband (UWB) digital pulse generator of the present invention comprises a time delay circuit for generating a plurality of time delay pulses having a predetermined time delay by inputting the first clock pulse, A latch circuit for receiving a plurality of time delay pulses from the time delay circuit and outputting the plurality of time delay pulses, and controlling the output of the time delay pulses according to a clear control signal; and a plurality of time delay pulses from the latch circuit. A pulse sensing circuit for outputting a pulse signal corresponding to the difference in signal delayed by the time delay circuit and a pulse signal output from the pulse sensing circuit into one, and having a form of a Gaussian shape (Gaussian shape) Including a Gaussian envelope shaper that outputs a signal Can be made. The second clock pulse may be generated by a logical combination of a time delay pulse and the first clock pulse that are output last among a plurality of time delay pulses of the time delay circuit. In this case, the generation circuit of the second clock pulse is an inverter for inputting a time delay pulse that is output last of the plurality of time delay pulses of the time delay circuit and inverted polarity, and outputs the output signal of the inverter and the first It may be configured to include an AND gate for inputting the clock pulse and output by the logical product.

The time delay circuit may include a plurality of inverters that input the first clock pulse and output a plurality of time delay pulses each having a predetermined time delay. Here, the plurality of inverters may be configured in a current mirror (current mirror) structure.

delete

The latch circuit may be composed of a plurality of D-latch.

The pulse sensing circuit may input two time delay pulses output from the latch circuit, respectively, and output pulse signals corresponding to the delayed signal differences. The pulse sensing circuit may be configured with a plurality of exclusive-OR gates.

The Gaussian envelope shaper includes a plurality of first amplifiers each inputting and amplifying a pulse signal output from the pulse sensing circuit, and an impulse signal having a form of a Gaussian shape by combining the signals output from the plurality of first amplifiers into one. It may be configured to include a second amplifier for outputting. Here, the first and second amplifiers may be configured as an inverter.

The first amplifier or the second amplifier is connected in series between the terminal of the power supply voltage and the output terminal, and the first and second pull controlled by the second bias signal bias2 and the pulse signal output from the pulse sensing circuit. A up-up driver and first and second pull-down drivers connected in series between the output terminal and the ground voltage terminal and controlled by a pulse signal and a first bias signal bias1 output from the pulse sensing circuit. Can be configured.

Here, the first and second pull-up drivers are composed of PMOS transistors, and the first and second pull-down drivers are composed of NMOS transistors, or the first and second pull-up drivers are The first and second pull-down drivers may be configured as NMOS transistors, and the inverter may be configured at a gate of the second pull-up driver or the first pull-down driver.

The digital pulse generator may freely implement a desired frequency bandwidth by adjusting the number of pulses generated by randomly turning on / off each pulse by the clear control signal.

According to the present invention, not only generates an impulse at all frequencies of the ultra wide band (UWB), but also the bandwidth can be varied through an arbitrary signal.

In addition, by generating a Gaussian type impulse, an additional circuit such as a filter can be operated without the need.

In addition, an ultra-wideband impulse generator may be implemented using digital logic.

The digital pulse generator may freely implement a desired frequency bandwidth by adjusting the number of pulses generated by randomly turning on / off each pulse by the clear control signal.

In addition, a Gaussian pulse shape may have a frequency characteristic having a low side lobe.

The effects of the present invention are not limited to those mentioned above, and other effects that are not mentioned will be clearly understood by those skilled in the art from the following description.

1 is an overall configuration diagram of an ultra-wideband (UWB) digital pulse generator according to a preferred embodiment of the present invention
2 is an operation timing diagram of FIG. 1.
FIG. 3 is a circuit diagram of a time delay cell shown in FIG. 1.
4 is a view showing the structure and principle of the pulse detection circuit shown in FIG.
FIG. 5 is a circuit diagram of a Gaussian envelope shaper shown in FIG. 1.
6A to 6D are graphs of output measurement of a digital pulse generator according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In order to clearly explain the present invention in the drawings, parts not related to the description are omitted, and similar parts are denoted by similar reference numerals throughout the specification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Example

1 is an overall configuration diagram of an ultra wideband (UWB) digital pulse generator according to a preferred embodiment of the present invention, Figure 2 is an operation timing diagram of FIG.

As shown in FIG. 1, the ultra wideband (UWB) digital pulse generator includes a time delay circuit 10, a latch circuit 20, a pulse sensing circuit 30, and a Gaussian envelope shaper. 40 is comprised.

The time delay circuit 10 inputs a first clock pulse Ref. CLK (see FIG. 2A) to generate a plurality of time delay pulses (see FIG. 2B) having a constant time delay. do. The configuration can be configured by connecting a plurality of inverters in series. In this case, the inverter may adjust the speed of the time delay by using a current.

The first inverter of the plurality of inverters constituting the time delay circuit 10 outputs the first clock pulse Ref.CLK (FIG. 2A) by a predetermined time delay, and the second inverter outputs the first inverter. Delay the pulse signal output from the first inverter for a certain time and output it. In this way, the N-th inverter outputs the pulse signal output from the immediately preceding inverter (N-1 th) by a predetermined time delay. Therefore, the time delay circuit 10 may generate several time delay pulses having a constant time delay (see FIG. 2B).

The latch circuit 20 receives a plurality of time delay pulses ((b) of FIG. 2) from the time delay circuit 10 to enable the second clock pulse CLK in the enable period. A plurality of time delay pulses (Fig. 2B) are output to the output terminal Q. The configuration can be constructed using a plurality of D-latch.

Here, the second clock pulse CLK input to the plurality of D-latch includes a time delay pulse and a first clock pulse that are output last from among the plurality of time delay pulses of the time delay circuit 10. Can be generated by a logical combination of (Ref.CLK).

For example, the generation circuit of the second clock pulse CLK, which is input to the plurality of D-latch, is a time delay outputted last of the plurality of time delay pulses of the first time delay circuit 10. Inverter G1 for inverting the polarity by inputting a pulse and outputting the signal, and AND gate G2 for outputting the output signal of the inverter G1 and the first clock pulse Ref.CLK by logical AND. Can be configured.

Here, the second clock pulse CLK output from the AND gate G2 may be configured as a pulse signal as shown in FIG. Specifically, the second clock pulse CLK has the same period as the first clock pulse Ref.CLK (FIG. 2A), but adjusts a duty cycle to control the first clock. The second clock pulse CLK may be generated only at a rising time of the pulse Ref.CLK.

The plurality of D-latch includes a data input terminal D, a clock input terminal CLK, an output terminal Q, and a clear terminal, respectively. The data input terminal D is a terminal for inputting a plurality of time delay pulses output from the time delay circuit 10, and the clock input terminal CLK is a terminal for inputting the second clock pulse CLK. The output terminal Q is a terminal for outputting the plurality of time delay pulses input through the data input terminal D by the second clock pulse CLK. The clear terminal is a terminal for controlling each of the pulse signals output through the output terminal Q by a clear control signal.

Therefore, the plurality of D-latch may output the plurality of time delay pulses input from the data input terminal D to the output terminal Q by the second clock pulse CLK. . In addition, the plurality of D-latch may control ON / OFF of the pulse signal output through the output terminal Q by the clear control signal.

Accordingly, the digital pulse generator controls the Gaussian envelope by controlling ON / OFF of pulse signals output from the plurality of D-latch using the clear control signal. The ON / OFF of each pulse output through the shaper (Gaussian envelope shaper) 40 may be controlled. Thereby, the bandwidth of the output frequency can be adjusted.

The pulse sensing circuit 30 inputs a plurality of time delay pulses output from the latch circuit 20 and outputs pulse signals corresponding to signal delays delayed by the time delay circuit 10, respectively. The configuration can be configured using a plurality of Exclusive-OR gates.

The plurality of exclusive-OR gates respectively input two time delay pulses output from the latch circuit 20 to obtain a pulse signal corresponding to a signal difference delayed by the exclusive-OR logic. Output each (see FIG. 4).

For example, when the first Exclusive-OR gate is inputted with the output signal of the first and second D-latch, the Exclusive-OR logic combination, the first and second A pulse signal corresponding to a delayed signal difference between two signals output from the D-latch may be output. Similarly, the second Exclusive-OR gate inputs the output signal of the third and fourth D-latch to combine the Exclusive-OR logic, the third and fourth A pulse signal corresponding to a delayed signal difference between two signals output from the D-latch may be output.

As such, the pulse detection circuit 30 may input two time delay pulses output from the latch circuit 20 to output pulse signals corresponding to the delayed signal differences.

In this way, a signal capable of acquiring a plurality of impulses is generated by the time delay circuit 10 and the latch circuit 20 by using a single digital input signal to generate the Exclusive-OR gate. Through the pulse detection circuit 30 such as to generate a pulse.

The Gaussian envelope shaper 40 combines the pulse signals output from the pulse sensing circuit 30 into one to output an impulse signal having a shape of one Gaussian shape (FIG. 2 (see FIG. 2). d)).

The Gaussian envelope shaper 40 includes a plurality of first amplifiers for inputting and amplifying pulse signals output from the pulse sensing circuit 30, and a signal output from the plurality of first amplifiers as one. The second amplifier may be configured to output an impulse signal having a shape of one Gaussian shaper. The configuration and operation of the Gaussian envelope shaper 40 will be described in detail later with reference to FIG. 5.

As described above, the ultra wide band UWB of the embodiment generates a plurality of time delay pulses by using the first clock pulse Ref. CLK in the time delay circuit 10. The latch circuit 20 outputs a plurality of time delay pulses input from the time delay circuit 10 to the pulse detection circuit 30 by the second clock pulse CLK. At this time, the latch circuit 20 may adjust the number of pulses required by the clear control signal (Clear Control), thereby adjusting the bandwidth of the pulse train (bandwidth). In addition, the clock signal of the latch circuit 20 is supplied by the inverter G1 and the gate G2. This allows the pulse train to be created only at the rising edge of the data signal, with the same period as the data clock but with different duty.

The pulse detection circuit 30 generates a pulse signal that detects a difference between the delayed signals using a plurality of time delay pulses input through the latch circuit 20. Thereafter, the Gaussian envelope shaper 40 combines the pulse arrays output from the pulse sensing circuit 30 into one to output an impulse signal having a shape of one Gaussian shaper.

Therefore, the digital pulse generator can freely implement a desired frequency bandwidth by adjusting the number of pulses generated by arbitrarily turning on / off each pulse by the clear control signal.

Embodiment of the time delay circuit 10

3 is a circuit diagram of the time delay circuit 10 shown in FIG.

The time delay circuit 10 may be configured of a plurality of inverters that can adjust the speed of the time delay using a current. In this case, the inverter may have a current mirror structure.

For example, as shown in FIG. 3, a second MOS connected between a power supply voltage VDD terminal and a ground voltage Vss terminal and controlled by a signal of the first node Nd1. Third and first connected in series between a transistor Q2 and the power supply voltage VDD terminal and a third node Nd3 and controlled by a signal and a clock signal Clock of the first node Nd1, respectively. A fifth MOS transistor (MOS) connected between the MOS transistors Q3 and Q1 and the power supply voltage VDD terminal and the ground voltage Vss terminal and controlled by a signal of the second node Nd2 ( Q5) and fourth and sixth MOSs connected in series between the third node Nd3 and the ground voltage Vss terminal and controlled by the signals of the clock signal Clock and the second node Nd2, respectively. (MOS) transistors Q4 and Q6 and are connected between the power supply voltage VDD terminal and the output terminal Nd4 and controlled to the signal of the third node Nd3. An eighth MOS transistor Q8 connected between a seventh MOS transistor Q7 and the output terminal Nd4 and a ground voltage Vss terminal and controlled to a signal of the third node Nd3. It can be composed of).

The first to third and seventh MOS transistors Q1 to Q3 and Q7 may be PMOS transistors, and the fourth to sixth and eighth MOS transistors Q4 to Q6. Q8 may be configured as an NMOS transistor.

The second and third MOS transistors Q2 and Q3 and the fifth and sixth MOS transistors Q5 and Q6 have a current mirror structure, respectively. When the clock signal Clock is "0", the first and eighth MOS transistors Q1 and Q8 are turned on to output "0" to the output terminal Nd4, and the clock signal Clock When "1" is "1", the fourth and seventh MOS transistors Q4 and Q7 are turned on to output "1" to the output terminal Nd4. In this case, the pulse signal output to the output terminal Nd4 is driven by the first, fourth, seventh and eighth MOS transistors Q1, Q4, Q7 and Q8 from the clock signal Clock. This signal is delayed by time.

Accordingly, the time delay circuit 10 uses the plurality of inverters to generate a plurality of time delay pulses having a predetermined time delay from the first clock pulse Ref. CLK (see FIG. 2A) (FIG. 2). In (b)).

Embodiment of the pulse sensing circuit 30

4 is a view showing the structure and principle of the pulse detection circuit 30 shown in FIG.

As shown in FIG. 4, the pulse sensing circuit 30 inputs two time delay pulses output from two D-latches in the latch circuit 20, respectively, to form an Exclusive-OR logic. It may be composed of a plurality of Exclusive-OR gate (Gate) for outputting the pulse signal corresponding to the delayed signal difference by each.

The Exclusive-OR gate outputs "0" when both input signals have "0" or "1", and outputs "1" when the two input signals have different values. do.

Therefore, the pulse detection circuit 30 may output pulse signals corresponding to the time delayed signal difference in the time delay circuit 10 by the logical combination of the exclusive-OR gate.

Embodiment of Gaussian Envelope Shaper 40

5 is a circuit diagram of the Gaussian envelope shaper 40 shown in FIG.

As shown in FIG. 5, the Gaussian envelope shaper 40 includes a plurality of first amplifiers 41 that input and amplify pulse signals output from the pulse sensing circuit 30, respectively. The second amplifier 42 may output an impulse signal having a form of a Gaussian shaper by combining the signals output from the plurality of first amplifiers 41 into one. Here, the plurality of first amplifiers 41 may have different gains.

The plurality of first amplifiers 41 are connected in series between, for example, a terminal of a power supply voltage VDD and an output terminal, and are output from a second bias signal bias2 and the pulse sensing circuit 30. The first and second pull-up drivers Q11 and Q12 controlled by a pulse signal, and are connected in series between the output terminal and the ground voltage Vss terminal and are outputted from the pulse sensing circuit 30. The first and second pull-down drivers Q11 and Q12 controlled by the pulse signal and the first bias signal bias1 may be configured.

Here, the first and second pull-up drivers Q11 and Q12 may be configured as PMOS transistors, and the first and second pull-down drivers Q13 and Q14 may be configured as NMOS transistors.

In the first amplifier 41 having the above configuration, when the first and second bias signals bias1 and bias2 are active, the pulse signal output from the pulse sensing circuit 30 is "1". When the first pull-down driver Q13 is driven to output "0" to the output terminal (output), when the pulse signal output from the pulse sensing circuit 30 is "0", the second pull The up-up driver Q12 is driven to output "1" to the output terminal. At this time, the pulse signal output to the output terminal (output) is an amplified signal inverted the pulse signal output from the pulse detection circuit 30.

Meanwhile, as another example, the first and second pull-up drivers Q11 and Q12 and the first and second pull-down drivers Q13 and Q14 may both be configured with NMOS transistors, and the second pull-up may be used. An inverter may be configured at the gate of the driver Q12 or the first pull-down driver Q13.

The plurality of first amplifiers 41 may configure gains differently to amplify and output the pulse signals output from the pulse sensing circuit 30, respectively. At this time, the pulse signal input to the plurality of first amplifiers 41 from the pulse detection circuit 30 is different in magnitude and generation time of the pulses as shown in FIG. 5.

Meanwhile, the plurality of first amplifiers 41 may be configured to have the same gain to amplify and output the pulse signals output from the pulse sensing circuit 30, respectively.

The second amplifier 42 combines the signals output from the plurality of first amplifiers 41 into one to output an impulse signal having a form of a Gaussian shaper. The second amplifier 42 may be configured as an inverter such as the first amplifier 41.

Accordingly, the Gaussian envelope shaper 40 having the above configuration outputs an impulse signal having a Gaussian shape by combining the pulse signals output from the pulse sensing circuit 30 into one. can do.

The pulse signal input to the Gaussian envelope shaper 40 has the same magnitude and the same time delay, and passes through the Gaussian envelope shaper 40, such as a Gaussian shape. It has a pulse shape. This suppresses side lobes in the frequency plot to ensure the purity of the main signal.

The Gaussian envelope shaper 40 is made by the size and bias of different transistors for each pulse, and the outputs are combined into one form of a Gaussian shape. It has an impulse signal with. Meanwhile, the results measured in FIG. 6 are shown to confirm the characteristics of the Gaussian envelope shaper 40 for the low side lobe.

Example of output measurement graph

6A to 6D are graphs of output measurement of the digital pulse generator according to the present invention. 6A is a 3.5 GHz operating frequency, FIG. 6B is a 4.1 GHz operating frequency, FIG. 6C is a 4.7 GHz operating frequency, and FIG. 6D is an output measurement graph of the digital pulse generator when the operating frequency is 6.5 GHz. It can be seen that Gaussian impulse signals each having the output of? In addition, a side lobe having a difference of about 20 dBc and a size of 18 dBc may be identified as compared to a main lobe.

As described above, the present invention adds a Gaussian shaper to make the side lobe smaller in conventional impulse generation, and simultaneously adjusts the impulse row to adjust the frequency bandwidth ( bandwidth) and operating frequency can be varied.

In addition, the impulse generator based on the conventional delay signal has a lot of difficulties due to many components and inaccurate delays when manufactured in a hybrid form, but in the present invention, the impulse generator is composed of digital logic in the chip. By integrating, the characteristics can be maximized.

In particular, the conventional impulse generator using a simple impulse stringer requires a bandpass filter to reduce the size of the side lobe. However, in the present invention, a Gaussian shaping combiner circuit can be used to eliminate the use of an external bandpass filter. This method eliminates the need to reduce the size of the chip or configure the bandpass filter on the PCB board, resulting in a competitive advantage in lowering the terminals of the system.

In addition, by implementing an impulse generator using digital logic, it is possible to take advantage of very small power consumption.

In addition, in the case of the conventional VCO impulse generator, the bandwidth can be varied by adjusting the time the VCO operates, in the case of the present invention is generated by randomly turning on / off each pulse by the clear control signal. By controlling the number of pulses, the desired frequency bandwidth can be freely implemented. Accordingly, the number of pulses can be arbitrarily implemented in the design, and the pulse train can be arbitrarily adjusted to freely implement a desired bandwidth.

It will be apparent to those skilled in the art that various modifications and changes can be made in the present invention without departing from the spirit or scope of the present invention as defined by the appended claims. It will be appreciated that such modifications and variations are intended to fall within the scope of the following claims.

10: time delay circuit
20: latch circuit
30: pulse detection circuit
40: Gaussian envelope shaper

Claims (13)

A time delay circuit configured to input a first clock pulse to generate a plurality of time delay pulses having a predetermined time delay;
A latch circuit that receives a plurality of time delay pulses from the time delay circuit and outputs the second delayed pulses, and controls the output of the time delay pulses by a clear control signal;
A pulse sensing circuit which receives a plurality of time delay pulses from the latch circuit and outputs a pulse signal corresponding to a signal difference delayed by the time delay circuit; And
A Gaussian envelope shaper which combines the pulse signals output from the pulse sensing circuit into one and outputs an impulse signal having a form of a Gaussian shape;
Lt; / RTI >
The second clock pulse,
Generated by a logical combination of a time delay pulse last output of the plurality of time delay pulses of the time delay circuit and the first clock pulse,
Ultra wideband (UWB) digital pulse generator.
The method of claim 1, wherein the time delay circuit,
Comprising a plurality of inverters for respectively inputting the first clock pulse and outputting a plurality of time delay pulses having a predetermined time delay,
Ultra wideband (UWB) digital pulse generator.
The method of claim 2, wherein the plurality of inverters,
Consisting of a current mirror structure,
Ultra wideband (UWB) digital pulse generator.
delete The circuit of claim 1, wherein the generating circuit of the second clock pulse comprises:
An inverter for inputting a time delay pulse that is output last among the plurality of time delay pulses of the time delay circuit and inverting the polarity to output the time delay pulse; And
An AND gate inputting the output signal of the inverter and the first clock pulse and outputting the result of the AND;
Ultra wideband (UWB) digital pulse generator comprising a.
The method of claim 1, wherein the latch circuit,
Consisting of multiple D-latch,
Ultra wideband (UWB) digital pulse generator.
The pulse detection circuit of claim 1,
Respectively inputting two time delay pulses output from the latch circuit to output a pulse signal corresponding to the delayed signal difference,
Ultra wideband (UWB) digital pulse generator.
The method of claim 7, wherein the pulse detection circuit,
Consists of multiple Exclusive-OR Gates,
Ultra wideband (UWB) digital pulse generator.
The method of claim 1, wherein the Gaussian envelope shaper,
A plurality of first amplifiers each inputting and amplifying a pulse signal output from the pulse sensing circuit; And
A second amplifier for outputting an impulse signal having a form of one Gaussian shape by combining the signals output from the plurality of first amplifiers into one;
Ultra wideband (UWB) digital pulse generator comprising a.
10. The method of claim 9,
The first and second amplifiers are composed of an inverter,
Ultra wideband (UWB) digital pulse generator.
The method of claim 9, wherein the first amplifier or the second amplifier,
First and second pull-up drivers connected in series between a terminal of a power supply voltage and an output terminal and controlled by a second bias signal bias2 and a pulse signal output from the pulse sensing circuit; And
First and second pull-down drivers connected in series between the output terminal and the ground voltage terminal and controlled by a pulse signal and a first bias signal bias1 output from the pulse sensing circuit;
Ultra wideband (UWB) digital pulse generator comprising a.
12. The method of claim 11,
The first and second pull-up drivers are configured as PMOS transistors, and the first and second pull-down drivers are configured as NMOS transistors, or
The first and second pull-up drivers may be configured with NMOS transistors, and the first and second pull-down drivers may be configured with NMOS transistors, and the second pull-up driver or the first pull-down driver may be used. Inverter is configured at the gate of the driver,
Ultra wideband (UWB) digital pulse generator.
The method of claim 1, wherein the digital pulse generator,
Ultra-wideband (UWB) digital pulse generator that can freely implement the desired frequency bandwidth by adjusting the number of pulses generated by the on / off of each pulse by the clear control signal.

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