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KR101250475B1 - Heterogeneous substrate having insulating material pattern and nitride-based semiconductor device using the same - Google Patents

Heterogeneous substrate having insulating material pattern and nitride-based semiconductor device using the same Download PDF

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KR101250475B1
KR101250475B1 KR1020110142814A KR20110142814A KR101250475B1 KR 101250475 B1 KR101250475 B1 KR 101250475B1 KR 1020110142814 A KR1020110142814 A KR 1020110142814A KR 20110142814 A KR20110142814 A KR 20110142814A KR 101250475 B1 KR101250475 B1 KR 101250475B1
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layer
nitride
insulator
base substrate
substrate
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백광현
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전자부품연구원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
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    • H01L21/02389—Nitrides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/024—Group 12/16 materials
    • H01L21/02403—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

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Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterogeneous substrate having an insulator pattern and to a nitride based semiconductor device using the same, and to forming a nonpolarized or semipolarized nitride layer having a low internal bonding on a base substrate such as sapphire. According to the present invention, the heterogeneous substrate includes a base substrate, an insulator pattern, a crystal growth layer, a buffer layer and a horizontal growth layer. The base substrate has either a nonpolarized or semipolarized surface. The insulator pattern is formed in a plurality of polygonal patterns on the surface of the base substrate, and has a refractive index different from that of the base substrate. The nitride-based crystal growth layer is formed on the surface of the base substrate exposed between the insulator patterns. The buffer layer is formed on the basis of the crystal growth layer, and grows faster in the vertical direction than in the horizontal direction to cover the nitride-based crystal growth layer and the insulator pattern. The horizontal growth layer is grown on the buffer layer and grows faster in the horizontal direction than in the vertical direction.

Description

Heterogeneous substrate having insulating material pattern and nitride-based semiconductor device using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to form an insulator pattern on a base substrate such as sapphire, and to form a heterogeneous substrate having a high quality nonpolarized or semipolarized nitride layer thereon and a nitride system using the same. It relates to a semiconductor device.

Nitride-based single crystal semiconductor substrates such as gallium nitride (GaN), which are used as substrates in the manufacture of semiconductor devices, are mostly nitride films of c plane ({0001} plane), mainly on c plane ({0001} plane) of sapphire substrates. It is obtained after growing by the method of Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE) or hydride vapor phase epitaxy (HVPE).

The c-plane nitride-based single crystal film thus formed has a polarity because, for example, a gallium layer and a nitrogen layer are repeatedly stacked in the c-crystal axis direction. For example, in the case of GaN / AlGaN / InGaN heterostructures with c planes, the electronic band structure in the heterostructures is caused by a strong electric field formed by spontaneous polarization or piezoelectric polarization. By tilting the band structure, the carrier recombination rate is reduced, resulting in lower quantum efficiency.

In detail, there is a polarization discontinuity in the c-axis growth direction, which creates a fixed sheet charge at the surface or interface, resulting in an internal electric field in the quantum well. The separation of electron and hole wavefunctions shifts light emission toward long wavelengths, and when an electric field is applied, light emission wavelengths shift toward shorter wavelengths, making it difficult to develop devices for long wavelengths.

In contrast, the a-plane ({11-20} plane) and the m-plane ({1-100} plane) nitride-based crystals have non-polar characteristics, so that the c-plane nitride-based single crystals described above are The problem, that is, the problem that the quantum efficiency is reduced by the internal electric field due to polarization can be overcome. A-plane nitride-based crystals do not have a polarization field, so no band bending occurs, and a stark effect is not observed in an AlGaN / GaN / InGaN quantum well grown on an unpolarized crystal surface. Therefore, the a-polarized nitride-based heterostructure on the a side has a possibility that it can be usefully used for the light emitting device and the high electron mobility transistor (HEMT) in the high-efficiency ultraviolet-visible region.

In addition, the a-plane nitride-based film has a higher concentration of p-doping than the c-plane nitride-based single crystal film. This is because the energy on the a side is much lower because the activation energy is 118 meV on the a side and 170 meV on the c side. In general, as more Al is included in GaN, the doping efficiency is drastically reduced, which is higher in the a plane than the c plane.

As described above, despite the fact that the nonpolarized nitride-based single crystal film has more advantages than the c plane, the reason why it is not manufactured and commercialized as a substrate is that it is difficult to obtain the surface of the obtained smooth film, and it is relatively more internal than the c plane. Because it has a defect.

Specifically, the a-plane nitride-based single crystal film is obtained by growing on the r-plane ({1-102} plane) sapphire single crystal substrate. In this case, a nitride film having a surface shape such that the ridges having {1010} planes extending in the <0001> direction instead of the flat shape film is formed, and in-plane thermal expansion with anisotropy of lattice constant is formed. Because of the large anisotropy along the crystallographic direction of the modulus, a strong compressive stress acts in the <1-100> direction of the nitride.

In the case where the a-plane nitride single crystal is grown into a thick film or a thin film, a film in which the mountain structure is not coalesced is grown, which forms many defects in the film. Poor surface geometry and defects make the device difficult to fabricate, and its presence on the substrate surface ultimately adversely affects the performance of the final thin film device.

Accordingly, it is an object of the present invention to reduce the number of defects, particularly propagation potential and stacking defects, present in nonpolarized or semipolarized nitride layers, and to planarize rough surface shapes to improve the properties of the active layer or double junction structure grown thereon. SUMMARY OF THE INVENTION An object of the present invention is to provide a heterogeneous substrate having an insulator pattern capable of improving the performance of the semiconductor device and a nitride semiconductor device using the same.

In order to achieve the above object, the present invention provides a heterogeneous substrate comprising a base substrate, and a nitride layer of one of the non-polarized or semi-polarized surface formed in multiple layers on one surface of the base substrate. The nitride layer includes a first insulator pattern, a nitride-based crystal growth layer, a first buffer layer, and a horizontal growth layer. The first insulator pattern is formed in a plurality of straight or polygonal patterns on one surface of the base substrate, and has a refractive index different from that of the base substrate. The crystal growth layer is formed on a surface of the base substrate exposed between the first insulator patterns. The first buffer layer is grown based on the seed crystal growth layer, and grows faster in the vertical direction than in the horizontal direction to cover the nitride based seed growth layer and the first insulator pattern. The horizontal growth layer is grown on the first buffer layer and is formed to grow faster in the horizontal direction than in the vertical direction.

In the heterogeneous substrate according to the present invention, the nitride layer may further include a second insulator pattern and a second buffer layer. The second insulator pattern is formed on the horizontal growth layer. The second buffer layer may grow at the same or faster rate of growth in the horizontal direction than the vertical direction based on the horizontal growth layer exposed between the second insulator patterns to cover the horizontal growth layer and the second insulator pattern.

In the heterogeneous substrate according to the present invention, the material of the first and second insulator patterns may include at least one of SiO 2 , SiN X, and TiO 2 .

In the heterogeneous substrate according to the present invention, the first and second insulator patterns are hexagonal patterns aligned in the c-axis direction when the nitride layer is a nonpolarized a-plane nitride layer, and the nitride layer is semipolarized. } The surface nitride layer may be a straight line pattern aligned in the m-axis direction.

In the heterogeneous substrate according to the present invention, the base substrate may be one of SiC, ZnO, AlN, and LiAlO 3 substrates, and the nonpolarized or semipolar surface may be one of a surface, r surface, or m surface.

In the heterogeneous substrate according to the present invention, the nitride-based crystal growth layer may be one of GaN, Al x Ga 1-x N, In x Ga 1-y N (0 <x, y <1).

The present invention also provides a nitride-based semiconductor device using the heterogeneous substrate described above. The nitride-based semiconductor device is formed of the first nitride layer of the n-type or p-type formed on the hetero substrate, the hetero substrate, the active layer formed on the first nitride layer, and formed on the active layer and opposite to the first nitride layer. A second nitride layer of the type.

The heterogeneous substrate according to the present invention forms a nitride layer using an insulator pattern formed on a base substrate, thereby reducing many defects, particularly propagation potential and stacking defects, present in the non-polarized or semi-polarized nitride layer, and reducing the rough surface shape. The planarization can improve the performance of the nitride-based semiconductor device by improving the characteristics of the active layer or the double junction structure grown thereon.

In particular, the hetero-substrate according to the invention forms a non-polarized or semi-polarized nitride layer by controlling the crystal growth mode using an insulator pattern formed on the base substrate, thereby flattening and having low internal defects on the base substrate. A layer can be formed. That is, after the crystal growth layer is formed on the base substrate by using the insulator pattern, the buffer layer is formed on the crystal growth layer so as to grow faster in the vertical direction than in the horizontal direction, and further on the buffer layer in the horizontal direction than in the vertical direction. By forming the horizontal growth layer so as to grow rapidly, it is possible to form a non-polarized or semi-polarized nitride layer having a flat and small internal defect on the base substrate.

1 is a flowchart illustrating a method of manufacturing a heterogeneous substrate having an insulator pattern according to a first embodiment of the present invention.
2 to 8 are diagrams illustrating each step according to the method of manufacturing the heterogeneous substrate of FIG. 1.
9 is a photograph taken of the surface of the heterogeneous substrate according to the first embodiment of the present invention after the optical microscope.
FIG. 10 is a photograph of specimens of heterogeneous substrates prepared by a manufacturing method according to a first embodiment of the present invention with Cathode Luminescence (CL).
11 is a TEM photograph of a heterogeneous substrate according to the first embodiment of the present invention.
12 is a cross-sectional view illustrating a nitride based semiconductor device using a heterogeneous substrate according to a first embodiment of the present invention.
13 is a diagram for describing a semiconductor device formed on a heterogeneous substrate according to a first embodiment of the present invention.
14 is a photograph showing a state in which light is generated by applying power to the nitride-based semiconductor device of FIG. 13.
FIG. 15 is a graph illustrating a difference in light output between a heterogeneous substrate and a conventional heterogeneous substrate according to the first embodiment of the present invention. FIG.
16 is a flowchart illustrating a method of manufacturing a dissimilar substrate having an insulator pattern according to a second embodiment of the present invention.
17 to 19 are diagrams illustrating respective steps according to the method of manufacturing the heterogeneous substrate of FIG. 16.

In the following description, only parts necessary for understanding the embodiments of the present invention will be described, and the description of other parts will be omitted so as not to obscure the gist of the present invention.

The terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary meanings and the inventor is not limited to the meaning of the terms in order to describe his invention in the best way. It should be interpreted as meaning and concept consistent with the technical idea of the present invention. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely preferred embodiments of the present invention, and are not intended to represent all of the technical ideas of the present invention, so that various equivalents And variations are possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

A method of manufacturing the heterogeneous substrate 10 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 8. 1 is a flowchart of a method of manufacturing a heterogeneous substrate 10 having an insulator pattern 12 according to a first embodiment of the present invention. 2 to 8 are diagrams illustrating respective steps according to the method of manufacturing the heterogeneous substrate 10 of FIG. 1.

First, as shown in FIG. 2, the base substrate 11 is prepared (S61). As the base substrate 11, a sapphire substrate may be used, and other substrates such as SiC, ZnO, AlN, LiAlO 3, or the like may be used. At this time, in order to form the nitride layer of the non-polarized or semi-polarized surface, as the base substrate 11, a surface except for the c surface, a surface, r surface, m surface or other surface may be used. In this embodiment, in order to form the a-plane nitride layer (18 in FIG. 8), a sapphire substrate having an r-plane is used as the base substrate 11. On the other hand, when forming the nitride layer of semi-polarization {11-22}, a sapphire substrate having an m surface may be used as the base substrate 11.

Next, as shown in FIG. 3, an insulator film 12a is formed on the upper surface of the base substrate 11 by using an insulator (S63). The insulator film 12a uses a material having a refractive index different from that of the base substrate 11. In this case, the insulator film 12a may be formed using a deposition method such as PECVD using a material such as SiO 2 , SiN X , TiO 2, or the like. Next, as shown in FIG. 4, the insulator film 12a is patterned to form the insulator patterns 12 (S65). 5 illustrates a state in which the insulator pattern 12 is formed on the base substrate 11. In the patterning, after the photoresist is applied on the insulator film 12a, the photoresist film is removed so that the insulator film 12a in the remaining areas except the region where the pattern is formed is exposed, and then the insulator in the region where the photoresist film is removed. The film 12a is etched to form the insulator pattern 12.

In this case, the insulator pattern 12 may be formed in a plurality of stripes or polygonal patterns. The pattern has a period of several μm and the spacing may also be a few μm. For example, when the nitride layer is a semi-polarized {11-22} plane nitride layer, the insulator pattern 12 may be formed in a linear pattern aligned in the m-axis direction. In addition, the insulator pattern 12 may be formed in a quadrangle, a hexagon, or the like, and an example in which the insulator pattern 12 is formed in a hexagon is disclosed. In particular, in the case of hexagons, it is important to form a pattern by aligning in the c-axis direction when growing a specific direction, for example, a-plane nitride layer (18 in FIG. 8). By forming in this way, when the a-plane nitride layer (18 in FIG. 8) is grown on the base substrate 11, the propagation potential and the lamination defects can be reduced, and the rough surface shape can be flattened. Detailed description thereof will be described later.

6 to 8, a crystal growth layer 13, a buffer layer 14, and a horizontal growth layer 15 are formed on the base substrate 11 on which the plurality of insulator patterns 12 are formed. The a-side nitride layer 18 is formed (S67, S69, S71). The a-plane nitride layer 18 can be formed by MOCVD, MBE, or HVPE, and in the first embodiment, it is formed by MOCVD. Here, the a-plane nitride layer 18 has a structure in which the crystal growth layer 13, the buffer layer 14, and the horizontal growth layer 15 are sequentially stacked on the base substrate 11 on which the insulator pattern 12 is formed.

A method of forming the a surface nitride layer 18 will be described below with reference to FIGS. 6 to 8.

First, as shown in FIG. 6, the crystal nucleus growth layer 13 is formed on the base substrate 11 on which the plurality of insulator patterns 12 are formed (S67). At this time, the nitride-based crystal growth layer 13 is formed at a ratio of V / III at 50 ~ 3000 in a nitrogen or hydrogen atmosphere of 450 ℃ ~ 1300 ℃, 30 ~ 760 torr. Since the thickness of the crystal growth layer 13 affects the crystallinity of the a-plane nitride layer 18 growing thereon, the crystal growth layer 13 is preferably formed to a thickness of 5 to 700 nm. It is formed to 70 ~ 250nm. In this case, the nitride-based crystal growth layer 13 may be formed of one of GaN, Al x Ga 1-x N, and In x Ga 1-y N (0 <x, y <1). In the first embodiment, a-plane GaN was used as the nitride-based crystal growth layer 13.

Next, as shown in FIG. 7, the buffer layer 14 is grown on the crystal growth layer 13 (S69). The buffer layer 14 is formed on the nucleus growth layer 13 by growing faster in the vertical direction than in the horizontal direction. The buffer layer 14 is grown in an atmosphere having a V / III ratio of 50 to 2000, 450 to 1300 ° C, and 100 to 760 torr. The buffer layer 14 grown under such conditions has a rough surface, but results in a decrease in the full width of half maximum (FWHM) value of the a plane, which is scanned by X-ray diffraction (XRD) in a direction parallel to the m-axis. You can get it.

As shown in FIG. 8, the horizontal growth layer 15 is grown on the buffer layer 14 (S71). The horizontal growth layer 15 is formed on the buffer layer 12 by growing faster in the horizontal direction than in the vertical direction. The horizontal growth layer 15 is grown at a ratio of V / III of 2 to 1000, 800 ° C to 1500 ° C, and 10 to 300 torr. The horizontal growth layer 15 is grown at a relatively low V / III ratio compared to the buffer layer 14. The horizontal growth layer 15 grown under such conditions has a flat mirror-like surface, and the FWHM value of the a plane scanned by XRD in the direction parallel to the c-axis can be obtained. This shows that the crystallinity of gallium nitride grown in the c-axis direction is good. In addition, it can be seen that the FWHM value of the a plane scanned by XRD in a direction parallel to the c-axis decreases.

As described above, in the heterogeneous substrate 10 according to the first embodiment, the a-plane nitride layer 18 is formed by controlling the crystal growth mode using the insulator pattern 11 formed on the base substrate 11, thereby forming the base substrate 11. The a-plane nitride layer 18 may be formed on the planar layer and have a small internal defect. That is, after the insulator pattern 11 is formed on the base substrate 11, the crystal growth layer 13 is formed, and the buffer layer 14 is grown faster on the crystal growth layer 13 in the vertical direction than in the horizontal direction. ) And the horizontal growth layer 15 formed on the buffer layer 14 so as to grow faster in the horizontal direction than in the vertical direction, thereby forming a planar nitride layer 18 flat on the base substrate 11 and small in internal defects. Can be formed.

As described above, the a-plane nitride layer 18 of the dissimilar substrate 10 according to the first embodiment is flat and free from internal defects. In this case, the dissimilar substrate 10 manufactured according to the first embodiment uses an r surface sapphire substrate as the base substrate 11, forms an insulator pattern 11 on the r surface of the sapphire substrate, and then a surface nitride layer ( 18) has a formed structure. At this time, SiO 2 was used as the insulator pattern 11 and GaN was used as the a-plane nitride layer 18.

9 is a photograph taken of the surface of the heterogeneous substrate 10 according to the first embodiment of the present invention after the optical microscope. As shown in FIG. 9, due to the difference in refractive index, the surface a surface nitride layer 18 and the insulator pattern 12 present on the base substrate 11 can be observed. It can also be seen that the surface is very smooth and planarized so that no pits are observed.

In addition, FIG. 10 is a photograph of a specimen of a heterogeneous substrate 10 manufactured by a manufacturing method according to a first embodiment of the present invention by CL (Cathode Luminescence). As shown in FIG. 10, it can be seen that the optical properties of the a-plane nitride layer 18 on the insulator pattern 12 are greatly improved. That is, it can be seen that the quality of the a-plane nitride layer 18 on the insulator pattern 12 is very good.

On the other hand, there are two methods for better light emission from a light emitting device in a general semiconductor device. That is, a method of forming ELOG (Epitaxial Lateral Over Growth, or ELO, LEO, and PENDEO, etc.) using a pattern on the base substrate, and changing the path difference of the light to further emit light There is a Patterned Sapphire Substrate (PSS) method. However, in the method of forming an ELOG, after forming a nitride layer on the base substrate, a pattern must be formed and then nitride is formed again. In other words, regrowth is necessary to increase crystallinity. In addition, the PSS method must etch the base substrate. On the other hand, in the case of the first embodiment, the base substrate 11 is not etched, and more light can be emitted through the addition of a simple process of forming the insulator pattern 12 on the base substrate 11.

11 is a TEM photograph of a heterogeneous substrate according to the first embodiment of the present invention. Referring to FIG. 11, it is confirmed that the hetero substrate 10 according to the first embodiment is formed on the insulator pattern 11 with the a-plane nitride layer 18 flat on the r surface of the base substrate 11 and having small internal defects. Can be. In addition, it can be seen that the a-plane nitride layer 18 has a very improved crystallinity.

Meanwhile, the heterogeneous substrate 10 according to the first embodiment may be used as a substrate for various electronic devices, including a light emitting device such as a light emitting diode (LED) and a laser diode (LD).

The nitride based semiconductor device 100 using the dissimilar substrate 10 according to the first embodiment may be implemented as shown in FIGS. 12 and 13. 12 is a cross-sectional view illustrating a nitride based semiconductor device 100 using a heterogeneous substrate 10 according to a first embodiment of the present invention. FIG. 13 is a diagram for describing a semiconductor device implemented as an LED formed on a heterogeneous substrate 10 according to a first embodiment of the present invention.

12 and 13, the semiconductor device 100 according to the first embodiment may include a first nitride layer 20, an active layer 30, and a second layer on the a-plane nitride layer 18 of the heterogeneous substrate 10. The nitride layer 40 is an LED having a stacked structure sequentially.

The thickness of the a-plane nitride layer 18 of the dissimilar substrate 10 is about 4 μm.

The first nitride layer 20 is an n-type semiconductor including an n-type dopant, and an n-GaN-based group III-V nitride compound semiconductor may be used. The first nitride layer 20 may be formed to a thickness of about 2 μm.

The active layer 30 may be formed on the first nitride layer 20 with InGaN / GaN 4QWs having a thickness of 4 nm / 10 nm.

The second nitride layer 40 is a p-type semiconductor including a p-type dopant, and a p-GaN-based group III-V nitride compound semiconductor may be used. The second nitride layer 40 may be formed to a thickness of about 150 nm.

Meanwhile, in the first embodiment, a structure in which an n-type first nitride layer 20, an active layer 30 and a p-type second nitride layer 40 are sequentially stacked on the a-plane nitride layer 18 is illustrated. It is not limited to this. For example, the nitride-based semiconductor device 100 may have a structure in which a p-type first nitride layer, an active layer, and an n-type second nitride layer are formed on the a-plane nitride layer 18.

The semiconductor device 100 according to the first embodiment has a structure in which a heterogeneous substrate 10, a first nitride layer 20, an active layer 30, and a second nitride layer 40 are sequentially stacked. The second nitride layer 40, the active layer 30, and the first nitride layer 20 are etched to expose a portion of the 20. Then, the electrodes 50 and 60 are formed on the first nitride layer 20 and the second nitride layer 40 to complete the light emitting device (LED). Each of the electrodes 50 and 60 may be n-type and p-type electrodes according to the doping of the first nitride layer 20 and the second nitride layer 40. For convenience of description, the first nitride layer 20 and the second nitride layer 40 are doped with n-type and p-type, respectively, and accordingly, reference numeral 50 denotes an n-type electrode, and reference numeral 60 denotes a p-type electrode. Assume However, it may be reversed depending on the doping of the first nitride layer 20 and the second nitride layer 40.

As described above, the nitride-based semiconductor device 100 using the dissimilar substrate 10 according to the first embodiment has a light emitting layer on the a-plane nitride layer 18 containing the insulator pattern 12, as shown in FIG. 14. By forming the light scattering around the insulator pattern 12 it can be confirmed that occurs. 14 is a photograph showing a state in which light is generated by applying power to the nitride-based semiconductor device 100 of FIG. 13.

 In addition, by using the heterogeneous substrate 10 according to the first embodiment, as shown in FIG. 15, it can be confirmed that there is an effect in improving the light extraction efficiency. FIG. 15 is a graph illustrating a difference in light output of a nitride based semiconductor device using a heterogeneous substrate 10 and a conventional heterogeneous substrate according to the first embodiment of the present invention. Conventional heterogeneous substrates have a nitride layer formed on the surface without an insulator pattern.

Referring to FIG. 15, it can be seen that a nitride-based semiconductor device using a heterogeneous substrate containing an insulator pattern according to the first embodiment has an optical output improved by about 50% compared with a conventional nitride-based semiconductor device. This is presumably due to the improvement of light extraction efficiency due to the insulator pattern and the improvement of crystallinity due to the reduction of defects. That is, in the case of a nitride-based semiconductor device, it is estimated that light generated therein scatters in the insulator pattern and thus the light traveling direction is changed to improve the light extraction efficiency.

Second Embodiment

In the meantime, the hetero substrate 10 according to the first embodiment has been described in which the buffer layer 14 and the horizontal growth layer 15 are grown once by using the insulator pattern 12 formed on the base substrate 11. It is not limited to this. By repeating one or more times, the plurality of buffer layers 14 and 19 and the horizontal growth layer 15 may be formed around the insulator patterns 12 and 16 to further improve the crystallinity of the a-plane nitride layer 18.

A method of manufacturing the heterogeneous substrate 110 according to the second embodiment will be described with reference to FIGS. 16 to 19 as follows. FIG. 16 is a flowchart of a method of manufacturing a heterogeneous substrate 110 having insulator patterns 12 and 16 according to a second embodiment of the present invention. 17 to 19 are diagrams illustrating respective steps according to the manufacturing method of the heterogeneous substrate 110 of FIG. 16.

Here, after the insulator pattern 12 (hereinafter, referred to as a 'first insulator pattern') is formed on the base substrate 11, the crystal growth layer 13 and the buffer layer 14 (hereinafter, referred to as a “first buffer layer”) are described. ) And forming the horizontal growth layer 15 (S261 to S271) are the same as the manufacturing method (S61 to S71) of the heterogeneous substrate (Fig. 10) according to the first embodiment, so that the horizontal growth layer 15 The process performed after the formation (S273) will be described below.

As illustrated in FIGS. 17 and 18, the second insulator pattern 16 is formed on the horizontal growth layer 15 (S273). The second insulator pattern 16 may be formed by the same process as the first insulator pattern 15. Alternatively, when silicon nitride (SiN x ) is used as the material of the second insulator pattern 16, it may be formed as follows. In other words, SiH4 (Silene) or Si2H6 (Disylene) and NH3 (Ammonia) gas were used while supplying Ga (gallium), In (Indium), and Al (Aluminum), which are Group III elements, in MOCVD. To form a second insulator pattern 16 made of silicon nitride. In this case, a plurality of holes 17 are formed in the silicon nitride layer of the second insulator pattern 16, and the lower horizontal growth layer 15 is exposed.

As shown in FIG. 19, the manufacturing process of the heterogeneous substrate 110 according to the second embodiment is completed by growing the second buffer layer 19 covering the second insulator pattern 16 (S275). The second buffer layer 19 is grown in an atmosphere having a V / III ratio of 50 to 2000, 450 to 1300 ° C, and 30 to 760 torr, and doping Si for the n-type semiconductor as necessary. The second buffer layer 19 should have the same horizontal growth rate and vertical growth rate, or have a faster horizontal growth rate. It can be seen that the second buffer layer 19 grown under such conditions maintains a flat mirror surface and improves crystallinity. At this time, the first insulator pattern 12, the crystal growth layer 13, the first buffer layer 14, the horizontal growth layer 15, the second insulator pattern 16, and the second buffer layer formed on the base substrate 11 ( 19) forms a surface nitride layer 18.

In particular, the second buffer layer 19 is grown on the horizontal growth layer 15 exposed through the hole 17 of the second insulator pattern 16 so as to cover the second insulator pattern 16. That is, crystals do not grow directly on the second insulator pattern 16, but crystals grow through portions of the horizontal growth layer 15 exposed through the holes 17 of the second insulator pattern 16. In this case, as shown in FIGS. 18 and 19, the crystal grows faster in the vertical direction (V) in the horizontal direction (L) to cover the second insulator pattern (16), thereby the second buffer layer (19) Is formed flat and the crystallinity becomes better.

On the other hand, the embodiments disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

11: base substrate
12, 16: insulator pattern
12a: insulator film
13: crystal growth layer
14, 19: buffer layer
15: horizontal growth layer
18: a surface nitride layer
10, 110: dissimilar substrate
100: nitride semiconductor device

Claims (8)

A base substrate;
It includes; a nitride layer of one of the non-polarized or semi-polarized surface formed in multiple layers on one surface of the base substrate,
The nitride layer,
A first insulator pattern formed on one surface of the base substrate in a plurality of straight or polygonal patterns and having a refractive index different from that of the base substrate;
A nitride-based crystal growth layer formed on a surface of the base substrate exposed between the first insulator patterns;
A first buffer layer grown based on the crystal growth layer and growing faster in the vertical direction than in the horizontal direction to cover the nitride based crystal growth layer and the first insulator pattern;
A horizontal growth layer grown on the first buffer layer and growing faster in the horizontal direction than in the vertical direction; / RTI &gt;
The nitride layer,
A second insulator pattern formed on the horizontal growth layer;
A second buffer layer covering the horizontal growth layer and the second insulator pattern by growing at the same or faster growth rate in the horizontal direction than the vertical direction based on the horizontal growth layer exposed between the second insulator patterns;
Heterogeneous substrate having an insulator pattern, characterized in that it further comprises. delete The method of claim 1,
The substrate of the first and second insulator patterns may include at least one of SiO 2 , SiN X, and TiO 2 . The method of claim 1, wherein the first and second insulator patterns
When the nitride layer is a polarized a-plane nitride layer, the nitride layer is a hexagonal pattern aligned in the c-axis direction,
And the nitride layer is a semi-polarized {11-22} plane nitride layer, wherein the nitride layer is a straight line pattern aligned in the m-axis direction. The method of claim 1,
The base substrate is one of SiC, ZnO, AlN, LiAlO 3 substrate, the non-polarized or semi-polarized surface is a heterogeneous substrate having an insulator pattern, characterized in that one of a surface, r surface or m surface. The method of claim 5,
The nitride-based crystal growth layer is a heterogeneous substrate having an insulator pattern, characterized in that one of GaN, Al x Ga 1-x N, In x Ga 1-y N (0 <x, y <1). Heterogeneous substrates;
A first nitride layer of one of n type or p type formed on the heterogeneous substrate;
An active layer formed on the first nitride layer;
And a second nitride layer formed on the active layer and opposite to the first nitride layer.
The heterogeneous substrate,
A base substrate;
It includes; a nitride layer of one of the non-polarized or semi-polarized surface formed in multiple layers on one surface of the base substrate,
One nitride layer of the non-polarized or semi-polarized surface,
A first insulator pattern formed on one surface of the base substrate in a plurality of straight or polygonal patterns and having a refractive index different from that of the base substrate;
A nitride-based crystal growth layer formed on a surface of the base substrate exposed between the first insulator patterns;
A first buffer layer grown based on the crystal growth layer and growing faster in the vertical direction than in the horizontal direction to cover the nitride based crystal growth layer and the first insulator pattern;
A horizontal growth layer formed on the first buffer layer and growing faster in a horizontal direction than in a vertical direction, wherein the first nitride layer is formed on the first buffer layer; / RTI &gt;
The heterogeneous substrate,
Interposed between the horizontal growth layer and the first nitride layer,
A second insulator pattern formed on the horizontal growth layer;
A second buffer layer covering the horizontal growth layer and the second insulator pattern by growing at the same or faster growth rate in the horizontal direction than the vertical direction based on the horizontal growth layer exposed between the second insulator patterns;
The nitride-based semiconductor device further comprises. delete
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JP2002241198A (en) 2001-02-13 2002-08-28 Hitachi Cable Ltd GaN SINGLE CRYSTAL SUBSTRATE AND METHOD FOR PRODUCING THE SAME
JP2007184433A (en) 2006-01-06 2007-07-19 Mitsubishi Chemicals Corp Semiconductor laminated structure, and semiconductor element formed thereon
KR101028585B1 (en) 2009-06-15 2011-04-12 (주)웨이브스퀘어 Hetero-substrate, ?-nitride semiconductor devices using the same and manufacturing method of thereof

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JP2002241198A (en) 2001-02-13 2002-08-28 Hitachi Cable Ltd GaN SINGLE CRYSTAL SUBSTRATE AND METHOD FOR PRODUCING THE SAME
JP2007184433A (en) 2006-01-06 2007-07-19 Mitsubishi Chemicals Corp Semiconductor laminated structure, and semiconductor element formed thereon
KR101028585B1 (en) 2009-06-15 2011-04-12 (주)웨이브스퀘어 Hetero-substrate, ?-nitride semiconductor devices using the same and manufacturing method of thereof

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