KR101177570B1 - Data Output Buffer of Liquid Crystal Display - Google Patents

Abstract

The present invention relates to a data output buffer of a liquid crystal display device to reduce offset and power consumption.

The data output buffer of the liquid crystal display includes an input unit for compensating an offset by using a capacitor for storing a difference voltage between an input voltage and an output voltage; And an output unit connected between the input terminal and an output terminal to which the output voltage is output, and controlling the output voltage in response to a voltage added with the input voltage and the voltage of the capacitor.

Description

Data Output Buffer of Liquid Crystal Display

1 is a block diagram showing a liquid crystal display device.

FIG. 2 is a block diagram illustrating the data driving circuit shown in FIG. 1 in detail.

3 is a circuit diagram illustrating in detail the data output buffer shown in FIG.

4A to 4C are circuit diagrams showing the operation of the data output buffer shown in FIG.

5 and 6 are views for explaining the channel length modulation phenomenon.

7 is a circuit diagram illustrating a data output buffer according to an embodiment of the present invention.

8A through 8C are circuit diagrams showing operations in column inversion or frame inversion driving of the data output buffer shown in FIG.

9A to 9C are circuit diagrams showing stepwise operation of dot inversion or line inversion driving of the data output buffer shown in FIG.

FIG. 10 is a graph illustrating liquid crystal cell voltage polarity in a column inversion scheme; FIG.

Fig. 11 is a diagram showing the liquid crystal cell voltage polarity in the dot inversion method.

12 is a diagram illustrating a liquid crystal cell voltage polarity in a dot inversion method.

FIG. 13 is a graph showing liquid crystal cell voltage polarity in a line inversion method; FIG.

14 is a diagram illustrating a gate voltage in a column inversion or frame inversion scheme.

FIG. 15 is a diagram illustrating a gate voltage in a dot inversion or line inversion scheme. FIG.

Description of the Related Art

11: Timing Controller 12: Data Driving Circuit

13 gate driving circuit 14 liquid crystal display panel

21: first latch 22: shift register

23 second latch 24 digital-to-analog converter

25: buffer

The present invention relates to a liquid crystal display device, and more particularly, to a data output buffer of a liquid crystal display device to reduce offset and power consumption.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. In an active matrix liquid crystal display device, switching elements are formed for each liquid crystal cell, which is advantageous for displaying a moving image. As the switching device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

FIG. 1 schematically shows a liquid crystal display, and FIG. 2 shows the data driving circuit shown in FIG. 1 in detail.

1 and 2, a liquid crystal display device includes a liquid crystal display panel in which data lines D1 to Dm and gate lines G1 to Gn cross each other and a TFT for driving the liquid crystal cell Clc is formed at an intersection thereof. (14), data pulses (12) for supplying data to the data lines (D1 to Dm) of the liquid crystal display panel 14, and scan pulses to the gate lines (G1 to Gn) of the liquid crystal display panel (14). And a timing controller 11 for controlling the data driving circuit 12 and the gate driving circuit 13.

In the liquid crystal display panel 14, liquid crystal is injected between two glass substrates, and the data lines D1 to Dm and the gate lines G1 to Gn are orthogonal to each other on the lower glass substrate. The TFTs formed at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn liquid crystal the data on the data lines D1 to Dm in response to a scan pulse from the gate lines G1 to Gn. It is supplied to the cell Clc. For this purpose, the gate electrodes of the TFTs are connected to the gate lines G1 to Gn, and the source electrodes are connected to the data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. A common voltage (Vcom) is supplied to the common electrode facing the pixel electrode. Each liquid crystal cell Clc of the liquid crystal display panel 14 is provided with a storage capacitor Cst for maintaining a constant voltage charged in the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc connected to the n-th gate line and the n-1 th front gate line, and is separate from the liquid crystal cell Clc connected to the n-th gate line. It may be formed between common storage lines.

The data driving circuit 12 includes a data register for temporarily storing data RGB from the timing controller 11, a shift register 22 for shifting the clock, and a clock signal CLK from the shift register as shown in FIG. In response to the first latch 21 for sampling data, the second latch 23 and second latch 23 for simultaneously outputting one line of data after latching the data from the first latch 21. Digital-to-analog converter 24, digital-to-analog converter 24 and data lines D1 to Dm for selecting the positive / negative gamma voltages VPG and VNG corresponding to the digital data values And an output buffer 25 connected therebetween.

The gate driving circuit 13 includes a shift register for sequentially generating scan pulses, and a level shifter for shifting the voltage of the scan pulses to a level suitable for driving the liquid crystal cell Clc. The gate driving circuit 13 sequentially supplies scan pulses to the gate lines G1 to Gn under the control of the timing controller 11.

The timing controller 11 controls the gate control signal GDC and the data driving circuit 12 for controlling the gate driving circuit 13 using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal (DDC) includes a source start pulse (SSP), a source shift clock (SSC), a source output signal (SOE), and a polarity signal (POL). do. The source output signal SOE is used as a reference signal for indicating the output time of the data and for indicating a period for removing the reference signal and the offset voltage of the charge share circuit. The gate control signal GDC includes a gate shift clock GSC, a gate output enable GOE, a gate start pulse GSP, and the like.

Meanwhile, in the data driving circuit 12, the output buffer 25 minimizes the output voltage loss of the data driving circuit 12 and quickly transfers the output of the data driving circuit 12 to the data lines D1 to Dm. It is an essential circuit part.

The output buffer 25 includes first to third switches S1 to S3, a capacitor C, an n-MOS FET (nMOS), and a pMOS FET (pMOS) as shown in FIG. 3.

The first switch S1 is connected between the buffer input terminal and one electrode of the capacitor C, and the second switch S2 is connected between the buffer input terminal and the other electrode of the capacitor C. The third switch S3 is connected between the other electrode of the capacitor C and the buffer output terminal. One electrode of the capacitor C is connected to the first switch S1, the nMOS FET nMOS, and the pMOS FET pMOS via the first node n1, and the other electrode of the capacitor C is the second node. It is connected to the 2nd and 3rd switch S3 via (n2). The drain terminal of the nMOS FET (nMOS) is connected to the high potential voltage source VDD, the source terminal of the nMOS FET (nMOS) is connected to the buffer output terminal, and the gate terminal of the nMOS FET (nMOS) is connected to the first node n1. Connected. The source terminal of the pMOS FET (pMOS) is connected to the output terminal of the buffer, the drain terminal of the pMOS FET (pMOS) is connected to the base voltage source, and the gate terminal of the pMOS FET (pMOS) is connected to the first node n1.

Since the output buffer 25 has a voltage drop caused by a threshold voltage (Vth) of the nMOS FET (nMOS) and the pMOS FET (pMOS), such an offset should be removed. To this end, an operation process of the output buffer 25 includes a first section for offset detection and a second section for offset compensation. In the first section, as shown in FIG. 4A, the first and third switches S1 and S3 are closed, the second switch S2 is opened, and the capacitor C is connected in series between the buffer input terminal and the buffer output terminal to the capacitor C. The difference voltage between the buffer input terminal voltage and the buffer output terminal voltage is stored. In the second section, as shown in FIG. 4B, the first and third switches S1 and S3 are opened while the second switch S2 is closed to add the difference voltage stored in the capacitor C to the voltage at the buffer input terminal. The gate voltage is supplied to the gate terminals of the nMOS FET (nMOS) and the pMOS FET (pMOS) to equalize the buffer input terminal voltage and the buffer output terminal voltage.

However, when the output load is increased, for example, when the resolution of the liquid crystal display panel is increased and the capacitive load of the liquid crystal display panel is increased, the current at the buffer output terminal is increased. Therefore, the channel ratio of the nMOS FET (nMOS) and the pMOS FET (pMOS) is increased. (Width / Length ratio) should be increased to increase the current driving capability of nMOS FET (nMOS) and pMOS FET (pMOS). However, if the channel ratio of nMOS FET (nMOS) and pMOS FET (pMOS) is increased, the power consumption increases, and if channel length (L) is decreased to increase the channel ratio, the channel length modulation phenomenon Offset occurs.

The channel length modulation phenomenon is defined as a phenomenon in which the current gradually increases as the drain-source voltage of the MOS FET increases, similar to the early effect of the bipolar junction transistor (BJT). This phenomenon will be described in detail with reference to FIGS. 5 and 6 as follows. Referring to FIG. 5, when the drain-source voltage increases (Vds ≧ Vgs−Vth), the vicinity of the drain of the channel is pinched off. At this time, the drain current becomes Vdsat (voltage drop in the portion except the pinch-off region of the channel) / Rch (parasitic resistance of the channel). Increasing the drain voltage only increases the pinch-off voltage and hardly changes Vdsat. As the pinch-off region increases and the channel length decreases, the Rch decreases slightly, so that the drain current increases. On the other hand, when the channel length, i.e., L is small, the channel length modulation factor λ becomes large, thereby reducing the small signal output resistance and the voltage gain. The decrease in voltage gain causes an offset, and the offset becomes large because the effect of the process deviation is large when L is small compared to the case where L is large from the process side.

Accordingly, an object of the present invention is to provide a data output buffer of a liquid crystal display device to reduce offset and power consumption.

In order to achieve the above object, the data output buffer of the liquid crystal display according to the present invention includes an input unit for compensating the offset using a capacitor for storing the difference voltage between the input voltage and the output voltage; And an output unit connected between the input terminal and the output terminal to which the output voltage is output, and controlling the output voltage in response to a voltage added with the input voltage and the voltage of the capacitor.

The input unit includes: a first switch connected between a first node connected to one electrode of the capacitor and an input terminal to which the input voltage is supplied; A second switch connected between the input terminal and a second node connected to the other electrode of the capacitor; A third switch connected between the first node and a third node connected to an input terminal of the output unit; A fourth switch connected between the second node and the third node; A first pull-up transistor having a drain terminal connected to a high potential voltage source, a source terminal connected to the third node, and a gate terminal connected to the first node; And a first pull-down transistor having a source terminal connected to the third node, a drain terminal connected to a base voltage source, and a gate terminal connected to the first node.

The output unit includes a fifth switch connected between the third node and the output terminal; A second pull-up transistor having a drain terminal connected to the high potential voltage source, a source terminal connected to the output terminal, and a gate terminal connected to the third node; And a second pull-down transistor having a source terminal connected to the output terminal, a drain terminal connected to the base voltage source, and a gate terminal connected to the third node.

While the second and third switches are turned off during the first period, the first, fourth and fifth switches are turned on so that the capacitor C is connected in series between the input terminal and the fifth node.

During the second period following the first period, the first, fourth and fifth switches are turned on while the second and third switches are turned off to determine a difference voltage between the voltage at the input terminal and the voltage at the output terminal. Store in the capacitor.

The second and fifth switches are turned on during the third period following the second period, while the first, third and fourth switches are turned off to connect the capacitor to the gate terminal of the first pull-up transistor and the first. To the gate terminal of the pull-down transistor.

The transistors included in the output unit have a larger channel ratio than the transistors included in the input unit.

The transistors included in the output unit have a smaller channel length than the transistors included in the input unit.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 9.

Referring to FIG. 3, the data output buffer of the liquid crystal display according to the first exemplary embodiment of the present invention is a channel of the MOS FETs nMOS1 and pMOS1 to minimize channel length modulation in a steady state period during which no data is output. The input unit 1 is designed to have a sufficient margin and the output of the steady state period is small, but the channel length is relatively small in the panel driving period in which the data lines of the liquid crystal display panel are driven by the data output, and the gate voltage is The output unit 2 is provided with a buffer input voltage or higher and has a high current driving capability.

The input unit 1 includes first to fourth switches S1 to S4, a capacitor C, a first nMOS FET nMOS1, and a first pMOS FET pMOS1. The first switch S1 is connected between the first node n1 and the buffer input terminal connected to one electrode of the capacitor C, and the second switch S2 is connected between the capacitor C and the fourth switch S4. It is connected between the second node n2 of the buffer and the buffer input terminal. The third switch S3 is connected between the third node n3 and the first node n1 between the fourth switch S1 and the fifth switch S5. The capacitor C is connected between the first node n1 and the second node n2. The drain terminal of the first nMOS FET nMOS1 is connected to the high potential voltage source VDD, the source terminal of the first nMOS FET nMOS1 is connected to the third node n3, and the gate of the first nMOS FET nMOS1 is connected. The terminal is connected to the first node n1. The source terminal of the first pMOS FET pMOS1 is connected to the third node n3, the drain terminal of the first pMOS FET pMOS1 is connected to the base voltage source, and the gate terminal of the first pMOS FET pMOS1 is connected to the first node. It is connected to the node n1. The first nMOS FET (nMOS1) and the first pMOS FET (pMOS1) are designed to have a large channel length, thereby reducing offset and power consumption due to channel length modulation during a steady state without data output.

The output unit 1 includes fifth switches S5, a second nMOS FET nMOS2, and a second pMOS FET pMOS2. The fifth switch S5 is connected between the third node n3 and the buffer output terminal. The drain terminal of the second nMOS FET nMOS2 is connected to the high potential voltage source VDD, the source terminal of the second nMOS FET nMOS2 is connected to the buffer output terminal, and the gate terminal of the second nMOS FET nMOS2 is made of It is connected to three nodes n3. The source terminal of the second pMOS FET pMOS1 is connected to the output terminal of the buffer, the drain terminal of the second pMOS FET pMOS2 is connected to the base voltage source, and the gate terminal of the second pMOS FET pMOS2 is connected to the third node. is connected to (n3). The second nMOS FET (nMOS2) and the second pMOS FET (pMOS2) are designed with a relatively large channel length such that the channel ratio is large, so that the current flows small during the steady state in which no data is output and is driven by the high current driving capability during the panel driving period. do.

The operation of the data output buffer is driven differently according to the inversion method of the liquid crystal display panel. 8A to 8C illustrate a polarity of data supplied to liquid crystal cells in a column inversion scheme (FIG. 10) or a frame period in which polarities of data supplied to liquid crystal cells of neighboring vertical lines are opposite to each other. The operation of the data output buffer in the frame inversion scheme (Fig. 11) opposite to each other is shown in stages, and Figs. 9A to 9C show polarities of data supplied to liquid crystal cells of neighboring vertical lines. Data in a dot inversion method (FIG. 12) or a line inversion method (FIG. 13) in which the polarities of the data supplied to the liquid crystal cells of neighboring horizontal lines are opposite to each other are opposite to each other. It shows the operation of output buffer step by step. In FIG. 8A-9C, a thick line shows the path through which an electric current flows.

The operation of the data output buffer according to the present invention will be described based on the column inversion method or the frame inversion method.

The operation process of the data output buffer according to the present invention includes a first section for rapidly charging and discharging data lines with a high current driving capability during a panel driving period, a second section for offset detection during a steady state period, and offset compensation for It includes a third section.

In the first section, as shown in FIG. 8A, the second and third switches S2 and S3 are closed and the first, fourth and fifth switches S1, S4 and S5 are opened to move the capacitor C to the buffer input terminal and the third node. (n3) is connected in series to the gate terminals of the MOS FETs (nMOS2, pMOS2) of the output unit 2 by adding the voltage (α) stored in the capacitor (C) during the previous second period to the buffer input terminal voltage. Supply. At this time, the drain current of the MOS FETs (nMOS2, pMOS2) of the output terminal is approximately as shown in Equation 1 below.

Where W is channel width, L is channel length, Vgs is gate-source voltage, and Vth is threshold voltage of MOS FET. Also, μ _norp is the mobility of the nMOS or pMOS FET, and C _ox is the capacitance of the MOS FET.

As can be seen from Equation 1, since the currents of the MOS FETs nMOS2 and pMOS2 of the output unit 2 are proportional to the square of the voltage applied to the gate terminal, the conventional data output buffer to which only the voltage at the buffer input terminal is applied ( Compared to FIG. 4A, data lines of the liquid crystal display panel may be charged and discharged quickly. In addition, the output unit 2 does not need to consider the effect on channel length modulation. This is because the nMOS and pMOS TFTs of the output unit 2 are turned off as shown in FIG. 8B after fast charging using the capacitor voltage as shown in FIG. 8A. Therefore, the output section 2 can minimize the channel length of the nMOS and pMOS TFTs in the process to increase the current. On the other hand, assuming the same channel ratio, if the channel length is increased, the channel width must be increased by that much, but if the channel length is minimum, the current driving capability is the same because the channel width can be reduced even if the channel width is small. Therefore, since the size of nMOS and pMOS of the output unit 2 can be reduced, the chip size of the data buffer can be reduced.

In the second section, the first, fourth, and fifth switches S1, S4, and S5 are closed as shown in FIG. 8B, while the second and third switches S2 and S3 are opened to open the voltage at the buffer input terminal and the voltage at the buffer output terminal. The difference voltage between is stored in the capacitor C to detect the offset. At this time, the MOS FETs nMOS2 and pMOS2 of the output terminal are turned off because the gate voltage is zero.

In the third section, as shown in FIG. 8C, the second and fifth switches S2 and S5 are closed, and the first, third and fourth switches S1, S3 and S4 are opened to move the capacitor C to the MOS of the input unit 1. The FETs (nMOS1, pMOS1) are connected in series to compensate for the voltage difference, that is, offset between the voltage at the buffer input and the buffer output.

In the dot inversion method or the line inversion method, the operation of the data output buffer according to the present invention is different from that of the column inversion method in the control of the switch during the first period, and the operations in the second and third periods are the same as the column inversion method. Do. In the first period of the dot inversion method, as shown in FIG. 9A, the first, third, and fourth switches S1, S3, and S4 are closed, and the second and fifth switches S2 and S5 are opened to be stored in the capacitor C. FIG. The buffer input terminal voltage is supplied to the gate terminals of the MOS FETs nMOS2 and pMOS2 of the output unit 2 without adding the voltage to the buffer input terminal voltage.

The reason why the operation of the data output buffer according to the present invention is different is as follows. In Equation 1, α is a voltage stored in the capacitor C to speed up the driving with a voltage added to the Vgs of the nMOS or pMOS TFT in the data buffer. However, in the dot inversion method (FIG. 11) or the line inversion (FIG. 12), since the voltage of alpha becomes opposite to the polarity of the input voltage, the gate voltage of the nMOS or pMOS TFT is reduced. Therefore, in the column inversion method (FIG. 10) or the frame inversion method (FIG. 11), as shown in FIGS. 8A and 14, the gate of the nMOS or pMOS TFT of the data buffer with a gate voltage as large as the voltage stored in the capacitor C. Although the voltage is increased, the dot inversion method (FIG. 12) or the line inversion method (FIG. 13) does not use the voltage of α as in FIGS. 9A and 15. 14 and 15, Vinput means a voltage at the buffer input terminal, and Vcap means a voltage stored in the capacitor C, respectively.

As described above, the data output buffer of the liquid crystal display according to the present invention is designed to reduce the offset and power consumption during the steady-state period by using an input stage in which the channel ratio of the MOS FETs is designed, and the channel ratio of the MOS FETs is relatively large and the panel is designed. Data lines of a liquid crystal display panel, for example, a high resolution liquid crystal display panel requiring high current driving capability, may be rapidly charged and discharged by using an output terminal in which a gate voltage is applied above a buffer input voltage during an operation period. As a result, the data output buffer of the liquid crystal display according to the present invention can drive the high resolution liquid crystal display panel stably while reducing the offset and power consumption in the data output buffer.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (11)

An input unit for compensating the offset by using a capacitor for storing a difference voltage between an input voltage and an output voltage; An output unit connected between the input unit and an output terminal to which the output voltage is output, and controlling the output voltage in response to a voltage added with the input voltage and the voltage of the capacitor, The input unit, A first switch connected between a first node connected to one electrode of the capacitor and an input terminal to which the input voltage is supplied; A second switch connected between the input terminal and a second node connected to the other electrode of the capacitor; A third switch connected between the first node and a third node connected to an input terminal of the output unit; A fourth switch connected between the second node and the third node; A first pull-up transistor having a drain terminal connected to a high potential voltage source, a source terminal connected to the third node, and a gate terminal connected to the first node; And a first pull-down transistor having a source terminal connected to the third node, a drain terminal connected to a base voltage source, and a gate terminal connected to the first node. delete The method of claim 1, The output unit, A fifth switch connected between the third node and the output terminal; A second pull-up transistor having a drain terminal connected to the high potential voltage source, a source terminal connected to the output terminal, and a gate terminal connected to the third node; And a second pull-down transistor having a source terminal connected to the output terminal, a drain terminal connected to the base voltage source, and a gate terminal connected to the third node. The method of claim 3, wherein During the first interval, The second and third switches are on, whereas the first, fourth and fifth switches are turned off so that the capacitor is connected in series between the input terminal and the third node. Data output buffer. The method of claim 4, wherein During a second section following the first section, The first, fourth and fifth switches are turned on while the second and third switches are turned off to store a difference voltage between the voltage at the input terminal and the voltage at the output terminal in the capacitor. Data output buffer of the device. 6. The method of claim 5, During the third section following the second section, The second and fifth switches are turned on while the first, third and fourth switches are turned off to connect the capacitor to a gate terminal of the first pull-up transistor and a gate terminal of the first pull-down transistor. The data output buffer of the liquid crystal display device. The method of claim 3, wherein The transistors included in the output unit have a larger channel ratio than the transistors included in the input unit. The method of claim 7, wherein The transistors included in the output unit have a smaller channel length than the transistors included in the input unit. The method of claim 3, wherein During the first interval, And closing the first, third and fourth switches and opening the second and fifth switches to connect the input terminal to the third node. The method of claim 9, During a second section following the first section, The first, fourth and fifth switches are turned on while the second and third switches are turned off to store a difference voltage between the voltage at the input terminal and the voltage at the output terminal in the capacitor. Data output buffer of the device. 11. The method of claim 10, During the third section following the second section, The second and fifth switches are turned on while the first, third and fourth switches are turned off to connect the capacitor to a gate terminal of the first pull-up transistor and a gate terminal of the first pull-down transistor. The data output buffer of the liquid crystal display device.

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