KR101165468B1 - Liquid crystal display device and method for driving the same - Google Patents

Abstract

Disclosed are a liquid crystal display device and a driving method thereof capable of removing gamma distortion of an upper gray level among total expressible grays.

The liquid crystal display according to the present invention includes a frame rate control signal generator for generating a frame rate control signal using the least d bits of n bits of data and the n bits of data according to the frame rate control signal. ) Includes a data driver that converts data in bits to analog voltages.

Frame rate, DAC, data

Description

Liquid crystal display device and method for driving the same

1 is a diagram for explaining frame rate control when n is 8 and d is 2. FIG.

FIG. 2 is a graph showing the relationship of transmittance to grayscale when the frame rate control of FIG. 1 is applied. FIG.

3 is a view showing a liquid crystal display device according to the present invention.

4 illustrates the data driver of FIG. 3 in detail.

5 is a view illustrating a change in data in the liquid crystal display of FIG. 3.

FIG. 6 illustrates the C-DAC of FIG. 4 in detail. FIG.

7 illustrates frame rate control of a liquid crystal display according to the present invention;

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

102: liquid crystal panel 104: gate driver

106: data driver 107: shift register

108: timing controller 109: latch array

110: frame rate control signal generator 111: R-DAC

112: gamma voltage generator 113: C-DAC

114a to 114d: first to fourth switches 115: output buffer section

116a to 116c: first to third inverters

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of preventing gamma distortion of higher gray levels.

In recent years, as the weight and thickness of personal computers, televisions, and the like have been reduced, the weight and thickness of display devices have also been increasing. In order to satisfy such demands, flat panel displays such as liquid crystal displays instead of cathode ray tubes (CRTs) are required. Has been developed and put into practical use in various fields.

The flat panel display device receives n-bit RGB data from an external system. After the data format is converted in the timing controller of the flat panel display device, the analog gray voltage corresponding to the RGB data is selected by the driving driver, and the display operation is performed by applying the selected gray voltage to the panel.

In general, the number of bits of RGB data input to the timing controller in the system and the number of bits that can be processed by the driving driver are the same. Among flat-panel displays currently on the market, products with n = 8 bits are common in liquid crystal displays.

However, since the driving driver capable of processing the 8-bit RGB data is expensive, if the liquid crystal display device can be designed as a driving driver having a lower bit processing capability, the unit cost of the product may be much lowered.

According to this technical need, the proposed method is frame rate control (FRC).

The frame rate control is a method of reconstructing RGB data frame by frame so that display is possible using only (n-d) bits, which are the number of bits that can be processed by the driving driver, among the n-bit RGB data.

개의 프레임 동안, 각 프레임에서 RGB 데이터의 하위 d 비트를 이용하여 RGB 데이터의 (n-d)비트가 나타내는 계조값 'X'와 상기 X의 상위 계조인 X+1의 프레임별 발생 빈도가 조정되도록 프레임 데이터를 변환시킨다. Here, d is an integer and means the lower predetermined number of bits of the input RGB data. Continuous

Frame data such that the frequency of occurrence of each frame of the gray level value 'X' indicated by the (nd) bit of the RGB data and the frequency of occurrence of X + 1, which is the upper gray level of the X, are adjusted using the lower d bits of the RGB data in each frame. To convert

개의 계조를 추가로 표시할 수 있으며, 이것은 (n-d) 비트의 R, G, B 데이터에 d 비트를 추가하여 n 비트 RGB 데이터에 의해 표시가 이루어지는 것과 동일한 효과를 얻는다. Even in a predetermined pixel unit of a frame, for example, 4 * 2 pixel units, the frequency of occurrence of each of the two grayscales X and X + 1 is arranged to be spatially adjusted, so that n-bit RGB when the temporal spatial screen display is averaged It can be recognized as if the display is made by the data. That is, between gradation X and X + 1

Number of gray scales can be additionally displayed, which adds d bits to (nd) bits of R, G, and B data to obtain the same effect as that displayed by n bits of RGB data.

FIG. 1 is a diagram for explaining frame rate control when n is 4 and d is 2. FIG.

As shown in Fig. 1, the four states of the lower two bits represent four gradations between two gradations X and X + 1, respectively, 00 is X, 01 is X + 1/4, and 10 is X + 1 /. 2 and 11 represent X + 3/4 gradations, respectively. The frame rate control method implements the input four bits by sequentially displaying the input four bits by two bits for four frames.

For example, if four bits of data of 0000 are input, two bits of data of 00 are output during the first to fourth frames. When four bits of data 0111 are input, data 01 is output in the first frame, and two bits data 10 are output in the second to fourth frames.

The input 4-bit data of 0111 represents the decimal number 7. 01 output from the first frame represents a decimal number 1, and 10 output from the 2 to 4 frames represents a decimal number 2. As a result, the input decimal number 7 may be expressed as the sum of the decimal numbers output in the first to fourth frames.

When four bits of data of 1100 are input, two bits of 11 of 11 are outputted in the first to fourth frames. 11 represents decimal 3 and 1100 represents decimal 12. That is, the input decimal number 12 may be expressed as the sum of the decimal numbers output in the first to fourth frames.

When 4-bit data of 1101 is input, 2-bit data of 11 is output in the first to fourth frames. 1101 represents decimal 13 and 11 represents decimal 3. The input decimal number 13 is represented by 12, which is the sum of the decimal numbers output in the first to fourth frames.

In addition, even if 4-bit data of 1110 and 1111 are input, 2-bit data of 11 is output in the first to fourth frames. The 1110 represents a decimal number 14 and the 1111 represents a decimal number 15. The input decimal numbers 14 and 15 are represented by 12, which is a sum output from the first to fourth frames.

As a result, there is a limit in representing 4 bits input during 4 frames by using the state of the lower 2 bits of the input data.

FIG. 2 is a graph showing the relationship of transmittance to grayscale when the frame rate control of FIG. 1 is applied.

개이다. 그런데 상위 6비트를 이용하여 프레임 레이트 제어를 하므로, 상위 계조에서는 RGB 데이터의 상위 6비트가 111111이 된다. As shown in FIG. 2, there is a distortion of gamma in higher grayscales, thereby reducing the number of displayable colors. In more detail, since the R, G, and B data are 8 bits, the total number of gray levels that can be represented is

Dog. However, since frame rate control is performed using the upper six bits, the upper six bits of the RGB data become 111111 in the upper gray level.

In the frame rate control, the RGB data is expressed as being expanded by adjusting the frequency of occurrence of an arbitrary gradation and its higher gradation. However, since there is no upper gradation of 111111, the frame rate control cannot be applied unavoidably. There is no choice but to pre-set the same gradation.

As a result, gamma distortion occurs at higher gray levels, and image quality is degraded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of improving image quality by preventing gamma distortion of upper gray levels among expressable gray levels.

The liquid crystal display according to the present invention for achieving the above object is a frame rate control signal generation unit for generating a frame rate control signal using the least d-bit data of the n-bit data and the n according to the frame rate control signal It includes a data driver for converting the (nd) bit of the data of the bit into an analog voltage.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including generating a frame rate control signal using the least d-bit data among n bits of data, and generating the n-bit value according to the frame rate control signal. Converting (nd) bits of data into analog voltages.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

3 is a view showing a liquid crystal display according to the present invention.

As shown in FIG. 3, the liquid crystal display according to the present invention includes a liquid crystal panel 102 in which a plurality of gate lines GL0 to GLn and data lines DL1 to DLm, which define a pixel region, are arranged. A gate controller 104 for driving GL0 to GLn, a data driver 106 for driving the data lines DL1 to DLm, and a timing controller for controlling the gate driver 104 and data driver 106 108, a gamma voltage generator 112 for generating a gamma voltage, and a frame rate control signal generator for generating a frame rate control signal using the lower two bits of the RGB data supplied from the timing controller 108. 110.

In the liquid crystal panel 102, a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged in an intersection, and a thin film transistor TFT which is a switching element is formed at an intersection thereof. When the thin film transistor TFT is turned on, a data voltage is supplied to a pixel electrode (not shown) electrically connected to the thin film transistor TFT through the data lines DL1 to DLm. .

The liquid crystal panel 102 is composed of two glass substrates (not shown) and liquid crystal injected between the glass substrates.

The gate driver 104 supplies a scan signal, that is, a gate high voltage VGH, to the gate lines GL0 to GLn according to the gate control signal generated by the timing controller 108 to determine the thin film transistor TFT. Control turn-on / off.

The data driver 106 supplies a data voltage to the data lines DL1 to DLm according to a data control signal generated from the timing controller 108. Detailed description of the data driver 106 will be described later.

The timing controller 108 controls the gate driver 104 and the data using the vertical / horizontal synchronization signal (Vsync / Hsync) and data enable (DE) signals supplied from a system (not shown). A data control signal for controlling the driver 106 is generated.

In addition, the timing controller 108 receives 8-bit RGB data from the system and arranges the RGB data one line at a time and supplies the RGB data to the data driver 106.

The frame rate control signal generation unit 110 generates a frame rate control signal using the least significant 2 bit data among the RGB data supplied from the timing controller 108 to the data driver 106 to generate the data driver 106. To supply.

The gamma voltage generator 112 generates a predetermined gamma voltage using a power supply voltage Vdd supplied from a power supply unit (not shown) and supplies the gamma voltage to the data driver 106.

4 is a diagram illustrating in detail the data driver of FIG. 3.

As shown in FIG. 4, the data driver 106 includes a shift register 107 for supplying a sequential sampling signal and an upper six bits of RGB data supplied from the timing controller 108 in response to the sampling signal. The latch array 109 sequentially latches and outputs the same, and the upper 4 bits of the 6-bit data supplied from the latch array 109 are analogized using the gamma voltage generated from the gamma voltage generator 112. An analog voltage value generated by the R-DAC 111 according to the R-DAC 111 converting the voltage value into a voltage value and the lower 2 bits of the 6 bits according to the frame rate control signal generated from the frame rate control signal generator; The C-DAC 113 converts an analog voltage value using the C-DAC 113, and an output buffer 115 for buffering and outputting the analog voltage supplied from the C-DAC 113.

The RGB data supplied to the data driver 106 will be described in detail with reference to FIGS. 3 and 4 as follows.

The timing controller 108 supplies the upper 6 bits of the 8-bit RGB data to the data driver 106 and the remaining lower 2 bits to the frame rate control signal generator 110.

The upper six bits of data are supplied to the latch array 109 of the data driver 106. The upper four bits of the six bit data supplied to the latch array 109 are supplied to the R-DAC 111, and the lower two bits are supplied to the C-DAC 113.

Specifically, the upper 6 bits D0 to D5 of the 8 bit data D0 to D7 supplied from the timing controller 108 are supplied to the latch array 109 of the data driver 106 with reference to FIG. 5. The lower two bits D6 and D7 are supplied to the frame rate control signal generator 110.

The upper four bits D0 to D3 of the upper six bits D0 to D5 are supplied to the R-DAC 111, and the lower two bits D4 and D5 are supplied to the C-DAC 113.

As a result, the upper six bits of data D0 to D5 among the eight bits of data D0 to D7 supplied from the timing controller 108 are converted into analog voltages in the R-DAC 111 and the C-DAC 113. The lower two bits of data D6 and D7 are converted into a frame rate control signal by the frame rate control signal generator 110 and supplied to the C-DAC 113.

The frame rate control signal is supplied to the C-DAC 113 and affects two bits of data D4 and D5 supplied to the C-DAC 113. The frame rate control signal is generated by the frame rate control signal generator 110.

Table 1 below shows a frame rate control signal generated for each frame by converting the lower two-bit data D6 and D7 supplied to the frame rate control signal generator 110.

D6 D7 First frame 2nd frame Third frame 4th frame 0 0 0 0 0 0 0 One 0 0 0 One One 0 0 One 0 One One One 0 One One One

When two bits of data D6 and D7 are supplied to the frame rate control signal generation unit 110, the frame rate control signal generation unit 110 performs four frames on the input two bits of data D6 and D7. Generate 0 or 1 signal over.

For example, if data 00 is supplied to the frame rate control signal generator 110, the frame rate control signal generator 110 outputs a zero signal over first to fourth frames. The output 0 signal is supplied to the C-DAC 113.

In addition, when the data 01 is supplied to the frame rate control signal generator 110, the frame rate control signal generator 110 outputs 0 signal in the first to third frames and 1 signal in the fourth frame. The output signals are supplied to the C-DAC 113 every frame.

At this time, the frame rate control signal generator 110 outputs the signals added to the C-DAC 113 for each of the first to fourth frames and inputs the signal to the frame rate control signal generator 110. The two bit data D6 and D7 are the same.

When the data of 10 is supplied to the frame rate control signal generator 110, the frame rate control signal generator 110 outputs a zero signal in the first and third frames and a single signal in the second and fourth frames. do. The output signals are supplied to the C-DAC 113 every frame.

When data 11 is supplied to the frame rate control signal generator 110, the frame rate control signal generator 110 outputs 0 signal in the first frame and 1 signal in the second to fourth frames. The output signals are supplied to the C-DAC 113 every frame.

Meanwhile, the upper 4 bit data D0 to D3 supplied to the R-DAC 111 may include a gamma voltage generated by the gamma voltage generator 112 and a plurality of resistors located inside the R-DAC 111. Are converted to analog voltage using the " not shown "

Two voltages of the analog voltages converted by the R-DAC 111 are supplied to the C-DAC 113. The two voltages are supplied to the C-DAC 113 to become first and second reference voltages Vref-1 and Vref-2. The first reference voltage Vref-1 has a voltage value lower than the second reference voltage Vref-2.

As illustrated in FIG. 6, the C-DAC 113 may include first to fourth capacitors 114a to 114d and first to fourth capacitors corresponding to the first to fourth switches 114a to 114d ( C1 to C4 and first to third inverters 116a to 116c.

The first and second reference voltages Vref-1 and Vref-2 generated from the R-DAC 111 are supplied to the first to third switches 114a to 114c. In this case, the first data D4 is supplied to the first switch 114a among the lower two bits supplied from the latch array 109, and the second data D5 is supplied to the second switch 114b.

The capacity of the first capacitor C1 is equal to the capacity of the third capacitor C3, and the capacity of the fourth capacitor C4 is equal to twice the capacity of the second capacitor C2. The capacity of the second capacitor C2 is equal to twice the capacity of the first capacitor C1. As a result, the capacity of the fourth capacitor C4 is equal to four times the capacity of the first capacitor C1.

This can be expressed as follows.

,

,

When the C-DAC 113 is reset, the first switch 114a is connected to a second reference voltage Vref-2, and the second and third switches 114b and 114c are connected to a first reference voltage. The fourth switch 114d is also connected to the second reference voltage Vref-2.

Meanwhile, when two bits of data D4 and D5 are supplied to the C-DAC 113, the first data D4 is supplied to the first switch 114a, and the second data D5 is supplied to the C-DAC 113. It is supplied to the second switch 114b. The two bits of data have values of {D4, D5} = 00, 01, 10, and 11, respectively.

When the first data D4 is 0, the first data D4 is supplied to the first switch 114a, and the first switch 114a supplies the first reference voltage Vref-1. Output When the first data D4 is 1, the first data D4 is supplied to the first switch 114a, and the first switch 114a supplies the second reference voltage Vref-2. Output

When the second data D5 is 0, the second data D5 is supplied to the second switch 114b, and the second switch 114b supplies the first reference voltage Vref-1. Output When the second data D5 is 1, the second data D5 is supplied to the second switch 114b, and the second switch 114b supplies the second reference voltage Vref-2. Output

The first or second reference voltages Vref-1 and Vref-2 output through the first and second switches 114a and 114b are first and second through the first and second capacitors C1 and C2. It is supplied to two nodes nd1 and nd2.

The third switch 114c outputs the first or second reference voltages Vref-1 and Vref-2 according to the frame rate control signal supplied from the frame rate control signal generator 110.

When a signal of 1 is supplied from the frame rate control signal generator 110 to the third switch 114c, the third switch 114c outputs a second reference voltage Vref-2. In addition, when a control signal of 0 is supplied from the frame rate control signal generator 110 to the third switch 114c, the third switch 114c outputs a first reference voltage Vref-1.

When the 2-bit data D4 and D5 supplied to the C-DAC 113 is 00, the first data D4 is supplied to the first switch 114a, and the second data D5 is It is supplied to the second switch 114b. As a result, the first switch 114a outputs a first reference voltage Vref, and the second switch 114b also outputs a first reference voltage Vref-1. The first reference voltage Vref-1 output from the first switch 114a is supplied to the first node nd1 through the first capacitor C1.

In addition, the first reference voltage Vref-1 output from the second switch 114b is supplied to the second node nd2 through the second capacitor C2.

At the same time, when a zero signal of the frame rate control signal is supplied to the third switch 114c, the third switch 11c outputs a first reference voltage Vref-1. The output first reference voltage Vref-1 is supplied to the third node nd3 through the third capacitor C3.

In addition, when the C-DAC 113 is in operation, Vout output from the first to third inverters 116a to 116c is supplied to the fourth switch 114c. That is, when the C-DAC 113 is in operation, the fourth switch 114c is connected to the Vout voltage.

The Vout voltage is supplied to the second node nd2 through the fourth capacitor C4. The voltage input to the first inverter 116a may be known by calculating voltages supplied to the first to third nodes nd1 to nd3.

The voltage input to the input terminal of the first inverter 116a becomes the Vout voltage of the C-DAC 113. The Vout voltage means a value obtained by converting two bits of data D4 and D5 supplied to the C-DAC 113 into an analog voltage.

In other words, when two bits of data D4 and D5 of 00 are supplied to the C-DAC 113 and a control signal of 0 is supplied from the frame rate control signal generation unit 110 of FIG. The DAC 113 outputs the first reference voltage Vref-1.

For example, the first reference voltage Vref-1 refers to a minimum value among values obtained by the R-DAC 111 converting 4-bit data D0 to D3 into analog voltages. The second reference voltage Vref-2 refers to the maximum value of the R-DAC 111 converting 4-bit data D0 to D3 into an analog voltage.

In addition, when the 2-bit data D4 and D5 of 01 are supplied to the C-DAC 113 and a control signal of 0 is supplied from the frame rate control signal generator 110, the C-DAC 113 is supplied. Outputs a first reference voltage Vref-1 + (second reference voltage Vref-2-first reference voltage Vref-1) / 4. This can be represented by a simple equation: Vout = (Vref-1) + ((Vref-2)-(Vref-1)) / 4.

When two bits of data D4 and D5 of 10 are supplied to the C-DAC 113 and a control signal of 0 is supplied from the frame rate control signal generation unit 110, the C-DAC 113 is configured to generate a second value. The first reference voltage Vref-1 + (second reference voltage Vref-2-first reference voltage Vref-1) / 2 is outputted. That is, it is represented by Vout = (Vref-1) + ((Vref-2)-(Vref-1)) / 2.

When the 2-bit data D4 and D5 of 11 are supplied to the C-DAC 113, and a control signal of 0 is supplied from the frame rate control signal generator 110, the C-DAC 113 The first reference voltage Vref-1 + (second reference voltage Vref-2-first reference voltage Vref-1) / * 3/4 is outputted. That is, it is represented by Vout = (Vref-1) + ((Vref-2)-(Vref-1)) / 2.

On the other hand, when the control signal of 1 is supplied from the frame rate control signal generator 110, the C-DAC 113 outputs the following Vout voltage.

When the 2-bit data D4 and D5 of 00 are supplied to the C-DAC 113 and a control signal of 1 is supplied from the frame rate control signal generation unit 110, the C-DAC 113 is configured to be first. The reference voltage Vref-1 + (second reference voltage Vref-2-first reference voltage Vref-1) / 4 is outputted. This can be represented by a simple equation: Vout = (Vref-1) + ((Vref-2)-(Vref-1)) / 4.

In this case, the first reference voltage Vref-1 refers to, for example, a minimum value among values obtained by the R-DAC 111 converting 4-bit data D0 to D3 into an analog voltage. Vref-2) refers to the maximum value of the R-DAC 11 converting 4-bit data D0 to D3 into an analog voltage.

In addition, when the 2-bit data D4 and D5 of 01 are supplied to the C-DAC 113 and a control signal of 1 is supplied from the frame rate control signal generator 110, the C-DAC 113 is supplied. Outputs a first reference voltage Vref-1 + (second reference voltage Vref-2-first reference voltage Vref-1) / 2. That is, it is represented by Vout = (Vref-1) + ((Vref-2)-(Vref-1)) / 2.

When two bits of data D4 and D5 of 10 are supplied to the C-DAC 113 and a control signal of 1 is supplied from the frame rate control signal generation unit 110, the C-DAC 113 is configured to have a first value. The first reference voltage Vref-1 + (second reference voltage Vref-2-first reference voltage Vref-1) / * 3/4 is outputted. That is, it is represented by Vout = (Vref-1) + ((Vref-2)-(Vref-1)) / 2.

When the 2-bit data D4 and D5 of 11 are supplied to the C-DAC 113, and a control signal of 0 is supplied from the frame rate control signal generator 110, the C-DAC 113 The second reference voltage Vref-2 is output.

The C-DAC 113 receives the first and second reference voltages Vref-1 and Vref-2 from the R-DAC 111, and also receives a frame from the frame rate control signal generator 110. The control signal is supplied to output Vout, which is an output voltage.

In this case, Vout of the C-DAC 113 is determined by the capacity of the first to fourth capacitors C1 to C4. As such, the Vout voltage output from the C-DAC 113 is supplied to the output buffer unit 115.

The output buffer 115 arranges the Vout voltage supplied from the C-DAC 113 and supplies the aligned Vout voltage to the data lines DL1 to DLm.

The Vout voltage supplied to the data lines DL1 to DLm represents a predetermined gray level as the data voltage.

7 is a diagram illustrating frame rate control of a liquid crystal display according to the present invention.

As shown in FIG. 7, the gray level of the LCD including the data driver capable of receiving 2-bit data by receiving 4-bit data from the system is shown as an example.

When four bits of data are input from the system, the upper two bits of the four bits of data are supplied to the C-DAC (113 in FIG. 4), and the lower two bits of the four bits of data are the frame rate control signal. It is supplied to the generating unit (110 in FIG. 4).

The frame rate control signal generator 110 generates 0 or 1 signals over the first two bits as shown in Table 1 in the lower two bits. The frame rate control signal generated by the frame rate control signal generator 110 is supplied to the C-DAC 113.

The C-DAC 113 generates new two bits of data over the first to fourth frames using the frame rate control signal and the upper two bits. The sum of two bits of data generated over the first to fourth frames is the same as the four bits of data supplied from the system.

For example, when 4-bit data of 0000 is input from the system, the upper two bits of 00 are supplied to the C-DAC 113, and the lower two bits of 00 are the frame rate control signal generator 110. Is supplied. The frame rate control signal generator 110 generates a zero signal over the first to fourth frames and supplies the zero signal to the C-DAC 113.

The C-DAC 113 outputs a voltage corresponding to 00 data over first to fourth frames using the 0 signal and the upper 2 bits 00.

When 4-bit data of 1111 is input from the system, the upper 2 bits 11 are supplied to the C-DAC 113, and the lower 2 bits 11 are supplied to the frame rate control signal generator 110. . The frame rate control signal generator 110 generates a zero signal in the first frame and a single signal in the second and fourth frames. The frame rate control signal generated by the frame rate control signal generator 110 is supplied to the C-DAC 113.

The C-DAC 113 outputs a voltage corresponding to data of 11 in the first frame. In addition, the C-DAC 113 outputs a voltage corresponding to 100 data in the second to fourth frames. The data 11 output from the first frame represents the decimal 3, and the data 100 output from the second to fourth frames represents the decimal 4. The sum of the decimal numbers of the data output from the first to fourth frames has the same value as the decimal number of the data 1111 supplied from the system.

When 4-bit data 1101 is input from the system, the C-DAC 113 outputs a voltage corresponding to data 11 of the first to third frames. In addition, the C-DAC 113 outputs a voltage corresponding to 100 data in the fourth frame. The data 11 output from the first to third frames represents the decimal 3, and the data 100 output from the fourth frame represents the decimal 4.

The sum of the decimal numbers of the data output from the first to fourth frames has the same value as the decimal number of the data 1101 supplied from the system.

When 4-bit data of 1110 is input from the system, the C-DAC 113 outputs a voltage corresponding to 11 of data in the first and third frames. In addition, the C-DAC 113 outputs a voltage corresponding to 100 data in the second and fourth frames. The data 11 that is output in the first and third frames represents the decimal number 3, and the data 100 that is output in the second and fourth frames represents the decimal number 4.

The sum of the decimal numbers of the data output from the first to fourth frames has the same value as the decimal number of the data 1110 supplied from the system.

In the conventional liquid crystal display, when the 4-bit data is input from the system, the upper predetermined gray levels are displayed the same. For example, when four bits of data 1101, 1110, and 1111 are supplied from the system, gray level voltages corresponding to two bits of data 11 are displayed over the first to fourth frames. Although the 4-bit data inputted from the system were different, the gray voltages displayed on the liquid crystal panel were all the same.

As a result, the upper predetermined gray scales are displayed the same, resulting in deterioration of image quality such as gamma distortion.

In order to overcome this problem, the liquid crystal display according to the present invention receives a frame rate control signal generator and a frame rate control signal for generating a frame rate control signal for every frame using the least two bits of data input from the system. A C-DAC converting data input from the system may be provided to overcome the deterioration of image quality caused by the conventional liquid crystal display and to improve image quality.

As described above, the liquid crystal display according to the present invention expresses 8-bit data as 6-bit data over the first to fourth frames, and overcomes the gamma distortion generated in higher gray levels. By providing a frame rate control signal generation unit for generating a frame rate control signal by using the least significant two bits of the data, it is possible to overcome the problems caused in the conventional liquid crystal display and to improve image quality.

Claims (11)

a frame rate control signal generation unit configured to generate a frame rate control signal using the least significant d bits of the n bits of data; And A data driver for converting (n-d) bits of the n bits of data into an analog voltage according to the frame rate control signal, The data driver generates an R-DAC for generating first and second reference voltages using upper e data among the (nd) bits and lower f data among the frame rate control signal and the (nd) bits. And a C-DAC generating an analog voltage reflecting the first and second reference voltages. delete The method of claim 1, The C-DAC,  First and second switches for selectively outputting the first or second reference voltage according to the lower f data;  A third switch for selectively outputting the first or second reference voltage according to the frame rate control signal;  A fourth switch for selecting the second reference voltage according to a reset case and an operating case; And And first to fourth capacitors corresponding to the first to fourth switches. The method of claim 3, And the first and second reference voltages have different voltage levels. The method of claim 3, The capacity of the first capacitor is equal to the capacity of the third capacitor, the capacity of the second capacitor is double the capacity of the first capacitor, and the capacity of the fourth capacitor is double the capacity of the second capacitor. Liquid crystal display device characterized in that. The method of claim 3, The first and second switches are connected to a first reference voltage when the 1-bit data of 0 is supplied, and output the first reference voltage. When the 1-bit data is 1, the first and second switches are connected to the second reference voltage. And output the second reference voltage. The method of claim 3, When the frame rate control signal of 0 is supplied, the third switch is connected to a first reference voltage to output the first reference voltage. When the frame rate control signal of 1 is supplied, the third switch is connected to a second reference voltage to supply the first reference voltage. 2. A liquid crystal display characterized by outputting a reference voltage. The method of claim 3, And the fourth switch is connected to a first reference voltage to output the first reference voltage when the fourth switch is reset, and outputs an output voltage of the C-DAC during driving. The method of claim 1, The frame rate control signal generator

And a frame rate control signal which is a 0 or 1 signal using the d bits for the number of frames. generating a frame rate control signal using the least significant d bits of the n bits of data; And Converting (n-d) bits of the n bits of data into an analog voltage according to the frame rate control signal, Converting (nd) bits of the n bits of data into an analog voltage includes generating first and second reference voltages using upper e data among the (nd) bits of data and controlling the frame rate. And generating an analog voltage reflecting the first and second reference voltages according to the lower f data among the signal and the (nd) bit data. The method of claim 10, The frame rate control signal is

A method of driving a liquid crystal display device, characterized in that is generated during four frames.

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