KR101165108B1 - Process for metallic contamination reduction in silicon wafers - Google Patents

Abstract

A process for removing selected contaminants from copper, nickel and combinations thereof from a silicon wafer having a surface and an interior, the method comprising: cooling a silicon wafer in a controlled atmosphere from an oxidation onset temperature or above and oxygen at the oxidation onset temperature Initiating the flow of the atmosphere to create an oxidizing environment around the silicon wafer surface, thereby forming an oxide layer on the silicon wafer surface and forming a strained layer at the interface between the oxide layer and the inside of the silicon wafer. Cooling the wafer is also controlled to allow atoms of contaminants to diffuse from the inside of the silicon wafer into the strained layer. Thereafter, the silicon wafer is cleaned to remove the oxide layer and the strained layer to remove the contaminants diffused into the strained layer.

Metal contaminants, copper, diffusion, strained layer, oxidizing atmosphere

Description

PROCESS FOR METALLIC CONTAMINATION REDUCTION IN SILICON WAFERS}

The present invention relates generally to the preparation of semiconductor material substrates, in particular to silicon wafers used in the manufacture of electronic devices. More specifically, the present invention relates to a process of annealing or annealing one or more silicon wafers to reduce the concentration of metal contaminants, such as copper, within or from the bulk of the wafer. In addition, the process of the present invention may be carried out in a manner that reduces the size or concentration of cohesive vacancy defects in the bulk and on the surface of one or more silicon wafers.

Silicon device performance is degraded by metallic contaminants. Transition metals including copper, iron and nickel can dissolve and diffuse during typical thermal cycles associated with integrated circuit fabrication conditions. During cooling from the temperatures associated with integrated circuit fabrication, copper and other metals may be deposited on the surface of the wafer, as well as regions, defect sites and interfaces doped with, for example, boron (eg, p-type wafer or region). Can be precipitated or concentrated. These precipitates are generally regarded as reaction products of metal contaminants and silicon. In the case of copper, the precipitates are considered to be copper silicide precipitates. Precipitates often create dislocations and other defects. Precipitates and dislocations and defects associated with them render the integrated circuit made from the wafer useless when present in the device fabrication area of the wafer. In addition, copper silicide precipitates form what are called haze defects because, when subjected to normal etching and bright light inspection, the precipitates cause defects that look like haze on the surface of the wafer. Due to this problem, integrated circuit manufacturers generally require that the concentration of copper on the surface of the silicon wafer be between 1 × ^{10 10} atoms / cm 2 and ¹ × ^{10 11} atoms / cm 2 as determined by standard methods in the art. In addition, this requirement will be reduced to values of 5x10 ⁹ atoms / cm 2, 1x10 ⁹ atoms / cm 2 or less since a large percentage of random device errors can be traced to copper silicide precipitates.

Single crystal silicon wafers are generally manufactured by a process starting with the growth of single crystal silicon ingots produced by the Czochralski method or the floating-zone method. Crystal ingots are typically sliced into wafers using a wire saw, and the wafers are planarized by lapping and chemically etched to remove mechanical damage and contamination. After etching, the wafers are polished to one or both sides. Although additional processing, such as thermal annealing, is applied to the wafers to reduce crystal originated particles (COP), the processing typically ends with modern cleaning methods. After this cleaning, the copper concentration on the surface of the polished wafers is typically less than ¹ × ^{10 10} atoms / cm 2, as determined by total reflection spectroscopy (TXRF) measurements. For example, C. Neumann et al Spectrochemica Acta , 10 (1991), pp. 1369-1377; And Spectrochemical Analysis by Ingle & Crouch, Prentice Hall, 1988. However, the surface copper concentrations of these wafers tend to increase over time, even at room temperature, until they reach saturation. Thus, wafers that meet the target specification for surface copper concentration immediately after cleaning may not meet this specification after 5 to 10 months.

To date, there have been three main approaches to address the problem of copper contamination of silicon wafers. The first approach involves reducing the amount of copper and other metals introduced into the silicon during the polishing operation. Specifically, the focus was primarily on identifying and eliminating these sources of contaminants. In addition to reducing the amount of metal in the polishing mixture, other methods, such as those disclosed by Prigge et al. (DE 3939661 A1), are substantially incorporated into the wafer during polishing by mixing the abrasive with certain reagents forming copper and coordination complexes. Limiting the amount of copper. This coordination composite serves to keep copper in a particular form that limits the ability of copper to enter silicon. Although modifying the polishing mixtures to reduce the degree of copper contamination in silicon wafers, it is typically not effective enough to eliminate the need for other copper abatement methods. In addition, the more stringent restrictions placed on the level of metallic contamination in silicon wafers by integrated circuit fabrication, make them rely on polishing mixture modifications, which are a much more expensive option for controlling metallic contamination in silicon wafers.

A second approach to dealing with metal contamination of polished silicon wafers is intrinsic gettering, which traps copper and other metals to prevent these metals from reaching the device region of the wafer. Intrinsic gettering techniques are used at locations that do not interfere with the functionality of integrated circuits manufactured from a wafer (ie, an area within the wafer below the device area, often referred to as a "bulk", "wafer bulk" or "bulk area"). This involves introducing defect sites into the silicon wafer. However, gettering techniques have not proven to be a fully acceptable solution for controlling metallic contaminants. For example, high diffusion coefficients of metals such as copper and nickel in silicon can cause these metals to escape from gettering sites and reach the device region. In addition, defects introduced as gettering sinks in silicon can lower the quality of silicon, for example by reducing minority carrier recombination life time.

A third approach to address the problem of metallic contamination of polished silicon wafers is to drive copper to a surface that can be removed from the bulk of the silicon wafer using one or more so-called "low temperature anneals". For example, US Pat. No. 6,100,167 to Falster et al. Generally describes cold annealing (eg, about 225 to about 300) a wafer for a relatively short period of time (eg, between about 5 minutes and about 1.5 hours). Increasing the rate at which copper diffuses to the surface of the wafer. After diffusion to the surface, copper is removed from the surface by performing a cleaning operation. One or more such low temperature annealing, including cleaning to remove copper, may be performed before the polished silicon wafer is heated to a temperature above 500 ° C. to avoid the formation of copper silicide precipitates. Although such low temperature annealing can be used to effectively remove copper from a single silicon wafer, it has not been implemented in conventional manufacturing processes because it significantly reduces throughput and significantly increases the cost of the wafer. For this reason, these low temperature anneals have been limited to laboratory and test applications.

In summary, the manufacture of silicon wafers includes many steps that are potential factors for the introduction of metallic contaminants such as wafer polishing. Given the shortcomings of the foregoing methods for obstructing or removing metallic contamination, a simple, low cost for removing metallic contaminants from polished silicon wafers, which can be included in conventional manufacturing processes without forming harmful precipitates And there is a continuing need for effective methods.

Thus, in short, the present invention relates to a process for removing contaminants selected from copper, nickel and combinations thereof from a silicon wafer having a silicon wafer surface and a silicon wafer interior. This process includes cooling the silicon wafer in an atmosphere controlled from the temperature at or above the oxidation start temperature. At the oxidation start temperature, a flow of atmosphere containing oxygen is initiated to create an oxidizing environment around the silicon wafer surface, resulting in an oxide layer on the silicon wafer surface and a strain layer at the interface between the oxide layer and the inside of the silicon wafer. ). Cooling of the silicon wafer is controlled such that atoms of contaminants diffuse from the inside of the silicon wafer into the strained layer. Thereafter, the wafer is cleaned to remove the oxide layer and the strained layer to remove the contaminants diffused into the strained layer.

The invention also relates to another process for removing contaminants selected from copper and nickel from a silicon wafer having a silicon wafer surface and a silicon wafer interior. This process exposes the silicon wafer surface to a cleaning environment comprising heating the silicon wafer to a temperature of at least about 1100 ° C. and a cleaning environment comprising one selected from the group comprising hydrogen, helium, neon, argon, krypton, xenon and mixtures thereof. Removing the silicon oxide from the silicon wafer surface to form a deoxidized silicon wafer. The deoxidized silicon wafer is exposed to an oxidizing environment to form an oxide layer on the silicon wafer surface, resulting in an oxidized silicon wafer having a strained layer at the interface between the oxide layer and the inside of the silicon wafer. The temperature of the oxidized silicon wafer is controlled to diffuse contaminants from inside the silicon wafer into the strained layer. Thereafter, the silicon wafer is cleaned to remove the contaminants diffused from the silicon wafer into the strained layer to form a cleaned silicon wafer.

The invention also relates to a process for removing selected contaminants from copper, nickel and combinations thereof from a plurality of silicon wafers having silicon wafer surfaces and silicon wafer interiors. This process includes cooling the silicon wafers from an oxidation initiation temperature of less than about 800 ° C. or above. At the oxidation initiation temperature, a flow of an atmosphere comprising oxygen is initiated to create an oxidizing environment around the silicon wafer surfaces to form oxide layers having a thickness of between about 5 and about 20 microns on the silicon wafer surfaces. Strain layers are formed at the interfaces between the layers and the silicon wafer interiors. Cooling of the wafers is controlled to diffuse atoms of contaminants from the silicon wafer interiors into the strained layers. The silicon wafers are then cleaned to remove oxide layers and strained layers, thereby removing the contaminants diffused into the strained layers.

The invention also relates to a process for removing contaminants selected from copper, nickel and combinations thereof from a silicon wafer having a silicon wafer surface and a silicon wafer interior. The process includes increasing the temperature of the silicon wafer to an annealing temperature of at least about 1100 ° C. while exposing the silicon wafer to a heat-cooling environment comprising argon. Silicon wafer by exposing the silicon wafer for a period of between about 30 minutes and about 90 minutes to an annealing environment selected from the group comprising hydrogen, helium, neon, argon, krypton, xenon and combinations thereof when the silicon wafer is at the annealing temperature Is annealed to remove silicon oxide from the silicon wafer surface and to facilitate the migration of silicon atoms to the exposed agglomeration void defects on the silicon wafer surface to reduce the size of the exposed agglomeration void defects. While exposing the silicon wafer to a heat-cooling environment, the temperature of the silicon wafer is reduced from the annealing temperature to an oxidation initiation temperature of about 800 ° C. or less. As the temperature of the wafer decreases from the onset of oxidation, the silicon wafer is exposed to an oxidizing environment containing oxygen at a concentration between about 10 and about 100 ppm, forming an oxide layer on the silicon wafer surface and forming the oxide layer and the silicon wafer. A strained layer is formed at the interface between the interiors. The temperature reduction of the silicon wafer is controlled to allow diffusion of atoms of contaminants from inside the silicon wafer into the strained layer. The silicon wafer is cleaned to remove contaminants that have diffused from the silicon wafer into the strained layer.

Other features and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawing (s).

1 shows the structure of a single crystal silicon wafer produced according to the present invention.

2 shows an oxygen precipitate profile of a wafer that can be prepared in accordance with the present invention.

The following discussion focuses on copper contamination in silicon, with copper being the most studied and typically the most problematic of metallic contaminants. However, the methods described for copper are also applicable to other metallic contaminants found in silicon (eg nickel, iron, aluminum, chromium, etc.).

Without being bound by any particular theory, it is believed that copper forms some kind of composite with boron and is included or "stored" in this form in boron-doped silicon wafers. In addition, these copper-boron complexes are considered to be unstable, even at room temperature. Thus, over time, copper may assume an interstitial position due to dissociation of these complexes. Copper is a fast diffuser in silicon; It is the fastest of all metals and is very fluid at room temperature. In addition, however, their solubility in silicon is very temperature dependent and very low at low temperatures, for example at room temperature. Thus, at low temperatures, interstitial copper diffuses quickly across the surface of the wafer. As such, the concentration of copper on the surface of the wafer tends to increase with time until a certain surface concentration limit (eg, saturation limit) is reached. In addition to being time dependent, the diffusion of copper to the surface is in part dependent upon the amount of copper provided to the wafer by the polishing process and / or other such as carbon and silicon carbide contained in furnace components and accessories. Depends on the amount of sources. In addition, the copper diffusivity depends in part on the concentration of boron in the wafer. Specifically, as the boron concentration of the wafer increases, the "storage" capacity for copper increases, thus increasing the potential for the increase in copper concentration on the wafer surface over time.

From the wafer bulk, the relative amount of copper contamination in the bulk of the silicon wafer can be evaluated by performing a test that accelerates the diffusion of copper to the surface of the wafer where copper can be removed and measured. One such method is a method in which the wafer bulk into a modified silicon region extending inwards a few nanometers distance (eg, less than about 100 nm) from the polished surface, a silicon oxide layer thereon, and / or the polished surface. Low temperature heat treatment of the wafer at a temperature of at least about 75 ° C. for at least about 30 seconds to outdiffuse copper. Without being bound by a particular theory, lattice differences often lead to deformation regions or layers at or near the surface (ie, at the interface where silicon turns to silicon oxides such as SiO and SiO ₂ , a larger volume of silicon oxide This force is forced into the space previously occupied by the smaller silicon state, causing compression and deformation. Further, some portion of the strain may be the result of the difference between the expansion coefficients of silicon and the silicon oxide thereon, causing thermally induced stress and strain when the temperature of the wafer changes. Preferably, the low temperature heat treatment includes heat treating the wafer at a temperature of about 250 ° C. for a period of about 4 hours. Thereafter, a test is performed to measure the amount of outdiffused copper on the heat treated wafer. One example of such a test is acid drop / inductively coupled plasma-mass spectroscopy (ICP-MS), which involves contacting the surface of a wafer with a chemical solution (e.g. a hydrofluoric acid based mixture) to extract copper. It involves dissolving oxides and copper from the surface, collecting a solution comprising dissolved oxides and copper, and measuring the amount of copper in the solution using ICP-MS. The measured amount of copper is converted to copper concentration expressed in number of atoms per square centimeter of the wafer surface and is generally referred to as "bulk concentration of copper", "bulk copper concentration", or "bulk copper". When measured according to the previous method, many integrated circuit fabrications require that the bulk copper concentration be less than 5 × ^{10 10} atoms / cm 2 and preferably less than ¹ × ^{10 10} atoms / cm 2.

Although polished and cleaned wafers may have a surface concentration of acceptable copper that is within integrated circuit manufacturer specifications (i.e., the concentration of copper on the surface prior to performing bulk concentration measurements), or exceed about 5x10 ¹⁰ atoms / cm 2 and it may have a bulk density of copper of greater than about 1x10 ¹¹ atoms / ㎠, or greater than about 1.5x10 ¹¹ atoms / ㎠. For example, P-type wafers that have been polished and annealed at high temperatures such as 1200 ° C. to reduce or eliminate crystallographic defects and then analyzed for bulk copper contents typically have a bulk copper concentration of about 2 × 10 ¹¹ atoms / cm 2. Have them.

In general, the process of the present invention is directed to removing metallic contaminants from the bulk of one or more silicon wafers. More specifically, the present invention relates to a process for treating one or more wafers comprising metallic contaminants at relatively high temperatures (eg, at least about 500 ° C., 600 ° C., 700 ° C., 800 ° C., 900 ° C., 1000 ° C., 1100 ° C., or 1200 ° C., or higher), followed by cooling the wafers in such a way that metallic contaminants, in particular copper, can diffuse into or near the strained surface of the wafer. will be. Thereafter, metallic contaminants diffused from the wafers can be removed by cleaning the wafers according to any suitable cleaning method, such as conventional SC1, SC2 cleaning operations. Without wishing to be bound by any theory, applying a process prior to boron doped silicon single crystal wafers increases the rate at which the copper-boron complexes dissociate, and when diffused copper is removed from the wafer's bulk, It is believed to increase the rate at which copper diffuses to the strain region near or at the surface where it preferably stays. By increasing the dissociation and diffusion rates, a significant portion of the previous copper in the bulk of the wafer can be removed. In fact, after removing the diffused copper, the amount of copper in the wafer is such that the bulk concentration of copper in the wafer is reduced to a level below about 1 × ^{10 10} atoms / cm 2. Preferably, the bulk concentration of copper is reduced to a level below about 5x10 ⁹ atoms / cm 2. More preferably, the bulk concentration of copper is reduced to levels below about 1 × ^{10 9} atoms / cm 2.

The process of the present invention is carried out to reduce or eliminate cohesive void defects, such as defects represented by octahedral voids and defects commonly referred to as crystal originated pits / particles and / or hydrogen and / or Or because it can be included in the cooling portion of conventional heat treatments such as argon annealing (or also referred to as “hydrogen-argon annealing”), a reduction in bulk copper concentration is achieved with little or no time to the manufacturing process. There is an advantage in that. Indeed, the method of the invention is particularly suitable for inclusion during the cooling portion of the hydrogen-argon annealing, and as such, the following description of the invention mainly relates to this embodiment. Another advantage of the present invention is that since it uses very little raw material (eg oxygen) which is relatively inexpensive, it can be carried out at substantially no additional cost. In addition, the present invention can remove copper without modification of conventional post-anneal cleaning processes.

Characteristics of Silicon Wafers

Preferred starting materials for the present invention are single crystal silicon wafers, preferably sliced from single crystal ingots grown according to any of the conventional variations of the Czochralski crystal growth method. Wafers prepared using the Czochralski method are typically from about 5x10 ¹⁷ atoms / cm 3 to about 9x10 ¹⁷ atoms / cm 3 (in other words, from about 10 ppm to about 18 ppm (ie, from about 10 to about 1,000,000 total atoms in the wafer). About 18 oxygen atoms)) (ASTM standard F-121-80), more typically about 6x10 ¹⁷ atoms / cm 3 to about 8.5x10 ¹⁷ atoms / cm 3 (ie about 12 ppm to about 17 ppm). If an oxygen free wafer is desired, the starting material is preferably sliced from a single crystal ingot grown according to any of the conventional variations of the floating region crystal growth method. Growth of silicon ingots, standard silicon slicing, lapping, etching and polishing techniques are well known in the art, see, for example, F. Shimura, Semiconductor Silicon Crystal Technology (Academic Press, 1989); And Silicon Chemical Etching, (J. Grabmaier, ed., Springer-Verlag, New York, 1982). The method of the present invention is preferably performed on one or more silicon wafers at any point in the manufacturing process prior to the final cleaning operation after a final polishing operation that provides specular light on at least the front side of the silicon wafer.

The wafer typically includes one or more dopants to provide the wafer with various desired properties. Specifically, the wafer is typically a P-type wafer (ie, a wafer doped mainly with boron, doped with elements from Group 3 of the periodic table such as boron, aluminum, gallium and indium). Preferably, the wafer is a P-type wafer having a resistivity of about 100 GPa to about 0.01 GPa. For silicon doped with boron, the foregoing resistivity values correspond to dopant concentrations of about 1.3 × ^{10 14} atoms / cm 3 to about 8.5 × 10 ¹⁸ atoms / cm 3, respectively. Although the process of the present invention is useful for removing copper from P-type wafers (generally called P-silicon) with relatively low boron concentrations, for example, with resistivities between about 20 kV and about 1 kV. Copper removal is particularly useful, for example, for wafers with higher boron concentrations having specific resistivities between about 0.03 Ωcm and about 0.01 Ωcm (generally called "P + silicon").

Preferably, the wafer also contains nitrogen. The presence of nitrogen offers several advantages for silicon wafers. Specifically, it is known in the art that nitrogen strengthens silicon wafers. In addition, the presence of nitrogen tends to slow the diffusion of the void defects in the silicon, which can reduce the concentration and / or size of the cavities in the wafer, with smaller cavities more easily when the wafer is placed in proper heat treatment. It tends to dissolve. Slowing the air diffusion also tends to stabilize the density or concentration of bulk micro defects (also called "BMD" or "BMDs") or oxygen precipitates in the wafer. Methods of controlling the nitrogen concentration in the growing silicon ingot are well known in the art. Preferably, any known method is used to control the nitrogen concentration in the growing ingot so that the wafer sliced therefrom is between about 1 × ^{10 12} atoms / cm 3 (about 0.00002 ppm) and 1 × ^{10 15} atoms / cm 3 (about 0.02 ppm) Have a concentration of nitrogen. More preferably, the nitrogen concentration is between about 1 × ^{10 12} atoms / cm 3 and about 1 × ^{10 13} atoms / cm 3 (0.0002 ppma).

Referring to FIG. 1, a single crystal silicon wafer has a central axis 8, a front surface 3 and a back surface 5 generally perpendicular to the central axis 8, and an imaginary center plane 7 equidistant between the front and back surfaces. ), A cylindrical edge 2 joining the front face 3 and the rear face 5, and a diameter 9 extending from the central axis to the columnar edge 2. Note that because silicon wafers typically have a certain total thickness change (TTV), warp, and bend, the midpoint between all points on the front and all points on the back may not be exactly in plane. However, as a practical matter, it can be said that when the approximate approximation, the center points fall within the virtual center plane because the overall thickness variation, warpage, and bending are typically minor.

To improve the surface properties of silicon wafers Annealing

Polished wafers typically have unwanted defects (eg, COPs) on the surface, formed when the ingot has cooled after solidification, which are detectable by laser scattering inspection tools. Such defects arise, in part, due to the excessive presence of intrinsic point defects known as public and self-interstitials (i.e. concentration above the high solubility limit). Silicon crystals grown from the melt are typically grown with excessive one or other types of intrinsic point defects, crystal lattice cavities or silicon itself interstitials. Cohesive intrinsic point defects in silicon can significantly affect the yield potential of materials in the production of complex and high integrated circuits. For example, gate oxide integrity breakage is correlated with the concentration of COPs on the wafer surface. D. Graf, M. Suhren, U. Schmilke, A. Ehlert, W. v. Ammon and P. Wagner., J. Electrochem. Soc. 1998, 145, 275; M. Tamatsuka, T. Sasaki, K. Hagimoto and G. A. Rozgonyi, Proc. 6th. Int. Symp. On Ultralarge Scale Integration Science and Technology "ULSI Science and Technology / 1997", The Electrochemical Society 1997, PV97-3, p. 183; And in T. Abe, Electrochem. Soc. Proc. 1998, PV98-1, 157; N. Adachi, T. Hisatomi, M. Sano, H. Tsuya, J. Electrochem. Soc. 2000, 147, 350.

At the wafer surface, the COPs appear as pits with walls covered with silicon dioxide and are typically about 50-300 nm wide and can be up to about 300 nm deep. Heat treatment of the wafer in certain environments increases the migration of silicon atoms to the COPs, reducing the depth of the COPs until they appear as shallow dish-shaped depressions that are not normally detected by automated inspection tools. Previously disclosed heat treatments or thermal annealing processes include long time annealing (eg, longer than about 30 minutes) in a hydrogen atmosphere to produce surfaces that are substantially COP free. D. Graf, U. Lambert, M. Brohl, A. Ehlert, R. Wahlich, P. Wagner., J. Electrochem. Soc. 1995, 142, 3189. Annealing wafers in an argon environment is also disclosed. D. Graf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. v. Ammon and P. Wagner, Electrochem. Soc. Proc. 1996. 96-13, 117; lida, W. Kusaki, M. Tamatsura, E. lino, M. Kimura, and S. Murasoka, Electrochem. Soc. Proc. 1999, 99-1, 449. Also, annealing wafers in a mixture of H ₂ and Ar has been attempted for GOI improvement with surface COP disappearance and similar increase in haze. T. Abe, Electrochem. Soc. Proc. 1998, 98-1, 157; M. Tamatsuka, N. Kobayashi, S. Tobe, and T. Masiu, Electrochem. Soc. Proc. 1999, 99-1, 456; D. Graf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. v. Ammon, and P. Wagner, Electrochem. Soc. Proc. 1996, 96-13, 117; And in W. lida, M. Kusaki, E. Tamatsura, MK lino, S. Muraoka, Electrochem. Soc. Proc. 1999, 99-1, 449. The copper removal process of the present invention may be used to remove COPs located in the surface and bulk of the wafer (eg, an area extending in depth from the surface to a depth of at least about 10 μm). Note that this may inherently be included in the heat treatment.

Anomalies on the surface of a silicon wafer are typically laser scattering inspection tools, regardless of whether they are particles (eg abrasive particles), cohesive interstitial defects or cohesive void defects (eg COPs). Is detected by. Examples of suitable commercially available laser scattering inspection tools include SURFSCAN 6220 and SURFSCAN SP1 from KLA-Tencor, Mountain View, California, USA, and CR80, CR81 and ADE Optical Systems Corp. of Charlotte, North Carolina, USA. CR82. These tools can determine the size and location of defects (commonly called LPDs) on the silicon wafer surface. When measuring the size of LPDs on the surface of a wafer using a laser scattering inspection tool, it is well known that the actual size of the LPD is not determined. Instead, the detected defect (ie, light scattering event) scatters light equivalent to a latex sphere (LSE) of a certain diameter (e.g., for laser scattering inspection tools such as SURFSCAN 6220 and SURFSCAN SP1). Latex spheres with diameters greater than the current detection limit of about 0.095 μm). Prior to the heat treatment, the cavity-rich wafer typically has a concentration of greater than about 3LPDs / cm 2, about 6LPDs / cm 2, or even about 8LPDs / cm 2 on the front side of the wafer.

Typically, the heat treatment includes heating one or more wafers and removing layers of silicon oxide (eg, a native oxide layer) from the surfaces of the heated wafers. Preferably, the wafers are heated to a temperature of at least about 1100 ° C, more preferably at least about 1150 ° C, even more preferably from about 1200 ° C to about 1250 ° C. This heating is preferably performed in an atmosphere in which the surfaces of the silicon wafers contain little oxidizing agents, such as CO ₂ (eg, less than about 0.001 wt% of oxidant, preferably less than about 0.0001 wt% of oxidant, most preferably Is performed by exposure to or in contact with 0 wt% oxidant). In addition, the atmosphere preferably does not substantially etch or remove silicon from the front surface free of native oxide (eg, less than about 0.1 nm / min of silicon is removed from the surface of the silicon wafer). Such an environment may comprise a monoatomic inert gas selected from the group consisting of hydrogen, helium, neon, argon, krypton, xenon and mixtures thereof. Preferably, hydrogen is not introduced until the temperature in the furnace reaches above about 950 ° C. As such, monoatomic inert gases are preferred and argon is the most preferred monoatomic inert gas, since argon is the lowest cost and most widely available monoatomic inert gas. High purity argon is commercially available in various grades such as ultra high purity grade (UHP 5) with a purity of 99.999 wt% and ultra large scale integrated circuit grade (VLSI 5.7+) with a purity of 99.9995 wt%.

The heat treatment of the present invention may be carried out in any number of annealing furnaces or commercially available heat treatments in which at least one wafer and preferably a plurality of wafers are heated or exposed in contact with one or more controlled atmospheres. One example of such a furnace is an ASM model A412 vertical furnace, in which 125 silicon wafers are mounted in a silicon carbide boat made by AG Electronic Materials, for example. The atmosphere in which the wafers are exposed flows through the furnace / reactor preferably at a rate of about 5 liters / minute to about 100 liters / minute, more preferably at a rate of about 10 liters / minute to about 20 liters / minute. The pressure of the atmosphere in the furnace may be in the range of sub-atmospheric to super-atmospheric, but atmospheric pressure is preferred due to cost and safety relationships.

The wafers are preferably heated at a rate that does not cause slip. More specifically, if the wafer is heated too quickly (eg, at a rate greater than about 35 ° C. per second), it creates enough internal stress to cause different sides in the wafer to move (eg, slip) relative to each other. There is a thermal gradient that can be developed. In general, the rate of change is not overly important until the temperature of the wafer exceeds about 750 ° C., but between about 750 and 1100 ° C. the temperature of the wafer does not change more than about 40 ° C. per minute to avoid slipping. It is preferable. Between about 1100 and about 1150 ° C., the rate of temperature change is preferably controlled to about 10 ° C. or less per minute to avoid slippage. Between about 1150 and about 1200 ° C., the speed is preferably controlled to about 5 ° C. or less per minute to avoid slippage. In view of the foregoing, the temperature profile of the wafer is preferably similar to a parabola with an extended horizontal portion corresponding to the period during which the wafer is maintained at a substantially constant temperature prior to cooling.

Silicon oxide (eg, typically about 20 GPa thick or less, when reaching a temperature of at least about 1100 ° C., more preferably at least about 1150 ° C., and even more preferably from about 1200 ° C. to about 1250 ° C. Native oxide layer) is removed from the surfaces of the wafers. The atmosphere or environment may be the same as that used to heat the wafers to the annealing temperature or may be modified. As mentioned above, the wafer is typically heated to an annealing temperature in an environment or atmosphere containing argon. When the annealing temperature is reached, it may be desirable to introduce hydrogen into the atmosphere or environment. Once introduced, the hydrogen concentration in the atmosphere or environment is typically at least about 20% hydrogen and the remainder is preferably monoatomic inert gas such as argon. In general, higher hydrogen concentrations are preferred. As such, the atmosphere comprises at least about 30, 40, 50, 60, 70, 80, 90 or even 100% hydrogen in order of increasing preference. The hydrogen gas is preferably 99.99999999% pure. At a temperature of at least about 1100 ° C., the oxide is removed from the wafer surface at a rate between about 1 and 2 nanometers per minute. Thus, conventional native oxide layers are removed in less than about 2 minutes.

Although the native oxide is quickly removed, at a temperature of at least about 1100 ° C. for at least a sufficient time period to reduce the size of the COPs on or near the surface of the silicon wafer and / or to reduce the concentration of LPDs on the surfaces of the wafers, Preferably the wafers are contacted with hydrogen, monoatomic inert gas or a combination thereof. The reduction in cohesion void defects is mainly due to the migration of silicon atoms from the surface and sub-surface regions surrounding the cohesion void defects to defect sites (after the oxide is removed from the walls of the sites). Preferably, the period is from about 30 minutes to about 90 minutes. More preferably, the exposure to the cleaning gas is about 60 minutes.

After exposure to an atmosphere comprising hydrogen, monoatomic inert gas, or a combination thereof for a desired period, the flow of hydrogen is preferably stopped when hydrogen has been introduced, and the oxide-free front surface of the heated wafer is vacuum (e.g. For example, less than about 5 milliTorr), or preferably as described above, is exposed to an atmosphere comprising one or more monoatomic gases (eg, argon). Typically, disconnection of hydrogen or reintroduction of an argon atmosphere is consistent with the temperature reduction of the wafers and at least continues until the wafers are cooled to a temperature of about 800 ° C. or less. Note that the migration of silicon atoms is believed to continue until at least the wafer has cooled to about 1100 ° C. To avoid slippage, the temperature reduction of the wafers to about 1100 ° C. typically occurs in at least about 10 minutes. Preferably, the temperature decrease to about 1100 ° C. occurs between about 30 minutes and about 90 minutes. More preferably, the period is about 60 minutes.

Referring to FIG. 1, by applying a heat treatment of the present invention to a silicon wafer, a stratum 21 extending from the front surface 3 to a distance D _s (eg, typically at least about 5 μm) is introduced. In forming, the layer 21 has a reduced cohesive void defect density when compared to the density of defects across the starting material. Between the layer 21 and the virtual center plane 7, it is believed that the density of the cohesive void defects 20 does not change. Specifically, the portion of the wafer between layer 21 and virtual center plane 7 (ie, the bulk of the wafer) is between about 1 × 10 ³ defects / cm 3 and about 1 × 10 ⁷ defects / cm 3, typically about 1 × 10 ⁵ defects / cm 3 Layer 21 has a density of aggregated void defects that is preferably less than about 50% of the density of aggregated void defects in the bulk of the wafer, while having a density of aggregated void defects between 1x10 ⁶ defects / cm 3. More preferably, the density of aggregated void defects in layer 21 is less than about 30%, 20% or 10% of the density of aggregated void defects in the wafer bulk. Most preferably, layer 21 is substantially free of cohesive void defects, ie the density of cohesive void defects is below the detection limit of these defects, which is currently about 10 defects / cm 3.

Reduction of the size and / or concentration of cohesive void defects is realized similar to the reduction of the average concentration of LPDs on the wafer surface. Preferably, the reduction is at least about 50%, 70%, 80%, 90% or more. Thus, an average concentration of LPDs less than about 1 LPD / cm 2 (greater than about 0.095-0.120 μm LSE) can be readily obtained. Preferably, the average concentration of LPDs is less than about 0.5 LPDs / cm 2, more preferably less than about 0.1 LPDs / cm 2, even more preferably less than about 0.05 LPDs / cm 2, even more preferably Is less than about 0.005 LPDs / cm 2. Even more preferably, the size and / or concentration of the cohesive void defect is reduced to such an extent that the defects cannot be detected by current laser scattering inspection tools.

The reduction of cohesive void defects on the surfaces of such silicon wafers is not accompanied by an unacceptable increase in haze on the surfaces of the heat treated silicon wafers. "Haze" is defined as the ratio of scattered light (photons) to incident light and is believed to depend at least in part on the micro roughness of the surface. For example, The Effects of H ₂ Annealing on the Si Surface and its Use in the Study of Roughening During Wet Chemical Cleaning, Electrochem. By S. Varharerbeke, T. Futatsuki, R. Messousi and T. Ohmi. Soc. Proceedings, Vol. 93-8, p. 1170, 1993. An unacceptable increase in haze is defined as an increase in haze of greater than about 500% when compared to haze on the surface of a silicon wafer before heat treatment. Thus, the acceptable increase in haze is less than about 500% compared to haze on the silicon wafer surface prior to heat treatment. Preferably, the increase in haze is less than about 350%, more preferably less than about 300%, even more preferably less than about 200%.

The level of haze is determined using a laser scattering inspection tool that collects scattering data and filters it using a haze processor to separate the haze information from the LPD information. Each inspection tool has its own unique optical design, and as a result, different haze values are produced by inspecting the wafer using different inspection tools. To scan the entire front surface of the wafer, the SURFSCAN 6220 tool directs the laser beam across the wafer surface as the wafer moves in a direction perpendicular to the direction in which the beam travels. As such, the orientation of the wafer with respect to the scanning laser beam can affect the haze values (all haze levels disclosed herein were determined using the notch of the wafer facing the 6 o'clock position in the loading cassette). . In contrast, the newer SURFSCAN SP1 inspection tool has symmetrical acquisition optics and uses a spiral scanning pattern to ensure that the measurement of haze is not affected by the orientation of the wafer. Typically this is undesirable because surface haze higher than about 1.2 ppm as measured by the SURFSCAN 6220 laser scattering test tool limits the ability to detect LPDs below about 0.2 μm LSE. Similarly, surface haze higher than about 0.2 ppm measured by the SURFSCAN SP1 laser inspection tool is considered undesirable. In comparison, the haze on the surface of the epitaxial silicon wafer measured by SURFSCAN 6220 is typically about 0.8 ppm to 1.1 ppm.

The front surface of the silicon wafer treated according to the method of the present invention is less than about 1.2 ppm, preferably less than about 0.7 ppm, more preferably between about 0.5 ppm and about 0.3 ppm measured by the SURFSCAN 6220 laser scattering inspection tool. Has a haze level. As measured by the SURFSCAN SP1 laser scattering test tool, the front surface of the silicon wafer treated according to the method of the present invention is less than about 0.17 ppm, preferably less than about 0.15 ppm, more preferably about 0.13 ppm to about 0.10 ppm Has a haze level between.

In addition to reducing the concentration of COPs on the surface of the wafers, the annealing process also installs what is commonly referred to as a denuded zone. The exposed zone is the area extending inward from the surface of the wafer, substantially free of oxide precipitates (eg, a typical exposed zone includes less than about 1 × 10 ⁶ oxygen precipitates or bulk microdefects per cm 3). . In contrast, the region of the wafer inward from the exposed zone typically contains oxygen precipitates or bulk microdefects at concentrations between about 1 × ^{10 7} and about 5 × ^{10 10} precipitates / cm 3. Referring to FIG. 2, there is shown a wafer having an oxygen precipitate distribution that can be formed by heat treating a wafer prepared in accordance with the present invention. In this particular embodiment, the wafer substrate 4 is characterized by regions 93 and 93 '(' exposed zone ') free of oxygen precipitates 95. These zones extend from the front 3 and back 5 to the depths of D _dz and D _dz ', respectively. Preferably, D _dz and D _dz ′ are each between about 10 μm and about 50 μm, more preferably between about 20 μm and about 30 μm. Between regions 93 and 93 'where there is no oxygen precipitate, there is a region 94 that includes a substantially uniform concentration of oxygen precipitate. It should be appreciated that the purpose of FIG. 2 is to aid the skilled person in the present invention by illustrating only one embodiment of the invention. The present invention is not limited to this embodiment.

Copper Removal from Wafers

The scope of the present invention should not be construed as limiting the application scope of the present invention primarily due to the fact that the process of the present invention relates to embodiments that are involved in heat treatment such as hydrogen-argon annealing. The process of the present invention can be performed in conjunction with other relatively hot silicon wafer processes involving oxidation of the wafer surface.

The process of the invention is carried out on one or more polished wafers which are preferably free of oxygen or oxide on their surfaces. If the process involves removing metallic contaminants by hydrogen-argon annealing, this process typically involves forming an oxide layer on the bare silicon wafer surface, which is why the native oxide layer (usually Less than about 20 microns in thickness), thereby reducing or eliminating the size of the COPs on or near the surface of the wafer.

For the purpose of reducing metallic contamination, if the oxide layer is thick enough to form a strained layer in silicon on or near the wafer surface, the thickness of the oxide layer is not overly important and the wafer surface has sufficient copper, The bulk copper can be reduced to the desired level after the wafer is cleaned. In addition, it is desirable that the thickness of the oxide layer is not large enough to prevent removal of diffused copper during the cleaning operation. The results to date indicate that by forming an oxide layer with a thickness between about 5 and about 20 microns, satisfactory retention of the diffused copper and complete removal of the diffused copper using standard SC1 and SC2 cleaning operations can be achieved. Indicates. Preferably, the oxide layer thickness is less than about 15 GPa. Even more preferably, the oxide layer thickness is between about 7 and about 15 microns. Although the oxide layer exceeds about 20 microns thick (i.e. it may be a relatively thick oxide layer), this is not generally the case, because removing the diffused copper is typically a longer cleaning operation, a greater amount of This is because cleaning solution (s), and / or more aggressive cleaning solutions are needed, any of which may increase the cost of the wafer and / or damage the wafer surfaces.

Heat treatments such as hydrogen-argon annealing are typically performed simultaneously on multiple wafers. Specifically, hydrogen-argon annealing is typically performed in an annealing furnace configured to process multiple wafers in a single batch and having such a size. One such furnace is the previously mentioned ASM model a412 vertical furnace. In order to effectively remove metallic contaminants from the group of wafers, the uniformity of the oxide layer thickness between the wafers is not overly important. That is, even though certain wafers have relatively thin oxide layers, for example 5 ms and other wafers have relatively thick oxide layers, for example 20 ms, effective removal of copper is achieved for all processed wafers. Can be. However, the uniformity of the oxide layers tends to be a factor for other wafer qualities. For example, if the thickness of the oxide layer is not uniform across the wafer (e.g., the oxide thickness change for the wafer group is greater than about 5 mm between the thinnest oxide layer and the thickest oxide layer), then the subsequent cleaning process. May create surface defects (eg, pits) on certain wafers, especially those with relatively thin oxide layers. Specifically, the relatively thin oxide layer is believed to cause the cleaning process to excessively remove silicon from the wafer to form pits. These defects can be detected using laser scattering inspection tools such as Tencor 6220 or Tencor SP-1 mentioned above and are referred to as LPDs.

In view of the foregoing, when carrying out the process of the invention on a plurality of wafers simultaneously, it is desirable to keep the thickness variation between oxide layers (formed prior to or during the process) to a minimum. Specifically, for the group of wafers processed simultaneously, the difference between the thinnest oxide layer and the thickest oxide layer is preferably less than about 5 GPa. More preferably, the difference between the thinnest oxide layer and the thickest oxide layer is less than about 3 GPa. In other words, for a group of wafers having an average oxide thickness that falls within any of the preceding preferred ranges, the standard deviation (sigma) from the average oxide thickness for that group is about 2.0 mm in order of increasing preference. Is less than, or less than, 1.0 ms, 0.5 ms, 0.3 ms, 0.2 ms, 0.1 ms.

As mentioned above, when carrying out the process of the present invention as part of an existing heat treatment such as hydrogen-argon annealing, the oxide layers on the wafers are typically formed as part of the process, because any oxide on the surface Is typically removed (ie the surfaces of the wafers are essentially bare silicon). In such a situation, the process of the present invention preferably includes forming oxide layers on silicon wafers via gas-phase oxidation. In general, gas phase oxidation involves contacting one or more silicon wafers with an atmosphere, environment, or gas containing oxygen. Although any suitable oxidizing atmosphere, environment or gas known to those skilled in the art can be used (eg oxygen, ozone, water vapor or combinations thereof), oxygen is generally preferred because of its relatively low cost. This is because it is widely available in purity sufficient for semiconductor manufacturing. In the case of using oxygen, it is generally preferred that the oxygen is pure (eg 99.99999999% purity). To achieve this purity, oxygen is typically treated with dry equipment such as those available from SAES PURE GAS and NUPURE. Thus, in one embodiment of the invention, the surfaces of the silicon wafers are exposed to or in contact with an atmosphere containing oxygen for a period of time sufficient to form oxide layers on the wafers in accordance with the above-described thickness and variation ranges. .

Vapor phase oxidation is typically performed, at least in part, while the wafers are at elevated temperatures (eg, temperatures or temperatures above about 500 ° C.). More specifically, when carrying out the process of the present invention as part of a hydrogen-oxygen anneal, the wafers are preferably oxidized with cooling from the maximum annealing temperature (eg, from about 1200 ° C. to about 1250 ° C.). . Although wafers may be oxidized near any temperature or in a range of temperatures, they are preferably oxidized at temperatures below about 1200 ° C. More preferably, the wafers are oxidized at temperatures below about 1100 ° C, 1000 ° C or even 900 ° C. Even more preferably, oxidation of the wafers begins when the wafers are cooled to a temperature below about 800 ° C. Even more preferably, oxidation of the wafers occurs after the wafer is cooled to a temperature below about 775 ° C. Alternatively, in other words, the oxidation start temperature is preferably 800 ° C. or lower, more preferably about 775 ° C. or lower. By performing the oxidation at temperatures below about 800 ° C., the oxide layers tend to grow to any thickness uniformly according to previously desired ranges. Specifically, it has been observed that at temperatures above about 800 ° C., the oxidation reaction tends to be controlled by the diffusion of oxygen in the atmosphere, resulting in a relatively non-uniform oxide layer thickness between the wafers. More specifically, wafers near gas inlets tend to have significantly thicker oxide layers than wafers located farther from those inlets. In contrast, at temperatures below about 800 ° C., the oxidation reaction is kinematically controlled (ie, the oxidation reaction tends to be controlled by the reaction between silicon and oxygen rather than the ability of oxygen to diffuse to the wafer surface). . Thus, oxides are formed on a plurality of wafers at substantially similar velocities regardless of their position in the chamber, with the result that the thicknesses of the oxide layers tend to be substantially uniform.

Although it is generally desirable to start oxidation at temperatures below about 800 ° C., gas phase oxidation may be initiated at temperatures above about 500 ° C., at least readily included in existing heat treatments, to minimize process time, and to reduce costs. It is also preferable. More preferably, the oxidation is initiated at a temperature of at least about 600 ° C. Even more preferably, oxidation is initiated at a temperature of at least about 700 ° C. Even more preferably, oxidation is initiated at a temperature of at least about 750 ° C.

In addition to the oxidation temperature, it has been found that the concentration of oxygen in the atmosphere tends to affect the uniformity of the oxide layers. Specifically, it was found that the oxygen concentration in the atmosphere is preferably increased as the oxidation temperature is raised. Without wishing to be bound by any theory, the foregoing relationship shows that oxides formed on wafers at relatively high temperatures (eg, higher than about 1100 ° C.) tend to evaporate from the surface during cleaning It is believed that this is due to the fact that it can lead to non-uniform oxide layers causing the fitting of. This evaporation tendency is particularly severe at relatively low oxygen concentrations (eg below about 64 ppm). Thus, if wafers are oxidized at temperatures higher than about 800 ° C., the oxygen concentration in the atmosphere is preferably increased to reduce the tendency for pit formation. Although increasing the oxygen concentration tends to improve oxide layer uniformity, it also tends to increase the oxide layer thickness.

Although the oxygen concentration in the oxidizing environment is not overly important, at least for the purpose of reducing the copper concentration, previous observations have shown that lower oxygen concentrations at lower oxidation temperatures are limited to limit the formation of surface defects on the wafers. Indicates that it is preferable. For example, although exposing wafers to an oxidizing environment containing about 15000 ppm of oxygen is effective for copper removal, this results in the wafers having an excessive amount of light point defects from the fitting (Table below). See test group 4 wafers in A). Thus, in general, the oxygen concentration in the oxidizing environment is preferably less than about 10,000 ppm (ie about 1 percent) to ensure that the processed wafers do not have excessive amounts of light point defects. In order of increasing preference, the oxygen concentration is more preferably less than about 5000, 1000, 500, 100 or even lower. For example, exposure of the wafers to an oxidizing environment comprising about 64 ppm indicates good copper removal and low degree of surface defect formation (see Test Group 7 wafers in Table A). On the low side, it is generally preferred that the oxygen concentration in the oxidizing environment be at least about 1 ppm. More preferably, the oxygen concentration is at least about 10 ppm. Even more preferably, the oxygen concentration is at least about 25 ppm.

In addition to the oxidation temperature (s) and oxygen concentration, the oxidation period tends to play a role in the uniformity of the oxide layers, especially at relatively low oxygen concentrations. Specifically, the length of time that the wafers are in contact with the oxidizing environment is preferably controlled such that the oxide layers have uniform thicknesses. More specifically, it has been observed that as the oxygen concentration decreases, the length of time needed to uniformly oxidize the wafers tends to increase. For example, at a relatively high oxygen concentration of about 15,000 ppm, wafers tend to oxidize uniformly in a short time, such as 4 minutes (see Test Wafer Groups 3 and 4 in Table A). However, at substantially lower oxygen concentrations (eg, about 64 ppm), an oxidation period of about 4 minutes or even 8 minutes will tend to oxidize the wafers unevenly (see Test Wafer Groups 5 and 6 in Table A). Reference). However, by prolonged exposure or contact with a low concentration of oxidizing environment, copper can be removed without negatively affecting the surface quality of the wafers (see, for example, test wafer group 7 in Table A). In summary, although the length of time that wafers are exposed to or in contact with the oxidizing environment can vary widely (eg, may be as short as about 1 minute or as long as about 1 hour), it is common for polished wafers. It is generally preferred that the period is preferably controlled to produce uniform oxide layers that are not thick enough to require longer than phosphorus and / or more aggressive cleaning operations and have a thickness sufficient for effective copper gettering. Typically, these conditions are met if the length of time the wafer is exposed to an oxidizing environment in the chamber is at least about 10 minutes. Preferably, the period is at least about 20 minutes. More preferably, the period is at least about 30 minutes. Even more preferably, the period is at least about 40 minutes.

Note that these periods are typically obtained without modifications to the rate or duration at which wafers are cooled during conventional hydrogen-argon annealing. In fact, about 750 ° C. to about 700 ° C. until wafers are removed from the heat treatment furnace, typically after the wafers are cooled to temperatures below about 600 ° C., 550 ° C., 500 ° C., 450 ° C., 400 ° C. or even lower. Preferably, the wafers are exposed to or in contact with the oxidizing environment when reaching a temperature within the range of. It is believed that removing wafers from the furnace when reaching a temperature of about 450 ° C. tends to maximize throughput, thereby reducing manufacturing costs. The furnace is typically controlled to cool the wafers below about 1000-900 ° C. at a rate below about 30 ° C. per minute (preferably, the speed is about 10 to 20 ° C. per minute), so the temperature of the wafers is at least about For a period of 10 minutes (preferably between about 15 minutes and about 30 minutes) it is preferably between about 750 ° C and about 450 ° C.

As mentioned above, the process of the present invention generally involves diffusing metal contaminants, especially copper, from the bulk of the wafer to the strain region on or near the surface of the wafer. Specifically, the gettering process heats the wafers to thermally drive them to at least about 500 ° C. (eg, between 1100 ° C. and about 1200 ° C.), which typically dissociates copper-boron complexes, and then drives the wafers below about 500 ° C. Cooling to (eg, between about 400 ° C. to about 300 ° C.), the released copper diffuses into the oxide induced strain region that can be removed from the wafer using standard, modern cleaning methods and compositions. On the other hand the diffusion of copper has mainly the wafer is decreased as cooled to below about 500 ℃ dramatically the solubility of the copper in the copper diffusion in the silicon in the silicon is held in (diffusion length) is relatively high (for example, 7.4x10 ^-6 Cm 2 / sec) is due to the fact.

The process of the invention is preferably suitable for diffusion of copper released for a period sufficient to reduce the bulk concentration of copper to less than about 1x10 ¹⁰ atoms / cm 2, less than about 5x10 ⁹ atoms / cm 2, or less than about 1x10 ⁹ atoms / cm 2. The wafers are performed to lie within the temperature range. In general, for a given copper concentration, the required period tends to be shorter at higher temperatures, and similarly, longer periods are associated with lower temperatures. For example, if the wafer is held at about 500 ° C., the time required for copper diffusion is as small as about 30 seconds. In contrast, if wafers are rapidly cooled or quenched from a temperature where the copper concentration is below the solubility limit for about 100 ° C., the period at about 100 ° C. may be as long as about 3 hours. At temperatures where copper is particularly mobile and the solubility limit is well below the copper concentration in the wafer (eg, below about 300-400 ° C., above about 100 ° C.), a sufficient period may be in the range of tens of minutes (eg , About 10 minutes to about 60 minutes). Advantageously, the periods and temperatures associated with cooling the wafers as part of a heat treatment such as hydrogen-argon annealing are typically sufficient to achieve the desired reduction in bulk copper. For example, acceptable levels of copper diffusion cool wafers (typically between about 15 to about 30 minutes) at a rate between about 750 ° C. and about 450 ° C. to about 10 to 20 ° C. per minute, and reach 450 ° C. Acceptable levels of copper diffusion were observed by removing wafers from the furnace (typically about 20 minutes) and by cooling to room temperature outside the furnace (typically about 20 minutes). Note that exposure to the oxidizing environment and diffusion of copper into the strain region can occur at least partially overlapping or sequentially.

After the heat treatment or annealing is complete, a cleaning step is performed on the wafer (s) to effectively remove copper from the wafer (s). Typical cleaning solutions include piranha mixtures (mixtures of sulfuric acid and hydrogen peroxide), RCA type SC1 and SC2 cleaning solutions (eg F. Shimura, Semiconductor Silicon Crystal Technology , Academic Press, 1989, pp. 188-191 And Annex XII, which is incorporated herein by reference). Wafers may be immersed in a cleaning solution or exposed to a scrubbing jet.

The RCA type SC1 solution removes organic contaminants and particles by both the solvation of ammonium hydroxide and the strong oxidation of hydrogen peroxide. Typical SC1 cleaning solutions are fed by H ₂ O: H ₂ O ₂ : NH ₄ OH volume (supplied with 30-35 weight percent H ₂ O _{2 in} water and 28-30 weight percent NH ₄ OH in water). Between about 1000: 1: 1 and about 1: 1: 1. That is, the SC1 cleaning solution comprises H ₂ O, H ₂ O ₂ , and NH ₄ OH and the ratio of H ₂ O to H ₂ O ₂ (supplied with 30-35 weight percent H ₂ O ₂ in water) is about Is between 1000: 1 and about 1: 1, and the ratio of H ₂ O to NH ₄ OH (supplied with 28-30 weight percent NH ₄ OH in water) is between about 1000: 1 and about 1: 1, H ₂ O ratio of H ₂ O ₂ is independent of the ratio of H ₂ O for NH ₄ OH. Preferred SC1 cleaning solutions include a ratio of about 100: 1: 1 to about 5: 1: 1 by H ₂ O: H ₂ O ₂ : NH ₄ OH volume. Preferably, the SC1 cleaning solution is heated to a temperature between about 30 to about 80 ° C and more preferably to a temperature between about 60 to about 80 ° C.

Wafers may be cleaned in the SC1 solution for a period between about 5 to about 30 minutes. If the wafers are immersed in the cleaning solution for a longer time, excessive etching, fitting and roughening of the surface may occur. After cleaning, the wafers are immersed in a rinse bath to quench the reaction and remove the SC1 cleaning liquid from the wafer surfaces. Wafers are rinsed in deionized water having a resistivity of about 3 to about 18 megohms, preferably greater than about 17 megohms, for a period of about 2 to about 60 minutes, typically about 5 to about 45 minutes. .

Conventional SC2 baths may comprise a ratio of about 1: 1: 5 to about 1: 1: 1000 by volume of HCl: H ₂ O ₂ : H ₂ O. The temperature of the SC2 solution is preferably between about 10 and about 90 ° C. and the silicon wafers are immersed in a flowing bath of the solution for a period of at least about 0.1 minutes. Such solutions effectively remove alkali and transition metals and prevent re-deposition from solution by forming soluble metal complexes.

HF solutions can also be used to clean silicon wafers. Typical HF solutions include from about 1: 1 to about 1: 10,000 ratios by volume of HF: H ₂ O (supplied with water as 49 weight percent HF). To enhance the metal removal, the solution is HCl (1000: 1 to 1: 1000 ratio by HF: HCl volume), hydrogen peroxide (1: 1 to 1: 1000 ratio by HF: H ₂ O ₂ volume), iso Propyl alcohol (10,000: 1 to 1:10 ratio by HF: IPA volume) or ozone (about 0.05 to about 50 ppm).

After cleaning, wafers are preferably has from about 1x10 ¹⁰ atoms / ㎠ less, more preferably from about 5x10 ⁹ atoms / ㎠ less, and more preferably, from about 1x10 ⁹ atoms / ㎠ surface is less than the copper concentration. Further, the washed wafers are preferably has from about 1x10 ¹⁰ atoms / ㎠ less, more preferably from about 5x10 ⁹ atoms / ㎠ less, and more preferably, from about 1x10 ⁹ atoms / ㎠ lower than bulk copper concentration.

Yes

The annealing furnace used is an ASM model A412 vertical furnace equipped with 125 slots of silicon carbide boats designed to hold 200 mm wafers and high purity TSQ-10 quartz tubes manufactured by Toshiba Ceramics. The silicon carbide boat has a high purity silicon carbide coating deposited thereon using chemical vapor deposition by AG Electronic Materials. After performing the annealing process, the wafers are cleaned using SubMicron Systems wet benches and standard SC1 and SC2 cleaning solutions described in more detail above.

Each test group of wafers is standard hydrogen annealed. Specifically, wafers (with natural oxide layers) are placed in a furnace and heated to a temperature of about 1200 ° C., held at 1200 ° C. for about 1 hour and then cooled. The plot of temperature as a function of annealing time from about 450 ° C. to the maximum temperature again to about 450 ° C. is generally similar to a parabola except that there is an extended horizontal portion corresponding to a 1200 ° C. hold period. When the wafers are heated to about 1200 ° C. and cooled from about 1200 ° C., the wafers are exposed to an atmosphere containing argon. However, when the wafers are held at about 1200 ° C. for about one hour, the wafers are exposed to an atmosphere containing about 100% hydrogen. The gas flow rates of argon and hydrogen through the furnace are about 20 liters per minute and 12 liters per minute, respectively.

In addition to argon, wafers in test group 3-7 are exposed to oxygen as they cool. The oxygen concentration in the furnace is varied for these wafers. The flow of oxygen begins when the wafers are cooled to about 700 ° C. (ie, the oxygen onset temperature is about 700 ° C.) and is maintained for the period provided in Table A below. Note that the flow of argon is maintained from beginning to end (ie, the flow of oxygen is added to the flow of argon). The oxygen flow rate for test groups 3 and 4 is about 300 milliliters per minute, corresponding to an atmospheric oxygen concentration of about 15,000 ppm. The flow rate of oxygen for test groups 5-7 is about 2 milliliters per minute, corresponding to an atmospheric oxygen concentration of 64 ppm. The period of oxygen flow for test group 7 corresponds to the time required to cool the wafers until removal from the furnace at about 700 ° C. to about 450 ° C. For test groups 3-6, after the flow of oxygen has ended, the flow of argon continues until the wafers are removed from the furnace upon reaching about 450 ° C. Note that at about 700 ° C. to about 450 ° C., the cooling rate is approximately 15 ° C. per minute and is substantially constant (ie, the decrease in temperature as a function of time is nearly linear).

The thickness of the oxide layers on the wafers is measured using ellipsometry. Certain wafers (shown in Table A) are cleaned according to the above description of SC1, SC2 cleaning. After the oxide layer thickness measurement, if performed after cleaning of the wafers, the surface concentration or bulk concentration of copper for the wafers is determined according to the method described above. After measuring the copper concentration, the wafers were analyzed for the presence of light weight defects. The results of the preceding tests are provided in Table A below.

The results provided in Table A are interpreted to arrive at some conclusions. For example, wafers from Control 1 and Control 2 indicate that cleaning reduces the amount of copper on the surface of the annealed wafer. These surface copper concentrations represent the amount of copper on the wafer without performing bulk copper crystals. The results for test groups 1 and 2 indicate that wafers have acceptable levels of light weight defects without in situ oxide growth, but exhibit relatively high bulk copper concentrations. The results for test group 3 wafers indicate that a significant amount of copper diffusion into the strain region was achieved by the process. Test results of Group 4 wafers treated the same as Group 3 wafers except for the addition of a cleaning step prior to determining the bulk copper concentration, resulted in a significant amount of copper removed by a combination of annealing and cleaning and of acceptable levels. It indicates that wafers with bulk copper were produced. Although copper is effectively reduced in group 3 and 4 wafers, the relatively high number of light point defects indicates that the process negatively affects the surfaces of the wafers. Without being bound by a particular theory, it is believed that the number of light weight defects is high because the oxide layers are formed relatively thick and relatively fast. Test results for group 5 and 6 wafers also indicate that although the process effectively removed the bulk copper, it could negatively affect the quality of the surface. For these wafers, the relatively high concentration of light weight defects is believed to be due to the fitting caused by non-uniform oxidation of the wafers. However, test results for test group 7 wafers, in addition to copper abatement, can be incorporated into existing thermal treatments such as hydrogen-argon annealing to effectively reduce or eliminate cohesive void defects such as COPs. It can be performed.

It is to be understood that the above description is illustrative and not restrictive. Many embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the present invention should not be determined based solely on the above description but on the full scope of the claims and their equivalents provided by those claims.

When introducing elements of the invention or embodiments thereof, the articles “a”, “an”, “the” and “said” may have one or more elements present. It is intended to mean. The terms "comprising", "including" and "having" are intended to be inclusive and mean that there are additional elements other than the listed elements.

Citation of a numerical range by end points includes all the numbers that fall within that range. For example, the ranges described as being between 1 and 5 include 1, 1.6, 2, 2.8, 3, 3.2, 4, 4.75 and 5.

Claims (41)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete A method for removing contaminants selected from copper and nickel from a silicon wafer having a silicon wafer surface and a silicon wafer interior, Heating the silicon wafer to a temperature of at least 1100 ° C. and exposing the silicon wafer surface to a cleaning environment selected from the group comprising hydrogen, helium, neon, argon, krypton, xenon and mixtures thereof, Creating a deoxidized silicon wafer by removing silicon oxide; Cooling the silicon wafer at a temperature of at least 1100 ° C. to an oxidation start temperature in the cleaning environment; Exposing the deoxidized silicon wafer to an oxidizing environment at the oxidation start temperature to form an oxide layer on the silicon wafer surface to produce an oxidized silicon wafer having a strained layer at the interface between the oxide layer and the inside of the silicon wafer. Making; Controlling the temperature of the oxidized silicon wafer to diffuse contaminants from inside the silicon wafer into the strained layer; And Cleaning the silicon wafer to remove the contaminants diffused from the silicon wafer to the strained layer to produce a cleaned silicon wafer ≪ / RTI > 18. The method of claim 17, wherein the oxidizing environment comprises an oxygen concentration between 10 ppm and 100 ppm. The method of claim 17, wherein the oxide layer has a thickness of between 5 kPa and 20 kPa. The method of claim 17, wherein the deoxidized silicon wafer is exposed to the oxidizing environment when cooled to an oxidation initiation temperature of 800 ° C. or less or 775 ° C. or less. The method of claim 20, wherein the deoxidized silicon wafer is cooled at a rate of less than 30 ° C. per minute or between 10 ° C. and 20 ° C. per minute. 20. The method of any one of claims 17-19, wherein the silicon wafer is exposed to the oxidizing environment for a period between 30 minutes and 60 minutes. 20. The method of any one of claims 17-19, wherein controlling the temperature of the oxidized silicon wafer to diffuse contaminants from within the silicon wafer into the strained layer comprises: cleaning the silicon wafer by 5x10 ⁹ atoms. Maintaining the temperature of the silicon wafer below 500 ° C. for a period sufficient to have a bulk copper concentration of less than / cm 2 or less than 1 × ^{10 9} atoms / cm 2. 20. The method of any one of claims 17 to 19, further comprising annealing the deoxidized silicon wafer to produce an annealed silicon wafer prior to exposing the deoxidized silicon wafer to the oxidizing environment. , The silicon wafer is annealed by exposing the deoxidized surface of the silicon wafer to an annealing environment or vacuum selected from the group comprising hydrogen, helium, neon, argon, krypton, xenon and combinations thereof, thereby providing A method of facilitating the migration of silicon atoms to exposed agglomerated vacancy defects to reduce the size of the exposed agglomerated void defects. The method of claim 24, wherein the annealing environment comprises hydrogen and the surface of the silicon wafer is exposed to the annealing environment for a period of at least 10 minutes while the temperature of the silicon wafer is at least 1100 ° C. 25. 25. The method of claim 24, wherein the annealed silicon wafer is exposed to an environment comprising argon until the deoxidized silicon wafer is exposed to the oxidizing environment. delete delete delete delete delete A method for removing contaminants selected from copper, nickel and combinations thereof from a silicon wafer having a silicon wafer surface and a silicon wafer interior, Increasing the temperature of the silicon wafer to an annealing temperature of at least 1100 ° C. while exposing the silicon wafer to a heat-cooling environment comprising argon; When the silicon wafer is at the annealing temperature, the silicon wafer is exposed to an annealing environment selected from the group comprising hydrogen, helium, neon, argon, krypton, xenon, and combinations thereof for a period between 30 minutes and 90 minutes. Annealing the silicon wafer by removing the silicon oxide from the silicon wafer surface and facilitating the movement of silicon atoms to exposed cohesive void defects on the silicon wafer surface. Reducing steps; Reducing the temperature of the silicon wafer from the annealing temperature to an oxidation initiation temperature of 800 ° C. or less while exposing the silicon wafer to the heat-cooling environment; Exposing the silicon wafer to an oxidizing environment containing oxygen at a concentration between 10 ppm and 100 ppm when the temperature of the wafer is reduced from the oxidation initiation temperature, thereby forming an oxide layer on the silicon wafer surface and forming the oxide layer Forming a strained layer at an interface between the inside of the silicon wafer; Controlling a temperature reduction of the silicon wafer such that atoms of the contaminant can diffuse from inside the silicon wafer into the strained layer; And Cleaning the silicon wafer to remove the contaminants diffused from the silicon wafer to the strained layer ≪ / RTI > The method of claim 32, wherein the annealing temperature is between 1200 ° C. and 1250 ° C., the wafer is exposed to the annealing environment for 60 minutes, the oxidation start temperature is 775 ° C. or less, and a silicon wafer temperature is from the oxidation start temperature. Controlling the temperature reduction of the silicon wafer to decrease at a rate between 10 ° C./min and 30 ° C./min to a temperature of 500 ° C. or less. delete delete delete delete delete delete delete delete

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