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KR101141707B1 - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
KR101141707B1
KR101141707B1 KR1020060018448A KR20060018448A KR101141707B1 KR 101141707 B1 KR101141707 B1 KR 101141707B1 KR 1020060018448 A KR1020060018448 A KR 1020060018448A KR 20060018448 A KR20060018448 A KR 20060018448A KR 101141707 B1 KR101141707 B1 KR 101141707B1
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semiconductor chip
semiconductor
substrate
pair
chip
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KR1020060018448A
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Korean (ko)
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KR20070088179A (en
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조세훈
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삼성테크윈 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 본 발명은 중앙부가 개방되며, 양면에 배선층이 형성되며, 저면에는 외부와 전기적으로 연결되는 외부 접속 단자를 구비하는 기판; 상기 중앙부를 기준으로 상기 기판의 양측에 각각 실장되며, 상기 기판으로부터 상기 중앙부쪽으로 돌출되도록 실장되는 적어도 한 층의 반도체 칩쌍; 및 상기 적어도 한층의 반도체 칩쌍 중 최상부에 있는 양측의 반도체 칩들을 지지하도록 실장되는 상부 칩을 포함하며, 각층에서의 상기 반도체 칩쌍은 적어도 한 쌍이고, 상기 상부 칩을 제외한 반도체 칩들 중에서 이웃한 반도체 칩들의 본딩(bonding) 영역은 서로 반대 방향으로 형성된 반도체 패키지 및 그 제조 방법을 제공한다.The present invention is a center portion is open, the wiring layer is formed on both sides, the bottom surface has a substrate having an external connection terminal electrically connected to the outside; At least one semiconductor chip pair mounted on both sides of the substrate with respect to the center portion and mounted to protrude from the substrate toward the center portion; And an upper chip mounted to support the semiconductor chips on both sides of the at least one semiconductor chip pair, wherein the semiconductor chip pair in each layer is at least one pair, and a neighboring semiconductor chip among the semiconductor chips except the upper chip. Bonding regions of the two provide semiconductor packages formed in opposite directions and a method of manufacturing the same.

Description

반도체 패키지 및 그 제조 방법{Semiconductor package and method of manufacturing the same}Semiconductor package and method of manufacturing the same

도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 도시하는 단면도이다.1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도 2는 도 1에 도시된 반도체 패키지를 도시하는 사시도이다.FIG. 2 is a perspective view illustrating the semiconductor package shown in FIG. 1.

도 3은 도 1에 도시된 반도체 패키지를 도시하는 저면도이다.3 is a bottom view illustrating the semiconductor package illustrated in FIG. 1.

도 4는 도 1에 도시된 반도체 패키지의 회로기판에 반도체 칩들이 적층된 모습을 개략적으로 도시하는 평면도이다.FIG. 4 is a plan view schematically illustrating a semiconductor chip stacked on a circuit board of the semiconductor package illustrated in FIG. 1.

도 5는 도 1에 도시된 반도체 패키지의 다른 실시예에 관한 회로기판에 반도체 칩들이 적층된 모습을 개략적으로 도시하는 평면도이다.5 is a plan view schematically illustrating a semiconductor chip stacked on a circuit board according to another embodiment of the semiconductor package illustrated in FIG. 1.

도 6a 내지 도 6f는 본 발명의 일 실시예에 관한 도 1 내지 도 4에 도시된 반도체 패키지의 제조 방법을 도시하는 도면이다. 6A to 6F illustrate a method of manufacturing the semiconductor package shown in FIGS. 1 to 4 according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 간단한 설명 *Brief description of symbols for the main parts of the drawings

5: 접착제층 10, 12: 회로기판5: adhesive layer 10, 12: circuit board

10c: 솔더 범프(solder bump) 11: 중앙부10c: solder bump 11: center

20,21, 22,23, 24,25: 제1층 반도체 칩쌍20,21, 22,23, 24,25: first layer semiconductor chip pair

30,31, 32,33, 34,35: 제2층 반도체 칩쌍30,31, 32,33, 34,35: second layer semiconductor chip pair

40,41, 42,43, 44,45: 제3층 반도체 칩쌍40, 41, 42, 43, 44, 45: third layer semiconductor chip pair

50: 상부 칩50: upper chip

20a,21a, 22a,23a, 24a,25a, 30a,31a, 32a,33a, 34a,35a, 40a,41a, 42a,43a, 44a,45a, 50a: 전극 패드20a, 21a, 22a, 23a, 24a, 25a, 30a, 31a, 32a, 33a, 34a, 35a, 40a, 41a, 42a, 43a, 44a, 45a, 50a: electrode pad

20b,21b, 22b,23b, 24b,25b, 30b,31b, 32b,33b, 34b,35b, 40b,41b, 42b,43b, 44b,45b, 50b: 금속 와이어20b, 21b, 22b, 23b, 24b, 25b, 30b, 31b, 32b, 33b, 34b, 35b, 40b, 41b, 42b, 43b, 44b, 45b, 50b: metal wire

15a, 15b: 몰딩부15a, 15b: molding part

본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 더 상세하게는 패키지내에 다수의 반도체 칩을 효율적으로 적층할 수 있는 멀티 칩 패키지(Multi-chip package) 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a multi-chip package and a method of manufacturing the same, capable of efficiently stacking a plurality of semiconductor chips in a package.

반도체 패키지는 반도체 칩을 인쇄회로기판(PCB)에 실장하기 위하여 외부로부터 보호하고 전기적으로 연결하기 위하여 반도체 칩을 밀봉하여 만든 패키지이다. The semiconductor package is a package made by sealing a semiconductor chip in order to protect the semiconductor chip from the outside and to electrically connect the semiconductor chip to a printed circuit board (PCB).

반도체 패키지 기술은 초기 삽입형(plated-through) 패키지인 DIP, PGA 형태에서 패키지 크기가 작고 전기적 성능이 우수한 표면실장형(SMT) 패키지인 QFP(quad flat package), SOP(system on package)등으로 발전하여 미세피치 표면실장형 TQFP(tape, TSOP등을 거쳐 발전하고 있다. 이러한 경박단소형 SMT 패키지는 1990년대 중반부터 솔더 플립칩(flip chip)과 SMT 기술의 장점을 결합한 BGA(Ball grid array)형태의 패키지로 발전하였다. 1990년대 후반부터 이러한 BGA 패키지 크기와 전기적 성능을 더욱 개선한 CSP(chip scale package) 형태로 발전하고 있으며, 웨이퍼(wafer) 상태에서 패키지를 구현하는 웨이퍼 레벨 CSP 패키지가 주종을 이루고 있다. 더 나아가 개별 칩 패키지는 MCM(multi-chip module)나 MCP(multi-chip package) 또는 SIP(system in package), SOP(system on package) 형태의 시스템 패키지로 발전하고 있다.Semiconductor package technology has been developed into DIP, an early plated-through package, and PFP, quad flat package (SFP), and system on package (SOP), which have small package size and excellent electrical performance. It is being developed through fine pitch surface mount type TQFP (tape, TSOP, etc.) This thin and small SMT package is a ball grid array (BGA) type combining the advantages of solder flip chip and SMT technology since the mid-1990s. Since the late 1990s, it has evolved into a chip scale package (CSP) that further improves the BGA package size and electrical performance, and a wafer-level CSP package that implements the package in a wafer state is mainly used. Further, individual chip packages are evolving into system packages in the form of multi-chip modules (MCM), multi-chip packages (MCP), system in package (SIP), and system on package (SOP).

상기 시스템 패키지는 하나의 반도체 패키지 안에 여러개의 칩등이 연결되는 형태이다. 이러한 칩간의 연결 및 칩과 회로기판 사이의 연결을 위하여 와이어 본딩(wire bonding), TAB(tape automated bonding) 및 플립칩 방식등이 사용된다.The system package is a type in which several chips and the like are connected in one semiconductor package. Wire bonding, tape automated bonding (TAB), and flip chip methods are used for the connection between the chips and the connection between the chip and the circuit board.

반도체 패키지는 반도체 칩으로의 전력 공급, 전기적인 신호 연결, 열 방출, 외부로부터의 보호하는 기능을 수행한다. 따라서 패키지의 구조 및 설계는 기계적 안정성, 전기적 속도와 안정성, 열 방출 능력 및 신뢰성 등의 성능 요구특성을 만족해야 한다. 특히, 다양한 칩이 적층되어 있는 시스템 패키지에서는 제한된 공간내에서 보다 많은 칩들이 적층되면서도 상호 전기적인 연결 방식이 와이어 본딩에 의하여 칩을 연결할 때에 상호 간섭을 최소화하고 용이하게 연결할 수 있는 구조로 설계되어야 한다.The semiconductor package performs power supply to the semiconductor chip, electrical signal connection, heat dissipation, and protection from the outside. Therefore, the structure and design of the package must satisfy the performance requirements such as mechanical stability, electrical speed and stability, heat dissipation capability and reliability. In particular, in a system package in which various chips are stacked, more chips are stacked in a limited space, but the mutual electrical connection method should be designed to minimize the mutual interference and easily connect the chips when connecting the chips by wire bonding. .

이를 위하여 대한민국 특허공개공보 제2004-0065416호, 제2004-000174호 및 제2004-0027901호에는 많은 칩들이 적층된 반도체 패키지들이 개시되어 있다. 그러나, 제2004-0065416에 개시된 반도체 패키지는 적층될 반도체 칩들의 크기가 같을 때는 스페이서를 사용하여야 하며, 칩의 전극 패드가 외곽에 위치해야만 한다는 구조적 제약이 있다. 제2004-000174호에 개시된 반도체 패키지는 적층될 반도체 칩들의 크기가 비슷할 때에는 적용하기 어려우며 각각의 패키지가 가진 두께로 인해 최종 반도체 패키지의 두께가 두꺼워지는 단점이 있다. 그리고 제2004-0065416호에 개시된 반도체 패키지는 칩의 전극 패드가 칩의 중앙에 위치하는 경우만 적용가능하다는 구조적인 제약이 있다.To this end, Korean Patent Publication Nos. 2004-0065416, 2004-000174, and 2004-0027901 disclose semiconductor packages in which many chips are stacked. However, the semiconductor package disclosed in 2004-0065416 has to use a spacer when the semiconductor chips to be stacked are the same size, and there is a structural constraint that the electrode pads of the chips must be located at the outer side. The semiconductor package disclosed in 2004-000174 is difficult to apply when the sizes of semiconductor chips to be stacked are similar, and the thickness of the final semiconductor package is increased due to the thickness of each package. And there is a structural constraint that the semiconductor package disclosed in 2004-0065416 is applicable only when the electrode pad of the chip is located at the center of the chip.

본 발명은 위와 같은 문제점을 해결하기 위한 것으로서 제한된 공간내에서 비슷한 크기의 많은 칩들을 적층하면서도 본딩 조밀도를 감소시켜 패키지내의 전기적인 연결이 용이한 반도체 패키지 및 그 제조방법을 제공하는 데 그 목적이 있다.The present invention is to solve the above problems and to provide a semiconductor package and a method for manufacturing the same, which facilitates electrical connection in the package by reducing the bonding density while stacking many chips of similar size in a limited space. have.

본 발명은 중앙부가 개방되며, 양면에 배선층이 형성되며, 저면에는 외부와 전기적으로 연결되는 외부 접속 단자를 구비하는 기판; 상기 중앙부를 기준으로 상기 기판의 양측에 각각 실장되며, 상기 기판으로부터 상기 중앙부쪽으로 돌출되도록 실장되는 적어도 한 층의 반도체 칩쌍; 및 상기 적어도 한층의 반도체 칩쌍 중 최상부에 있는 양측의 반도체 칩들을 지지하도록 실장되는 상부 칩을 포함하며, 각층에서의 상기 반도체 칩쌍은 적어도 한 쌍이고, 상기 상부 칩을 제외한 반도체 칩들 중에서 이웃한 반도체 칩들의 본딩(bonding) 영역은 서로 반대 방향으로 형성된 반도체 패키지를 개시한다.The present invention is a substrate having a central portion is open, the wiring layer is formed on both sides, the bottom surface having an external connection terminal electrically connected to the outside; At least one semiconductor chip pair mounted on both sides of the substrate with respect to the center portion and mounted to protrude from the substrate toward the center portion; And an upper chip mounted to support the semiconductor chips on both sides of the at least one semiconductor chip pair, wherein the semiconductor chip pair in each layer is at least one pair, and a neighboring semiconductor chip among the semiconductor chips except the upper chip. Bonding regions of these disclose semiconductor packages formed in opposite directions to each other.

또한, 본 발명의 또 다른 측면에 의하면, 중앙부가 개방되며 양면에 회로패턴이 형성된 기판의 상기 중앙부를 기준으로 상기 기판의 양측에 적어도 한 층의 반도체 칩쌍을 상기 기판으로부터 상기 중앙부쪽으로 돌출되도록 실장하는 단계; 상기 적어도 한 층의 반도체 칩쌍 중 최상부에 있는 양측의 반도체 칩들을 지지하도록 상기 최상부의 반도체 칩쌍위에 상부 칩을 실장하는 단계; 상기 반도체 칩쌍과 상기 기판의 주변부에서 상기 반도체 칩과 상기 기판을 전기적으로 연결하는 단계; 상기 중앙부를 통과하여 상기 반도체 칩과 상기 기판, 그리고 상기 상부 칩과 상기 기판을 전기적으로 연결하는 단계; 및 적어도 상기 전기적으로 연결된 영역을 몰딩(molding)하는 단계를 포함하며, 각 층에서의 상기 반도체 칩쌍은 적어도 한 쌍이고, 상기 상부 칩을 제외한 반도체 칩들 중에서 인접한 반도체 칩들의 본딩 영역은 서로 반대 방향으로 형성된 반도체 패키지 제조 방법이 개시된다.In addition, according to another aspect of the present invention, a center portion is opened and mounting at least one layer of semiconductor chip pair protruding from the substrate toward the center portion on both sides of the substrate with respect to the center portion of the substrate having a circuit pattern formed on both sides step; Mounting an upper chip on the uppermost semiconductor chip pair to support the semiconductor chips on both sides of the at least one layer of the semiconductor chip pair; Electrically connecting the semiconductor chip and the substrate at the periphery of the semiconductor chip pair and the substrate; Electrically connecting the semiconductor chip and the substrate and the upper chip and the substrate through the central portion; And molding at least the electrically connected regions, wherein the semiconductor chip pair in each layer is at least one pair, and bonding regions of adjacent semiconductor chips among the semiconductor chips except the upper chip are in opposite directions to each other. The formed semiconductor package manufacturing method is disclosed.

여기서, 상기 칩들과 상기 기판사이의 전기적인 연결은 와이어 본딩에 의하여 이루어지며, 상기 반도체 칩과 상기 기판 사이의 전기적인 연결부는 상기 기판의 중앙부를 통과하거나 상기 반도체 칩쌍과 상기 기판의 주변부에서 이루어질 수 있다.The electrical connection between the chips and the substrate may be made by wire bonding, and the electrical connection between the semiconductor chip and the substrate may pass through the center portion of the substrate or at the semiconductor chip pair and the periphery of the substrate. have.

이하에서는, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 도시하는 단면도이며, 도 2는 도 1에 도시된 반도체 패키지를 도시하는 사시도이고, 도 3은 도 1에 도시된 반도체 패키지를 도시하는 저면도이며, 도 4는 도 1에 도시된 반도체 패키지의 회로기판에 반도체 칩들이 적층된 모습을 개략적으로 도시하는 평면도이다.1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention, FIG. 2 is a perspective view showing the semiconductor package shown in FIG. 1, and FIG. 3 is a bottom view showing the semiconductor package shown in FIG. 1. 4 is a plan view schematically illustrating a state in which semiconductor chips are stacked on a circuit board of the semiconductor package illustrated in FIG. 1.

도면을 참조하면, 반도체 패키지의 반도체 실장용 회로기판(package substrate, 10)에는 제1층 반도체 칩쌍(20,21,22,23,24,25)이 적층되어 실장되어 있으며, 제1층 반도체 칩쌍(20,21, 22,23, 24,25)에는 제2층 반도체 칩쌍(30,31, 32,33, 34,35)이, 제2층 반도체 칩쌍(30,31, 32,33, 34,35)에는 제3층 반도체 칩쌍(40,41, 42,43, 44,45)이 적층되어 실장되어 있다. 최상부층인 제3층 반도체 칩쌍(40,41, 42,43, 44,45)에는 상부 칩(50)이 실장되어 있다. 도면에는 도시된 세 개층의 반도체 칩쌍은 예시에 불과할 뿐, 본 발명의 보호범위는 이에 한정되지 않음은 물론이다.Referring to the drawings, first layer semiconductor chip pairs 20, 21, 22, 23, 24, and 25 are stacked and mounted on a semiconductor package circuit board 10 of a semiconductor package. The second layer semiconductor chip pairs 30, 31, 32, 33, 34, 35 are formed at (20, 21, 22, 23, 24, 25), and the second layer semiconductor chip pairs 30, 31, 32, 33, 34, 35, the third layer semiconductor chip pairs 40, 41, 42, 43, 44, 45 are stacked and mounted. The upper chip 50 is mounted on the third layer semiconductor chip pairs 40, 41, 42, 43, 44, and 45 as the uppermost layer. The three semiconductor chip pairs shown in the drawings are only examples, and the protection scope of the present invention is not limited thereto.

회로기판(10, 12)에는 소정의 패턴에 따른 배선층(10a, 10b)이 형성되어 있으며, 도면에는 도시되지 않았으나 회로기판(10)의 상면과 그 이면도 비아 홀(via hole) 또는 스루우 홀(through hole)등을 통하여 전기적으로 연결되며, 이면에 형성된 솔더 범프(10c)는 외부와의 전기적인 연결을 수행한다. 회로기판(10)은 도 4에 도시된 바와 같이 중앙부(11)에 넓은 홀(hole)이 형성되어 개방된 형상일 수도 있으며, 도 5에 도시된 바와 같이 완전히 분리된 좌우 양측의 회로기판(12)일 수 있다. 어느 경우이든 전체 회로기판(10,12)의 중앙부(11)는 와이어 본딩을 위한 공간 확보를 위하여 개방되어 있어야 한다. 회로기판(10)은 양면 연성(flexible) PCB, 단면 연성 PCB 및 연성 다층(multi-flexible) PCB등 다양한 회로기판이 사용될 수 있다.The wiring layers 10a and 10b are formed on the circuit boards 10 and 12 according to a predetermined pattern, and although not shown in the drawing, the upper and rear surfaces of the circuit board 10 may also be via holes or through holes. It is electrically connected through a through hole and the like, and the solder bumps 10c formed on the rear surface perform electrical connection with the outside. As shown in FIG. 4, the circuit board 10 may have an open shape in which a wide hole is formed in the center portion 11, and as shown in FIG. 5, the circuit boards 12 on both the left and right sides are completely separated. May be). In any case, the central portion 11 of the entire circuit board 10 and 12 should be open to secure a space for wire bonding. The circuit board 10 may use various circuit boards, such as a double-sided flexible PCB, a single-sided flexible PCB, and a flexible multi-flexible PCB.

회로기판(10,12)의 상면(반도체 칩 형성면)에는 제1층 반도체 칩쌍(20,21, 22,23, 24,25)이 실장되는데, 제1층의 반도체 칩들은 다시 제1 반도체 칩쌍(20,21), 제2 반도체 칩쌍(22,23) 및 제3 반도체 칩쌍(24,25)으로 나뉘어진다. 도 면에는 각층의 반도체 칩쌍이 다시 세 개의 반도체 칩쌍으로 나뉘어지는 것으로 도시되어 있으나, 본 발명의 보호범위는 반드시 이에 한정되지 아니하며, 한 개, 두 개 또는 네 개의 반도체 칩쌍으로 나뉘어지는 것도 포함함은 물론이다. The first layer semiconductor chip pairs 20, 21, 22, 23, 24, and 25 are mounted on the upper surfaces (semiconductor chip formation surfaces) of the circuit boards 10 and 12. The semiconductor chips of the first layer are again the first semiconductor chip pairs. (20,21), the second semiconductor chip pairs 22 and 23, and the third semiconductor chip pairs 24 and 25. In the figure, the semiconductor chip pair of each layer is again divided into three semiconductor chip pairs, but the protection scope of the present invention is not necessarily limited thereto, and includes one, two, or four semiconductor chip pairs. Of course.

상기 제1층 반도체 칩쌍(20,21, 22,23, 24,25)을 이루는 각 반도체 칩들은 회로기판의 중앙부(11)를 기준으로 회로기판(10,12)의 양측에 각각 배치된다. 이 때, 제1 반도체 칩쌍(20,21) 제2 반도체 칩쌍(30,31), 제3 반도체 칩쌍(40,41)은 회로기판(10,12)으로부터 중앙부(11)쪽(내측)으로 약간 돌출되도록 위치되어야 한다. Each of the semiconductor chips constituting the first layer semiconductor chip pairs 20, 21, 22, 23, 24, and 25 is disposed on both sides of the circuit boards 10 and 12 with respect to the central portion 11 of the circuit board. At this time, the first semiconductor chip pairs 20 and 21, the second semiconductor chip pairs 30 and 31, and the third semiconductor chip pairs 40 and 41 are slightly moved from the circuit boards 10 and 12 toward the center portion 11 (inside). It must be positioned to protrude.

이와 유사하게, 제2층 반도체 칩쌍(30,31, 32,33, 34,35)은 회로기판의 중앙부(11)를 기준으로 제1층 반도체 칩쌍(20,21, 22,23, 24,25)에 각각 배치되며, 제4 반도체 칩쌍(30,31) 제5 반도체 칩쌍(32,33), 제6 반도체 칩쌍(34,35)은 각각 제1 반도체 칩쌍(20,21) 제2 반도체 칩쌍(30,31), 제3 반도체 칩쌍(40,41)으로부터 중앙부(11)쪽(내측)으로 약간 돌출되도록 위치되어야 한다. 또한, 제3층 반도체 칩쌍(40,41, 42,43, 44,45)은 회로기판의 중앙부(11)를 기준으로 제2층 반도체 칩쌍(30,31, 32,33, 34,35)에 각각 배치되며, 제7 반도체 칩쌍(40,41) 제8 반도체 칩쌍(42,43), 제9 반도체 칩쌍(44,45)은 각각 제4 반도체 칩쌍(30,31) 제5 반도체 칩쌍(32,33), 제6 반도체 칩쌍(34,35)으로부터 중앙부(11)쪽(내측)으로 약간 돌출되도록 위치되어야 한다.Similarly, the second layer semiconductor chip pairs 30, 31, 32, 33, 34, and 35 are formed of the first layer semiconductor chip pairs 20, 21, 22, 23, 24, and 25 based on the center portion 11 of the circuit board. And the fourth semiconductor chip pairs 30 and 31, the fifth semiconductor chip pairs 32 and 33, and the sixth semiconductor chip pairs 34 and 35, respectively, include the first semiconductor chip pairs 20 and 21 and the second semiconductor chip pairs ( 30 and 31, so as to protrude slightly from the third semiconductor chip pairs 40 and 41 toward the center portion 11 (inner side). In addition, the third layer semiconductor chip pairs 40, 41, 42, 43, 44, and 45 are connected to the second layer semiconductor chip pairs 30, 31, 32, 33, 34, and 35 based on the center portion 11 of the circuit board. The seventh semiconductor chip pairs 40 and 41, the eighth semiconductor chip pairs 42 and 43, and the ninth semiconductor chip pairs 44 and 45, respectively, include the fourth semiconductor chip pair 30 and 31 and the fifth semiconductor chip pair 32, respectively. 33), it should be positioned so as to project slightly from the sixth semiconductor chip pair 34,35 toward the center portion 11 (inside).

최상부층에는 제3층 반도체 칩쌍(40,41, 42,43, 44,45)에 모두 걸치도록 회로기판의 중앙부(11)에 대응하는 위치에 상부 칩(50)이 실장되어 있다. 상부 칩 (50)의 일 실시예로서 칩(50)의 중앙 하부에 전극 패드(50a)가 구비되는 반도체 칩일 수 있다. 다른 실시예로서 상부 칩(50)은 별도의 전기소자는 형성되어 있지 않고 열 방출을 확산시키는 열 방출 부재일 수 있다. 또 다른 실시예로서 상부 칩(50)은 별도의 전기소자는 형성되어 있지 않으며, 반도체 칩쌍을 지지하기 위한 용도의 연결용 칩일 수 있다. 또 다른 실시예로서 상부 칩(50)은 칩의 중앙 하부에 전극 패드가 구비되는 반도체 칩과 상기 반도체 칩상에 형성되는 열 방출 부재가 적층된 칩일 수도 있다.The upper chip 50 is mounted on the uppermost layer at a position corresponding to the central portion 11 of the circuit board so as to span all the third layer semiconductor chip pairs 40, 41, 42, 43, 44, 45. As an exemplary embodiment of the upper chip 50, the semiconductor chip may include a semiconductor pad having an electrode pad 50a disposed under the center of the chip 50. In another embodiment, the upper chip 50 may be a heat dissipation member that does not have a separate electric element and diffuses heat dissipation. In another embodiment, the upper chip 50 is not provided with a separate electric element, and may be a connection chip for supporting a semiconductor chip pair. In another embodiment, the upper chip 50 may be a chip in which a semiconductor chip including an electrode pad is disposed below the center of the chip, and a heat dissipation member formed on the semiconductor chip.

여기서, 돌출되어야 하는 길이는 반도체 칩(30,31)의 저면에 형성된 전극 패드(30a,31a)에 와이어 본딩이 수행될 수 있을 정도의 여유를 갖는 거리인 것이 바람직하다. 제1층 반도체 칩쌍(20,21, 22,23, 24,25)과 회로기판(10) 사이에는 접착제층(5)이 개재되는데, 접착제층(5)은 제1층 반도체 칩쌍(20,21, 22,23, 24,25)을 회로기판(10)에 실장하기 위한 것으로서 필름형 접착제나 액상 접착제 등 다양한 주지(well known)의 수단이 사용될 수 있다. 이와 유사하게, 제1층 반도체 칩쌍(20,21, 22,23, 24,25)과 제2층 반도체 칩쌍(30,31, 32,33, 34,35)의 사이에도 접착을 위한 접착제층(5)이 개재되어 있으며, 제2층 반도체 칩쌍(30,31, 32,33, 34,35)과 제3층 반도체 칩쌍(40,41, 42,43, 44,45)의 사이에도 접착제층(5)이 개재되어 있다. Here, the length to be protruded is preferably a distance having a margin sufficient for wire bonding to the electrode pads 30a and 31a formed on the bottom surfaces of the semiconductor chips 30 and 31. An adhesive layer 5 is interposed between the first layer semiconductor chip pairs 20, 21, 22, 23, 24, 25 and the circuit board 10, and the adhesive layer 5 is formed of the first layer semiconductor chip pairs 20, 21. , 22, 23, 24, 25 to mount the circuit board 10, a variety of well-known means such as a film adhesive or a liquid adhesive may be used. Similarly, the adhesive layer for adhesion between the first layer semiconductor chip pairs 20, 21, 22, 23, 24, 25 and the second layer semiconductor chip pairs 30, 31, 32, 33, 34, 35 ( 5) is interposed therebetween, and an adhesive layer (B) between the second layer semiconductor chip pairs 30, 31, 32, 33, 34, 35 and the third layer semiconductor chip pairs 40, 41, 42, 43, 44, 45. 5) is interposed.

이와 같이, 각 층의 반도체 칩(20,21,23,24,25,26 30,31,32,33,34,35, 40,41,42,43,44,45)은 하부에 있는 기판(10,12) 또는 반도체 칩쌍으로부터 중앙부(11)쪽으로 돌출되도록 적층되기 때문에 반도체 칩의 크기가 동일한 경우에도 와이 어 본딩되는 본딩 영역 즉, 전극 패드(20a,21a, 22a,23a, 24a,25a, 30a,31a, 32a,33a, 34a,35a, 40a,41a, 42a,43a, 44a,45a)가 노출될 수 있다. 따라서, 반도체 칩(20,21,30,31,40,41)의 크기에 상관없이 적층이 가능한 장점이 있다. 또한, 각각의 반도체 칩을 둘러싸는 패키지가 적층되는 방식이 아니라 각각의 반도체 칩(20,21,23,24,25,26 30,31,32,33,34,35, 40,41,42,43,44,45) 자체가 적층되는 방식이므로 다층 적층에 따른 두께의 증가가 많지 않아서 최종 패키지의 두께를 얇게 할 수 있다. 뿐만 아니라, 상부로 올라갈수록 내측으로 돌출되도록 적층된 구조에 의하여 생긴 중앙부(11) 공간(cavity)이 존재하게 되어 냉각 효율이 증대될 수 있다.As such, the semiconductor chips 20, 21, 23, 24, 25, 26 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, and 45 of each layer are formed on the lower substrate ( 10, 12 or the semiconductor chip pairs are stacked so as to protrude toward the center portion 11, even when the size of the semiconductor chip is the same bonding area that is wire-bonded, that is, electrode pads 20a, 21a, 22a, 23a, 24a, 25a, 30a , 31a, 32a, 33a, 34a, 35a, 40a, 41a, 42a, 43a, 44a, 45a may be exposed. Therefore, there is an advantage in that stacking is possible regardless of the size of the semiconductor chips 20, 21, 30, 31, 40, and 41. In addition, the semiconductor chip 20, 21, 23, 24, 25, 26 30, 31, 32, 33, 34, 35, 40, 41, 42, 43,44,45) because the stack itself is not much increase in thickness due to the multi-layer stack can be thinned the final package thickness. In addition, there is a cavity (11) formed by the stacked structure so as to protrude inward as the upper portion is raised, the cooling efficiency can be increased.

회로기판(10,12)의 상면 배선층(10a) 또는 하면 배선층(10b)과 반도체 칩의 전극 패드(20a,21a, 22a,23a, 24a,25a, 30a,31a, 32a,33a, 34a,35a, 40a,41a, 42a,43a, 44a,45a)는 와이어 본딩에 의하여 전기적으로 연결이 되어 있다. 이를 위하여, 각 반도체 칩의 전극 패드(20a,21a, 22a,23a, 24a,25a, 30a,31a, 32a,33a, 34a,35a, 40a,41a, 42a,43a, 44a,45a)는 적층을 위해 접촉되는 영역이 아닌 영역에 형성되어 있다. 그리고, 상부 칩을 제외한 반도체 칩들 중에서 인접한 반도체 칩들의 본딩 영역은 서로 반대 방향으로 형성되어 있다.The upper wiring layer 10a or the lower wiring layer 10b of the circuit boards 10 and 12 and the electrode pads 20a, 21a, 22a, 23a, 24a, 25a, 30a, 31a, 32a, 33a, 34a, 35a, 40a, 41a, 42a, 43a, 44a, 45a are electrically connected by wire bonding. To this end, the electrode pads 20a, 21a, 22a, 23a, 24a, 25a, 30a, 31a, 32a, 33a, 34a, 35a, 40a, 41a, 42a, 43a, 44a, 45a of each semiconductor chip are used for stacking. It is formed in a region other than the region in contact. The bonding regions of adjacent semiconductor chips among the semiconductor chips except the upper chip are formed in opposite directions.

예를 들면, 제1 반도체 칩쌍(20,21)의 경우 각각 좌측과 우측의 상면에 전극 패드(20a,21a)가 형성되며, 상기 제1 반도체 칩쌍(20,21)과 인접한 제2 반도체 칩쌍(22,23)의 경우 각각 우측과 좌측의 하면에 전극 패드(22a,23a)가 형성되어 있다. 또한, 상부 방향으로 상기 제1 반도체 칩쌍(20,21)과 인접한 제4 반도체 칩쌍 (30,31)의 경우 각각 우측과 좌측의 하면에 전극 패드(30a,31a)가 형성되어 있다. 한편, 최상부의 상부 칩(50)의 중앙 하부에 전극 패드(50a)가 형성되어 있다. For example, in the case of the first semiconductor chip pairs 20 and 21, electrode pads 20a and 21a are formed on upper and left surfaces of the first and second semiconductor chip pairs 20 and 21, respectively. In the case of 22 and 23, electrode pads 22a and 23a are formed on the lower surfaces of the right side and the left side, respectively. In the case of the fourth semiconductor chip pairs 30 and 31 adjacent to the first semiconductor chip pairs 20 and 21 in the upward direction, electrode pads 30a and 31a are formed on the lower surfaces of the right and left sides, respectively. On the other hand, the electrode pad 50a is formed in the center lower part of the upper chip 50 of the uppermost part.

와이어 본딩 영역을 상기한 바와 같이 배치시킴으로써, 본딩 간격을 확보하여 용이하게 와이어 본딩을 수행할 수 있다. 즉, 상대적으로 많은 칩들을 적층하면서도 와이어 본딩 밀집도를 절반으로 줄여서 와이어 본딩을 용이하게 하고 전기적인 단락(short)을 방지할 수 있다.By arranging the wire bonding regions as described above, the bonding interval can be secured and wire bonding can be easily performed. That is, while stacking a relatively large number of chips, the wire bonding density can be reduced by half to facilitate wire bonding and prevent electrical shorts.

한편, 제2 반도체 칩쌍(22,23), 제4 반도체 칩쌍(30,31), 제6 반도체 칩쌍(34,35), 제8 반도체 칩쌍(42,43) 및 상부 칩(50)의 본딩 영역은 중앙부를 향하도록 형성되어 있으므로 이들 반도체 칩과 회로기판(10,12)사이의 와이어 본딩은 기기판의 중앙부(11)를 통과하여 이루어진다. 그리고, 제1 반도체 칩쌍(20,21), 제3 반도체 칩쌍(24,25), 제5 반도체 칩쌍(32,33), 제7 반도체 칩쌍(40,41) 및 제9 반도체 칩쌍(44,45)의 본딩 영역은 이들 반도체 칩과 기판의 주변부를 향하도록 형성되어 있으므로 이들 반도체 칩과 회로기판(10,12)사이의 와이어 본딩은 기판의 상방 주변부에서 이루어진다.Bonding regions of the second semiconductor chip pairs 22 and 23, the fourth semiconductor chip pairs 30 and 31, the sixth semiconductor chip pairs 34 and 35, the eighth semiconductor chip pairs 42 and 43, and the upper chip 50, respectively. Is formed so as to face the center portion, the wire bonding between these semiconductor chips and the circuit boards 10 and 12 passes through the center portion 11 of the device substrate. The first semiconductor chip pair 20, 21, the third semiconductor chip pair 24, 25, the fifth semiconductor chip pair 32, 33, the seventh semiconductor chip pair 40, 41, and the ninth semiconductor chip pair 44, 45. Since the bonding region of () is formed toward the periphery of these semiconductor chips and the substrate, the wire bonding between these semiconductor chips and the circuit boards 10, 12 is made in the upper peripheral portion of the substrate.

상기한 대로 각 층의 반도체 칩쌍(20,21,22,23,24,25, 30,31,32,33,34,35, 40,41,42,43,44,45)과 회로기판(10, 12) 사이의 일정한 수의 금속 와이어가 중앙부(11)를 통과하여 이루어짐과 동시에 반도체 칩과 회로기판(10, 12)의 주변부에서도 이루어지므로 중앙부(11)만 통과하여 이루어지는 종래의 반도체 패키지와 비교하였을 때, 와이어 본딩의 밀집도를 줄이고 와이어 간의 상호간섭을 최소화함으로써 본딩 간격의 확보가 용이한 장점이 있다.As described above, the semiconductor chip pairs 20, 21, 22, 23, 24, 25, 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, 45 and the circuit board 10 of each layer. , 12) a certain number of metal wires are passed through the central portion 11 and also at the periphery of the semiconductor chip and the circuit board 10, 12, compared to the conventional semiconductor package that passes through the central portion 11 only. When doing so, it is easy to secure the bonding gap by reducing the density of wire bonding and minimizing mutual interference between wires.

중앙부(11)와 주변부를 통과하는 와이어의 주위에는 외부의 충격등으로부터 보호하기 위하여 수지 몰딩(15a,15b)이 되어 있다. 그리고, 비아 홀을 통하여 회로기판(10, 12)의 상면에 형성된 배선층(10b)과 전기적으로 연결되는 솔더 범프(10c)가 회로기판(10)의 저면에 형성되어 있다. 솔더 범프(10c)는 반도체 패키지의 외부 접속 단자로서 외부로부터의 전력을 공급받거나 반도체 패키지와 외부와의 전기적인 신호를 전달하는 통로가 된다. 도면에서는 외부 접속 단자로서 솔더 범프(10c)를 구비하는 BGA 타입을 예시하고 있으나, 본 발명의 보호범위는 이에 한정되지 아니하며, 핀을 구비하는 PGA(pin grid array)등 여러 가지 다양한 유형도 포함할 수 있다.Resin moldings 15a and 15b are provided around the wire passing through the central portion 11 and the periphery to protect against external shocks and the like. A solder bump 10c electrically connected to the wiring layer 10b formed on the upper surfaces of the circuit boards 10 and 12 through the via hole is formed on the bottom surface of the circuit board 10. The solder bump 10c is an external connection terminal of the semiconductor package and serves as a path for receiving electric power from the outside or for transmitting an electrical signal between the semiconductor package and the outside. Although the drawings illustrate a BGA type having a solder bump 10c as an external connection terminal, the protection scope of the present invention is not limited thereto and may include various types such as a pin grid array (PGA) having pins. Can be.

이하에서는, 도 6a 내지 도 6f를 참조하여 상기한 바와 같은 구성의 반도체 패키지의 제조 방법에 대하여 설명한다.Hereinafter, the manufacturing method of the semiconductor package of the above structure is demonstrated with reference to FIGS. 6A-6F.

여러 반도체 칩들이 적층되고 와이어 본딩된 후 몰딩되는 반도체 패키지의 제조 이전에 상기 반도체 패키지에 적층될 각 반도체 칩이 만들어 져야 한다. 웨이퍼로부터 개별의 반도체 칩(20,21,22,23,24,25, 30,31,32,33,34,35, 40,41,42,43,44,45)을 만드는 공정에 관하여는 여러 가지 다양한 방법이 공지되어 있으므로 여기에서 별도의 설명은 생략한다.Each semiconductor chip to be laminated to the semiconductor package must be made before fabrication of a semiconductor package in which several semiconductor chips are stacked, wire bonded and then molded. For the process of making individual semiconductor chips 20, 21, 22, 23, 24, 25, 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, 45 from the wafer, Since various methods are known, a separate description is omitted here.

도 6a에 도시된 바와 같이, 소정 패턴의 배선층이 형성된 회로기판(10)상에 제1 반도체 칩쌍(20,21), 제2 반도체 칩쌍(22,23) 및 제3 반도체 칩쌍(24,25)을 순차적으로 실장한다. 이 때, 제1 반도체 칩쌍(20,21), 제2 반도체 칩쌍(22,23) 및 제3 반도체 칩쌍(24,25)은 회로기판(10)으로부터 중앙부쪽으로 소정거리 돌출되도 록 실장된다. 실장면에는 회로기판(10)과 각 반도체 칩쌍(20,21, 22,23, 24,25)의 접착을 위한 접착제층(5)이 형성된다. 제1층 반도체 칩쌍(20,21, 22,23, 24,25)의 실장이 완료된 후, 제2층 반도체 칩쌍(30,31, 32,33, 34,35) 및 제3층 반도체 칩쌍(40,41, 42,43, 44,45)을 계단형으로 순차적으로 실장한다. 마찬가지로 각 실장면에는 접착제층(5)이 개재되어 있다. 이렇게 계단식으로 실장됨으로써 와이어 본딩을 위한 본딩 영역이 노출된다. As shown in FIG. 6A, the first semiconductor chip pairs 20 and 21, the second semiconductor chip pairs 22 and 23, and the third semiconductor chip pairs 24 and 25 are formed on a circuit board 10 on which a wiring layer of a predetermined pattern is formed. Are implemented sequentially. In this case, the first semiconductor chip pairs 20 and 21, the second semiconductor chip pairs 22 and 23, and the third semiconductor chip pairs 24 and 25 are mounted to protrude a predetermined distance from the circuit board 10 toward the center portion. On the mounting surface, an adhesive layer 5 for bonding the circuit board 10 and each semiconductor chip pair 20, 21, 22, 23, 24, 25 is formed. After the mounting of the first layer semiconductor chip pairs 20, 21, 22, 23, 24, 25 is completed, the second layer semiconductor chip pairs 30, 31, 32, 33, 34, 35 and the third layer semiconductor chip pair 40 , 41, 42, 43, 44, 45 are sequentially mounted in a stepped manner. Similarly, the adhesive bond layer 5 is interposed in each mounting surface. This stepwise mounting exposes the bonding area for wire bonding.

도 6b에 도시된 바와 같이, 제3층 반도체 칩쌍(40,41, 42,43, 44,45) 위에는 상부 칩(50)이 실장된다. 상부 칩(50)은 접착제층(5)에 의하여 좌측과 우측의 제3층 반도체 칩쌍(40,41, 42,43, 44,45)을 고정시킴으로써 각 반도체 칩들이 내측으로 쏠리지 않고 지지될 수 있도록 하는 역할을 수행한다. 이 때 상부 칩(50)은 전극 패드(50a)가 없거나 중앙 하부에 있는 것을 사용하는 것이 바람직하다.As shown in FIG. 6B, the upper chip 50 is mounted on the third layer semiconductor chip pairs 40, 41, 42, 43, 44, and 45. The upper chip 50 fixes the left and right third layer semiconductor chip pairs 40, 41, 42, 43, 44, and 45 by the adhesive layer 5 so that each semiconductor chip can be supported without being inwardly moved. It plays a role. At this time, the upper chip 50 is preferably used without the electrode pad (50a) or in the lower center.

도 6c에 도시된 바와 같이, 각 반도체 칩의 전극 패드(20a,21a,24a,25a, 32a,33a, 40a,41a,44a,45a)와 회로기판의 본딩 영역(10a) 사이의 와이어 본딩은 반도체 칩들과 회로기판(10)의 주변부에서 이루어진다. 와이어 본딩 방법을 예시하면, 각 반도체 칩의 전극 패드(20a,21a,24a,25a, 32a,33a, 40a,41a,44a,45a)상에 볼 본딩을 행하고, 볼 본딩으로부터 금속 와이어(20b,21b,24b,25b, 32b,33b, 40b,41b,44b,45b)를 연장시켜 회로기판(10)상에 형성된 배선층(10a)에 웨지(wedge) 본딩을 행한다. 이 때, 와이어 본딩되는 순서는 특별히 정해진 것은 아니며, 와이어 본딩시 서로 간섭받지 않도록 순차적으로 행하면 된다.As shown in FIG. 6C, the wire bonding between the electrode pads 20a, 21a, 24a, 25a, 32a, 33a, 40a, 41a, 44a, 45a of each semiconductor chip and the bonding region 10a of the circuit board is performed by a semiconductor. Chips and the peripheral portion of the circuit board 10 is made. To illustrate the wire bonding method, ball bonding is performed on the electrode pads 20a, 21a, 24a, 25a, 32a, 33a, 40a, 41a, 44a, 45a of each semiconductor chip, and metal wires 20b, 21b are formed from the ball bonding. And 24b, 25b, 32b, 33b, 40b, 41b, 44b, and 45b are extended to wedge bonding to the wiring layer 10a formed on the circuit board 10. At this time, the order of wire bonding is not particularly determined, and may be sequentially performed so as not to interfere with each other during wire bonding.

도 6d에 도시된 바와 같이, 각 반도체 칩의 전극 패드(30a,31a, 22a,23a,42a,43a, 34a,35a)와 회로기판의 본딩 영역(10b)사이의 와이어 본딩은 회로기판의 중앙부(11)를 통과하는 금속와이어(30b,31b, 22b,23b,42b,43b, 34b,35b)에 의하여 이루어진다. 이 때, 중앙부(11)를 통과하는 와이어 본딩과 주변부에서의 와이어 본딩간에 특별히 순서가 정해진 것은 아니지만, 중앙부(11)를 통과하는 와이어 본딩을 하기 위하여는 회로기판(10)에 실장된 반도체 칩들을 뒤집어야 하기 때문에 중앙부(11)부터 와이어 본딩을 수행하는 편이 유리하다.As shown in FIG. 6D, the wire bonding between the electrode pads 30a, 31a, 22a, 23a, 42a, 43a, 34a, 35a of each semiconductor chip and the bonding region 10b of the circuit board is performed at the center portion of the circuit board ( 11) made of metal wires 30b, 31b, 22b, 23b, 42b, 43b, 34b, 35b passing through. At this time, the order between the wire bonding passing through the center portion 11 and the wire bonding at the periphery portion is not particularly specified, but in order to perform wire bonding passing through the center portion 11, semiconductor chips mounted on the circuit board 10 may be used. It is advantageous to perform wire bonding from the center portion 11 since it must be flipped over.

상기한 바와 같이 회로기판(10)상에 각 층의 반도체 칩쌍(20,21,22,23,24,25 30,31,32,33,34,35, 40,41,42,43,44,45, 50)을 순차적으로 실장하고 와이어 본딩한 후에는 도 6e에 도시된 바와 같이, 와이어 본딩된 부분등을 수지 몰딩(15a,15b)등으로 밀봉한다. 몰딩을 행함으로써 외부로부터 반도체 칩(20,21,22,23,24,25 30,31,32,33,34,35, 40,41,42,43,44,45, 50)과 와이어 본딩부를 보호하고 열 방출을 촉진시키며, 취급을 용이하게 해준다.As described above, the semiconductor chip pairs 20, 21, 22, 23, 24, 25, 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, of each layer on the circuit board 10, 45 and 50 are sequentially mounted and wire-bonded, the wire-bonded portion and the like are sealed with resin moldings 15a and 15b as shown in FIG. 6E. By molding, the semiconductor chips 20, 21, 22, 23, 24, 25 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, 45, 50 and the wire bonding portion are Protect, promote heat dissipation, and facilitate handling.

마지막으로 도 6f에 도시된 바와 같이, 회로기판(10)의 저면에는 반도체 패키지를 외부와 전기적으로 연결시키도록 외부 접속 단자(10c)가 형성된다. 외부 접속 단자의 일 실시예인 솔더 범프(10c)를 형성하는 방법은 진공증착(evaporation) 방법, 전기도금(electroplating) 방법, 프린팅(printing) 방법 및 솔더 볼(solder ball) 배치 방법 등이 사용될 수 있다. 도면에는 솔더 범프(10c)를 사용하는 BGA(ball grid array) 타입의 반도체 패키지가 도시되어 있으나, 본 발명의 보호범위는 이에 한정되지 아니하며, PGA(pin grid array) 타입 등 다양한 반도체 패키지도 포함함은 물론이다.Finally, as shown in FIG. 6F, an external connection terminal 10c is formed on the bottom of the circuit board 10 to electrically connect the semiconductor package to the outside. As a method of forming the solder bump 10c as an embodiment of the external connection terminal, an evaporation method, an electroplating method, a printing method, a solder ball placement method, or the like may be used. . The drawing shows a ball grid array (BGA) type semiconductor package using solder bumps 10c, but the protection scope of the present invention is not limited thereto, and also includes various semiconductor packages such as a pin grid array (PGA) type. Of course.

상기한 제조 방법에 의하면, 반도체 패키지의 저면 중앙부(11)에 캐비티(cavity)가 형성되어 있어서 냉각 효율이 증대된다. 또한, 상부로 올라갈수록 내측으로 돌출되도록 적층된 구조에 의하여 생긴 중앙부(11) 공간을 이용하여 와이어 본딩이 이루어지기 때문에 반도체 칩들의 크기에 상관없이 적층할 수 있다. 뿐만 아니라, 일부의 반도체 칩쌍(30,31, 22,23,42,43, 34,35)과 회로기판(10) 사이의 와이어 본딩은 중앙부(11)를 통과하여 이루어지며, 나머지 반도체 칩쌍(20,21,40,41, 32,33, 24,25,44,45)과 회로기판(10) 사이의 와이어 본딩은 주변부에서 이루어진다. 따라서, 와이어 본딩이 중앙부(11)만 통과하여 이루어지는 반도체 패키지와 비교하였을 때, 와이어 본딩의 밀집도를 줄이고 와이어의 상호 간섭을 최소화함으로써 본딩 간격의 확보가 용이한 장점이 있다. According to the above-mentioned manufacturing method, a cavity is formed in the bottom center part 11 of a semiconductor package, and cooling efficiency increases. In addition, since the wire bonding is performed by using the space of the center portion 11 formed by the stacked structure so as to protrude inwards, the semiconductor chips can be stacked regardless of the size of the semiconductor chips. In addition, wire bonding between some of the semiconductor chip pairs 30, 31, 22, 23, 42, 43, 34, 35 and the circuit board 10 is performed through the central portion 11, and the remaining semiconductor chip pairs 20 The wire bonding between, 21, 40, 41, 32, 33, 24, 25, 44, 45 and the circuit board 10 is performed at the periphery. Therefore, compared with the semiconductor package in which the wire bonding passes through only the center portion 11, the bonding gap is easily secured by reducing the density of wire bonding and minimizing mutual interference of the wires.

그리고, 종래에 동일한 크기의 반도체 칩을 적층하여 만든 반도체 패키지의 경우, 반도체 칩(20,21,22,23,24,25 30,31,32,33,34,35, 40,41,42,43,44,45, 50)을 적층할 때마다 회로기판(10)과 반도체 칩간에 와이어 본딩을 수행하여야만 했다. 그런데, 와이어 본딩을 수행하기 전에는 와이어 본딩 장치를 정렬하는 작업이 수반되어야 하는바, 반도체 칩을 적층할 때마다 와이어 본딩을 수행하는 종래 방식에서는 와이어 본딩 때마다 정렬하는 작업을 하여야만 했다. 그런데, 본 발명은 동일한 크기의 반도체 칩(20,21,22,23,24,25 30,31,32,33,34,35, 40,41,42,43,44,45, 50)을 적층하더라도 와이어 본딩 영역의 노출되므로 모든 반도체 칩(20,21,22,23,24,25 30,31,32,33,34,35, 40,41,42,43,44,45, 50)을 적층한 후에 각 반도체 칩(20,21,22,23,24,25 30,31,32,33,34,35, 40,41,42,43,44,45, 50)과 회로 기판(10) 사이의 와이어 본딩을 동일한 공정에서 수행하므로 와이어 본딩 장치 정렬 작업에 소요되는 시간 및 공정을 줄일 수 있는 효과가 있다.In the case of a semiconductor package formed by stacking semiconductor chips of the same size in the related art, the semiconductor chips 20, 21, 22, 23, 24, 25 30, 31, 32, 33, 34, 35, 40, 41, 42, Each time 43, 44, 45, and 50 were stacked, wire bonding between the circuit board 10 and the semiconductor chip had to be performed. However, before the wire bonding is performed, the operation of aligning the wire bonding apparatus has to be accompanied. In the conventional method of performing wire bonding every time the semiconductor chips are stacked, the operation has to be performed every time the wire bonding is performed. However, the present invention stacks semiconductor chips 20, 21, 22, 23, 24, 25, 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, 45 and 50 of the same size. Even though the wire bonding area is exposed, all the semiconductor chips 20, 21, 22, 23, 24, 25 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, 45, 50 are stacked. After each semiconductor chip (20, 21, 22, 23, 24, 25 30, 31, 32, 33, 34, 35, 40, 41, 42, 43, 44, 45, 50) between the circuit board 10 Since wire bonding is performed in the same process, it is possible to reduce the time and process required for wire bonding device alignment.

상기 설명한 멀티 칩 패키지 및 그 제조방법은 멀티 칩 패키지(MCP)에만 적용될 수 있는 것은 아니며, SIP 및 SOP등의 시스템 패키지에도 적용될 수 있다.The above-described multichip package and a method of manufacturing the same may not be applied only to a multichip package (MCP), but may also be applied to system packages such as SIP and SOP.

본 발명의 반도체 패지지 및 그 제조 방법은 제한된 공간내에 비슷한 크기의 많은 칩들을 적층하면서도 와이어 본딩의 조밀도를 낮추며, 냉각 효율을 증대시킬 수 있다.The semiconductor package of the present invention and a method of manufacturing the same can reduce the density of wire bonding and increase the cooling efficiency while stacking many chips of similar size in a limited space.

본 발명은 도면에 도시된 실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 본 기술 분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 다른 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호 범위는 첨부된 특허청구범위의 기술적 사상에 의하여 정해져야 할 것이다.Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (10)

중앙부가 개방되며, 양면에 배선층이 형성되며, 저면에는 외부와 전기적으로 연결되는 외부 접속 단자를 구비하는 기판;A substrate having a central portion open, wiring layers formed on both surfaces thereof, and a bottom surface having an external connection terminal electrically connected to the outside; 상기 중앙부를 기준으로 상기 기판의 양측에 각각 실장되며, 상기 기판으로부터 상기 중앙부쪽으로 돌출되도록 실장되는 적어도 한 층의 반도체 칩쌍; 및At least one semiconductor chip pair mounted on both sides of the substrate with respect to the center portion and mounted to protrude from the substrate toward the center portion; And 상기 적어도 한층의 반도체 칩쌍 중 최상부에 있는 양측의 반도체 칩들을 지지하도록 실장되는 상부 칩을 포함하며,An upper chip mounted to support semiconductor chips on both sides of the at least one pair of semiconductor chips; 각층에서의 상기 반도체 칩쌍은 적어도 한 쌍이고, 상기 상부 칩을 제외한 반도체 칩들 중에서 이웃한 반도체 칩들의 본딩(bonding) 영역은 서로 반대 방향으로 형성되며,The semiconductor chip pair in each layer is at least one pair, and bonding regions of neighboring semiconductor chips among the semiconductor chips except the upper chip are formed in opposite directions, 상기 상부 칩은 적어도 칩의 하부에 전극 패드를 구비하는 반도체 칩, 및 상기 반도체 칩 위에 부착되며 열 방출을 확산시키는 열 방출 부재를 구비하는 반도체 패키지.And the upper chip includes a semiconductor chip having an electrode pad at least under the chip, and a heat dissipation member attached to the semiconductor chip and diffusing heat dissipation. 제 1항에 있어서,The method of claim 1, 상기 반도체 칩쌍이 복수층의 반도체 칩쌍인 경우, 상부층의 반도체 칩쌍은 하부층의 반도체 칩쌍으로부터 상기 중앙부쪽으로 돌출되도록 실장되는 반도체 패키지.When the semiconductor chip pair is a plurality of semiconductor chip pair, the semiconductor chip pair of the upper layer is mounted so as to protrude toward the center portion from the semiconductor chip pair of the lower layer. 제 1항에 있어서,The method of claim 1, 상기 칩들과 상기 기판사이의 전기적인 연결은 와이어 본딩에 의하여 이루어지며, 상기 반도체 칩과 상기 기판 사이의 전기적인 연결부는 상기 기판의 중앙부 를 통과하거나 상기 반도체 칩쌍과 상기 기판의 주변부에서 이루어지는 반도체 패키지.The electrical connection between the chips and the substrate is made by wire bonding, and the electrical connection between the semiconductor chip and the substrate passes through the center portion of the substrate or at the semiconductor chip pair and the periphery of the substrate. 삭제delete 삭제delete 중앙부가 개방되며 양면에 회로패턴이 형성된 기판의 상기 중앙부를 기준으로 상기 기판의 양측에 적어도 한 층의 반도체 칩쌍을 상기 기판으로부터 상기 중앙부쪽으로 돌출되도록 실장하는 단계;Mounting at least one layer of semiconductor chip pairs on both sides of the substrate to protrude from the substrate toward the central portion with respect to the central portion of the substrate having a central portion and a circuit pattern formed on both surfaces thereof; 상기 적어도 한 층의 반도체 칩쌍 중 최상부에 있는 양측의 반도체 칩들을 지지하도록 상기 최상부의 반도체 칩쌍위에 상부 칩을 실장하는 단계;Mounting an upper chip on the uppermost semiconductor chip pair to support the semiconductor chips on both sides of the at least one layer of the semiconductor chip pair; 상기 반도체 칩쌍과 상기 기판의 주변부에서 상기 반도체 칩과 상기 기판을 전기적으로 연결하는 단계;Electrically connecting the semiconductor chip and the substrate at the periphery of the semiconductor chip pair and the substrate; 상기 중앙부를 통과하여 상기 반도체 칩과 상기 기판, 그리고 상기 상부 칩과 상기 기판을 전기적으로 연결하는 단계; 및Electrically connecting the semiconductor chip and the substrate and the upper chip and the substrate through the central portion; And 적어도 상기 전기적으로 연결된 영역을 몰딩(molding)하는 단계를 포함하며,Molding at least the electrically connected region, 각 층에서의 상기 반도체 칩쌍은 적어도 한 쌍이고, 상기 상부 칩을 제외한 반도체 칩들 중에서 인접한 반도체 칩들의 본딩 영역은 서로 반대 방향으로 형성되며,The semiconductor chip pair in each layer is at least one pair, and bonding regions of adjacent semiconductor chips among the semiconductor chips except the upper chip are formed in opposite directions, 상기 상부 칩은 적어도 칩의 하부에 전극 패드를 구비하는 반도체 칩 및 상기 반도체 칩 위에 부착되며 열 방출을 확산시키는 열 방출 부재를 구비하는 반도체 패키지 제조 방법.And the upper chip comprises a semiconductor chip having an electrode pad at least under the chip and a heat dissipation member attached to the semiconductor chip and diffusing heat dissipation. 제 6항에 있어서,The method of claim 6, 상기 상부 칩과 상기 기판사이의 전기적인 연결부는 적어도 상기 기판의 중앙부를 통과하며, 상기 반도체 칩과 상기 기판 사이의 전기적인 연결부는 상기 기판의 중앙부를 통과하거나 상기 반도체 칩쌍과 상기 기판의 주변부에서 이루어지는 반도체 패키지 제조 방법.The electrical connection between the upper chip and the substrate passes through at least the central portion of the substrate, and the electrical connection between the semiconductor chip and the substrate passes through the central portion of the substrate or at the periphery of the pair of semiconductor chips and the substrate. Semiconductor package manufacturing method. 삭제delete 삭제delete 삭제delete
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US20020127775A1 (en) * 1999-12-23 2002-09-12 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US20040016999A1 (en) * 2002-07-29 2004-01-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

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US20020127775A1 (en) * 1999-12-23 2002-09-12 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US20040016999A1 (en) * 2002-07-29 2004-01-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

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