KR101133392B1 - Non-volatile Memory of having 3 Dimensional Structure - Google Patents

Abstract

A nonvolatile memory having a three-dimensional structure is disclosed. Next-generation nonvolatile memories perform resistance or phase changes between the two electrodes. A plurality of side electrodes corresponding to the lower electrode are disposed, and forms a step having a narrower width from the bottom to the top. The upper vertical electrode corresponding to the upper electrode is formed through the side electrode. This improves the density of next-generation nonvolatile memories. In addition, a diode is integrated between the region where the resistance change or phase change is performed and the upper vertical electrode. It has a forward configuration in normal operation and prevents reverse current due to malfunction.

Nonvolatile Memory, ReRAM, PRAM, PoRAM

Description

Non-volatile Memory of Having 3 Dimensional Structure

The present invention relates to a nonvolatile memory, and more particularly to a three-dimensional structure of the next generation nonvolatile memory.

Non-volatile memory, which is represented by a flash memory device, has a characteristic of retaining stored information even when a power supply is cut off. Recently, ReRAM (Resistance Random Access Memory) using resistance change of metal oxide thin film in addition to flash memory, Phase Change Random Access Memory (PRAM) using resistance change due to phase transition phenomenon, PoRAM using polymer or organic material as resistance change material (Polymer Random Access Memory) and the like are actively researched. This new nonvolatile memory other than the conventional flash memory is collectively referred to as next generation nonvolatile memory.

Resistance Random Access Memory (ReRAM) is a structure composed of 'metal-oxide-metal', and is a memory device using the characteristic that the resistance of an oxide located in the middle is changed by a specific voltage. Titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), nickel oxide (NiO), hafnium oxide (HfO ₂ ), silicon oxide (SiO ₂ ), or lanthanum oxide (LaO) is used as the oxide used in the device. In addition, PCMO (Pr _{1 - x} Ca _x MnO ₃ ) or LCMO (La-Ca-Mn-O), which is a multimetal oxide, may be used.

The oxide basically functions as an insulator, but when a high voltage is applied, an electrode metal material is inserted into the internal oxide due to electrical stress, or a metallic path is formed in an internal defect structure to form a passage through which current can flow. Will decrease. In this case, the resistance is greatly reduced as the signal '1'. On the contrary, in the state where the above-described phenomenon does not occur due to the lower voltage, the resistance value is large because the insulation property of the original oxide is maintained. This state is defined as signal '0'. If you need to read the stored information, apply a voltage between '1' and '0'. At this time, if the device is in a high resistance state and no current flows, it is recognized as '0'. If is passed, it operates as a memory device capable of recognizing '1' and storing information.

Similar to ReRAM, phase change random access memory (PRAM) stores information by changing the resistance state of an intermediate device. However, in the case of PRAM, a metal or non-metallic compound capable of phase change is used instead of a metal oxide. As the phase change material used as the information storage material in the PRAM, a compound of gallium (Ga) and lanthanide elements (La, Ce, Pr, Nd, etc.) may be used in addition to a chalcogenide compound. These phase-changeable materials are changed in state by thermal energy due to the applied current. That is, when high thermal energy generated by a large current is applied for only a short time and the writing is terminated, internal molecules of the phase change material melted by the thermal energy are not crystallized and become amorphous in a high resistance value. On the contrary, when a moderate amount of thermal energy generated by an appropriate current is applied over a long time, the internal molecules of the phase change material have a time allowance for crystallization, resulting in a crystal state having a low resistance value. At this time, if the resistance value is high, it is recognized as information '1' and if it is low, information '0' and the reading method operates in a similar way to ReRAM.

In addition, in the case of the polymer random access memory (PoRAM), the resistance state of the device is changed to store information, and the information storage material used in the PoRAM may be a general organic material as well as a polymer material. Materials used to change the resistance state include monomolecules (THP-CN ₂ -O-DNB), low molecules (AIDCN, Alq3, ZnPc, etc.), polymers (PVK, polystyrene, PS: TCNQ, PILC, etc.). The information storage method of PoRAM is different depending on the polymer material in the middle, and there are many materials whose operation method has not been identified and only the information storage characteristics are confirmed. In the case of Ion concentration control type, the current storage method has been identified, copper ions move inside the polymer material when a voltage of 2V or more is applied in the structure of copper-polymer material-copper, and current flows due to electron transfer by these ions. As it flows, it becomes a signal '1' and there is no movement of copper ions at a voltage below 2V, so it functions as an insulator, so no current flows and this becomes '0'. In addition to this, there are various types such as IBM type and UCLA type, but only the operation characteristics are not identified.

The three devices have a common metal-information storage material-metal form and store information by changing the state of an intermediate information storage material. This method is much simpler than conventional transistor-based memory structures, and can function as a resistor, or "memrister," which functions as a memory. Simply put, a memory resistor, an information storage material, is placed between the array of top metal electrodes and the array of bottom metal electrodes (the two electrodes must be placed at right angles to each other), storing information at a write voltage, and reading at a lower voltage. Large-scale memory structures can be produced.

Compared with a transistor-based manufacturing method, which is a conventional memory device manufacturing method, the next-generation nonvolatile memory described above has an excellent degree of integration compared to a transistor method requiring an area of a source, a drain, and a gate. This is due to the fact that the next-generation nonvolatile memory described above has memory characteristics as one resistor. In addition, if a simple deposition process is used three to five times instead of a complicated transistor manufacturing process, the memory device is completed, and thus, the process time and cost can be compared with conventional transistor-based memory devices. (Reference: Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart & R. Stanley Williams, “The missing memristor found” Nature Vol 453 | 1 May 2008 | doi: 10.1038)

Although all three devices have excellent integration in themselves, in order to further increase the integration, a three-dimensional manufacturing process for manufacturing devices three-dimensionally from a conventional two-dimensional semiconductor manufacturing process should be used.

There are many advantages of the three-dimensional structure, but the biggest advantage is that the integration can be greatly increased while maintaining the size of the device as it is.

Introduced is the Stack technique, which is a method of repeatedly stacking silicon on a wafer once all processes are finished and fabricating the device again. However, the disadvantage is that each layer is manufactured using a lithography process similar to the existing process. In other words, as the number of layers to be laminated increases, lithography costs continue to increase and cost increases, which is not currently used well. In addition, various methods have been proposed, but the next-generation nonvolatile memory requires a different process from the conventional semiconductor, and thus it is difficult to apply the method.

An object of the present invention for solving the above problems is to provide a nonvolatile memory having a three-dimensional structure.

In order to achieve the above object, the present invention, side electrodes formed on the substrate, extending in the lateral direction having a step; A resistance change layer formed in an open area passing through the side electrode and formed on a side surface of the side electrode; A diode formed on a side of the resistance change layer and integrally formed with respect to the entirety of the resistance change layer; And an upper vertical electrode formed through the side electrodes and filling a space opened by the formation of the diode.

In addition, the present invention for achieving the above object, side electrodes formed on the substrate, extending in the lateral direction, having a step; An upper vertical electrode formed through the side electrodes; A heater layer formed on the same layer as the side electrode and formed by nitriding the side electrode; A phase change layer integrally formed on a side surface of the heater layer; And a diode integrally formed on a front surface of a side of the phase change layer.

The above object of the present invention, the side electrodes formed on the substrate, extending in the lateral direction, having a step; An upper vertical electrode formed through the side electrodes; An organic material film integrally formed on the entire side surfaces of the penetrating side electrodes; And a diode formed over the entire side surface of the organic material film and electrically connected to the upper vertical electrode.

According to the present invention described above, in the unit device structure of the next-generation nonvolatile memory represented by ReRAM, PRAM, and PoRAM, a high performance device can be realized very simply and quickly. In addition, the diode is integrally formed in the film to perform the memory operation to prevent reverse current caused by a malfunction. In addition, a large capacity three-dimensional memory structure can be realized.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and, unless expressly defined in this application, are construed in ideal or excessively formal meanings. It doesn't work.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

First Example

1 to 22 are cross-sectional views and plan views illustrating a method of manufacturing a nonvolatile memory according to the first embodiment of the present invention.

Referring to FIG. 1, a buffer layer 110 is formed on a substrate 100. The substrate 100 is preferably made of silicon. In addition, the buffer layer 110 is formed using a dry or wet oxidation method, it is preferable that silicon oxide (SiO ₂ ) is used. In addition to the method of forming the buffer layer 110 described above, various methods such as sputtering or chemical vapor deposition may be used.

Referring to FIG. 2, insulating layers 120, 122, 124, 126, and 128 and side electrodes 121, 123, 125, and 127 are sequentially formed on the buffer layer 110, and are repeatedly formed. Therefore, a plurality of layers are formed on the buffer layer 110 by alternating insulating layers 120, 122, 124, 126, and 128 and side electrodes 121, 123, 125, and 127. In FIG. 2, the first to fifth insulating layers 120, 122, 124, 126, and 128 and the first to fourth side electrodes 121, 123, 125, and 127 are sequentially formed. If the combination of the and side electrodes is composed of a plurality of layers without departing from the spirit of the present invention. Of course, the degree of integration increases as the number of stacks increases, so the number of stacks may be greater than that shown in FIG. 2.

In addition, in order to sequentially stack the insulating layers 120, 122, 124, 126, and 128 and the side electrodes 121, 123, 125, and 127, sputtering or chemical vapor deposition, which may be formed in situ, is preferably used. In addition, the insulating layers 120, 122, 124, 126, and 128 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), metal oxides (CuO, NiO, TiO ₂ , Fe ₂ O _3). Etc.) or a multilayer thin film thereof, and the side electrodes 121, 123, 125, and 127 may include titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), and gold (Au). It may be formed of platinum (Pt) or an alloy thereof.

Referring to FIG. 3, a hard mask layer 130 is formed on the fifth insulating layer 128. The hard mask layer 130 is used as an etching mask for etching the insulating layers 120, 122, 124, 126, and 128 and the side electrodes 121, 123, 125, and 127. The hard mask layer 130 may be formed by a sputtering method or a chemical vapor deposition method. The hard mask layer 130 masks only a specific portion using photolithography and an etching process. In addition, the hard mask layer 130 may be formed in a plurality of layers, without being limited to one layer. For example, the hard mask layer 130 may be formed by sequentially stacking silicon oxide (SiO ₂ ) and silicon nitride (SiN). In addition, the photoresist pattern itself may be used as the hard mask film 130.

Referring to FIG. 4, an etching process is performed on the insulating layers 120, 122, 124, 126, and 128 and the side electrodes 121, 123, 125, and 127 using the hard mask layer 130 as an etching mask. As a result, a portion of the surface of the buffer layer 110 is exposed. In the etching process, reactive ion etching (RIE) is preferably used. Accordingly, a fluorine-based gas such as CF ₄ or CHF ₃ is used for etching the insulating layers 120, 122, 124, 126, and 128, and Cl ₂ is used for etching the side electrodes 121, 123, 125, and 127. , Chlorine-based gas such as SiCl ₄ or BCl ₃ , and mixtures thereof. The hard mask layer 130 is preferably etched in the gas used in the etching process or a low selection ratio is preferably used. In addition, the shape of the part etched in the said etching process is not limited to a rectangle, It may be another shape (for example, circular shape).

Referring to FIG. 5, a resistance change layer 140, an n-type semiconductor layer 142, a p-type semiconductor layer 144, and an upper vertical electrode 150 are formed on the structure illustrated in FIG. 4.

The resistance change layer 140 is formed on the open region and the top surface by the etching process illustrated in FIG. 4, and the n-type semiconductor layer 142 and the p-type semiconductor layer 144 are formed on the resistance change layer 140. Are stacked. The n-type semiconductor layer 142 and the p-type semiconductor layer 144 forms a diode. The formed diode is provided to block an overcurrent generated by reverse bias in a data read operation or a program operation on the resistance change layer 140. Therefore, the diode is provided in the positive direction of the normal bias application direction, and if the bias is applied from the side electrodes 121, 123, 125, and 127, the p-type semiconductor layer and the sidewall of the resistance change layer 140 are provided. The n-type semiconductor layer will be formed sequentially. The same applies to the embodiments described later.

An upper vertical electrode 150 is formed on sidewalls of the p-type semiconductor layer 144 constituting the diode. The upper vertical electrode 150 may be formed to fill a well-shaped region due to the etching process of FIG. 4.

The n-type semiconductor layer 142 and the p-type semiconductor layer 144 is preferably polycrystalline silicon, and the dopant is deposited in a highly doped state according to each conductivity type.

In addition, the resistance change layer 140 and the upper vertical electrode 150 may be formed by sputtering, chemical vapor deposition, or atomic layer deposition. However, as the insulating layers 120, 122, 124, 126, and 128 and the side electrodes 121, 123, 125, and 127 are stacked more, the depth of etching becomes deeper, so that the resistance change layer 140 and the upper vertical electrode 150 are formed. In the case of burying with), since voids due to the etching process disclosed in FIG. 4 may remain, it is preferable to form a deposition method having excellent gap-fill capability. In addition, the upper vertical electrode 150 may be formed by a damascene process.

The resistance change layer 140 may be formed of silicon oxide (SiO ₂ ), metal oxide (TiO ₂ , Al ₂ O ₃ , NiO, HfO ₂ , Fe ₂ O ₃ Etc.), a lanthanide oxide film (LaO, CeO ₂ , or Pr ₂ O ₃ ) or a polymetal oxide (PCMO: Pr _{1 - x} Ca _x MnO ₃ , LCMO: La-Ca-Mn-O) may be used. The upper vertical electrode 150 may be made of the materials presented by the side electrodes 121, 123, 125, and 127 or a metal alloy.

In FIG. 5, the resistive change layer 140, the n-type semiconductor layer 142, the p-type semiconductor layer 144, and the upper vertical electrode 150 are formed while the hard mask layer 130 remains. In some embodiments, after the hard mask layer 130 is removed, the resistance change layer 140, the n-type semiconductor layer 142, the p-type semiconductor layer 144, and the upper vertical electrode 150 may be formed. .

Referring to FIG. 6, a portion of the structure shown in FIG. 5 is removed and a planarization process is performed to remove one of the insulating layers 120, 122, 124, 126, and 128 or the side electrodes 121, 123, 125, and 127. Top layer 128 is exposed.

The planarization process is preferably accomplished through chemical mechanical polishing. Further, the planarization process proceeds until the fifth insulating film 128 disclosed in the drawings of this embodiment is exposed. Of course, the hard mask film may remain without exposing the fifth insulating film 128. As a result, surfaces of the upper vertical electrode 150, the n-type semiconductor layer 142, the p-type semiconductor layer 144, and the resistance change layer 140 are exposed.

FIG. 7 is a plan view of a nonvolatile memory after completion of the planarization process illustrated in FIG. 6.

Referring to FIG. 7, the fifth insulating layer 128 is disposed, has a regular arrangement, and the plurality of upper vertical electrodes 150, the n-type semiconductor layer 142, the p-type semiconductor layer 144, and the resistance change. Layer 140 is provided. In addition to the shape of the top view illustrated in FIG. 7, various device arrangements may be implemented, and it will be apparent that various arrangements that can be considered by those skilled in the art do not depart from the spirit of the present invention.

Referring to FIG. 8, the first photoresist pattern 160 is formed on the structure where the planarization process of FIG. 6 is completed. In addition, a first etching process is performed using the formed first photoresist pattern 160 as an etching mask. In the first etching process, the fifth insulating layer 128, the fourth side electrode 127, and the fourth insulating layer 126 are removed from the lower region of the first photoresist pattern, and the third side electrode 125 is exposed. Proceed until. By the above-described first etching process, the fourth insulating layer 126, the fifth insulating layer 128, and the fourth side electrode 127 have the same profile as the first photoresist pattern 160.

9, a reduction process is performed on the formed first photoresist pattern 160 to form a second photoresist pattern 162. The reduction process is referred to as photoresist shrink or photoresist sliming, and is to reduce the size of the first photoresist pattern 130 previously formed. Reduction to the first photoresist pattern 160 is accomplished by exposure to reactive plasma gas. However, the reactive plasma gas may be differently selected depending on the composition of the photoresist pattern. The second photoresist pattern 162 having a smaller size than the first photoresist pattern 160 is formed by the reduction process.

Referring to FIG. 10, a second etching process is performed using the formed second photoresist pattern 162 as an etching mask.

First, a portion of the fifth insulating layer 128 except for the lower portion of the second photoresist pattern 162 is removed. When the portion of the fifth insulating layer 128 is removed, the region exposed to the outside of the third side 125 electrode of FIG. 9 is not etched. This is due to the fact that conventional etching processes have an etch selectivity for heterogeneous films that are alternately stacked. Accordingly, a portion of the fourth side electrode 127 is exposed by etching the portion of the fifth insulating layer 128, and the previously exposed third side electrode 125 remains without etching.

Subsequently, an etching process is performed on a portion of the fourth side electrode 127 exposed in the lateral direction of the second photoresist pattern 162. Since the fourth side electrode 127 and the third side electrode 125 are made of the same material, a portion of the third side electrode 125 exposed together with the etching of the fourth side electrode 127 is also removed. Accordingly, a portion of the fourth insulating layer 126 under the fourth side electrode 127 is exposed, and a portion of the third insulating layer 124 under the third side electrode 125 is exposed.

Subsequently, an etching process is performed on the fourth insulating layer 126 exposed in the lateral direction of the second photoresist pattern 162. Etching of the exposed third insulating layer 124 is performed along with etching of the fourth insulating layer 126. A part of the second side electrode 123 and the third side 125 electrode is exposed by simultaneous etching of the two insulating layers 124 and 126.

In the above-described second etching process of FIG. 10, the third insulating layer 124 and the third side electrode 125 have the same profile as the first photoresist pattern 160, and the fourth insulating layer 126 and the fifth insulating layer. 128 and the fourth side electrode 127 have the same profile as the second photoresist pattern 162. This is the result of etching performed by the fourth insulating layer 126, the fifth insulating layer 128, and the fourth side electrode 127 using the second photoresist pattern 162 as an etching mask. This is because the third side electrode 125 is a result of etching by using the fourth electrode 127 and the fourth insulating layer 126 shown in FIGS. 8 and 9 as etching masks.

The result of the second etching process of FIG. 10 is shown in FIG. 11.

Referring to FIG. 12, a reduction process is performed on the previously formed second photoresist pattern 162. The reduction process proceeds as described in FIG. Therefore, in order to express clearly and concisely the technical matter of this invention, the overlapping description is avoided. A third photoresist pattern 164 having a smaller size than the second photoresist pattern 162 is formed by the reduction process disclosed in FIG. 12. A portion of the fifth insulating layer 128 under the second photoresist pattern 162 is exposed by forming the third photoresist pattern 164.

Referring to FIG. 13, a third etching process is performed using the third photoresist pattern 164 as an etching mask.

First, a portion of the fifth insulating layer 128 except for the lower portion of the third photoresist pattern 164 is removed. When the portion of the fifth insulating layer 128 is removed, the region exposed to the outside in the third side electrode 125 disclosed in FIG. 12 is not etched. This is due to the fact that conventional etching processes have an etch selectivity for heterogeneous films that are alternately stacked. Accordingly, a portion of the fourth side electrode 127 is exposed by etching the portion of the fifth insulating layer 128, and the previously exposed third side electrode 125 remains without etching.

Subsequently, an etching process is performed on the fourth side electrode 127, the third side electrode 125, and the second side electrode 123 exposed in the lateral direction of the third photoresist pattern 164. Accordingly, a portion of the fourth insulating layer 126 under the fourth side electrode 127 is exposed, a portion of the third insulating layer 124 under the third side electrode 125 is exposed, and the second side electrode 123 is exposed. A portion of the lower second insulating film 122 is exposed.

Subsequently, an etching process is performed on the fourth insulating layer 126, the third insulating layer 124, and the second insulating layer 122 exposed in the lateral direction of the third photoresist pattern 164. A portion of the first side electrode 121, the second side electrode 123, and the third side electrode 125 are exposed by simultaneous etching of the three insulating layers 122, 124, and 126.

In the above-described third etching process of FIG. 13, the second insulating layer 122 and the second side electrode 123 have the same profile as the first photoresist pattern 160, and the third insulating layer 124 and the third side surface. The electrode 125 has the same profile as the second photoresist pattern 162, and the fourth insulating layer 126, the fifth insulating layer 128, and the fourth side electrode 127 have a third photoresist pattern 164. Have the same profile as

The result of the second etching process of FIG. 13 is shown in FIG. 14.

Referring to FIG. 15, a reduction process of the previously formed third photoresist pattern 164 is performed.

The reduction process proceeds as described in FIG. Accordingly, the fourth photoresist pattern 166 having a smaller size than the third photoresist pattern 164 is formed by the reduction process disclosed in FIG. 15. A portion of the fifth insulating layer 128 under the third photoresist pattern 164 is exposed by the formation of the fourth photoresist pattern 166.

Referring to FIG. 16, an etching process is performed on the exposed fifth insulating layer 128 using the formed fourth photoresist pattern 166 as an etching mask. Thus, part of the fourth side electrode 127 is exposed.

8 to 16 are performed to transfer the photoresist pattern from the bottom to the top. The insulating layers 120, 122, 124, 126, and 128 and the side electrodes 121, 123, 125, and 127 are profiled. They are paired on the side and introduced to form stepped steps between adjacent pairs.

 17 to 20 are plan views illustrating inter-element isolation of the nonvolatile memory proceeding to FIG. 16 according to the present embodiment.

Referring to FIG. 17, the fourth photoresist pattern is removed from the structure formed by FIG. 16, and a separation photoresist pattern 170 is formed. Subsequently, etching is performed using the separation photoresist pattern 170 as an etching mask. Through etching, the side electrodes 121, 123, 125, and 127 and the insulating layers 120, 122, 124, 126, and 128 are removed, and the surface of the buffer layer 110 or the substrate 100 is exposed. This is shown in FIG.

Alternatively, device isolation may be performed by etching the upper vertical electrode 150 and the resistance change layer 140 as illustrated in FIGS. 19 and 20.

21, the protection film 190 is formed to protect the device, and the planarization process for the protection film 190 is performed. The planarization process is preferably achieved through chemical mechanical polishing. The protective layer 190 may be any insulating material, but silicon oxide (SiO ₂ ) is preferably used.

Referring to FIG. 22, an upper electrode 200 and a lower electrode 300 are formed, the upper electrode 200 is connected to the upper vertical electrode 150, and the lower electrode 300 is formed of side electrodes 121, 123, 125, 127). Electrical connection between the upper electrode 200 and the upper vertical electrode 300 is achieved by the upper contact plug 250, the electrical connection between the lower electrode 300 and the side electrodes 121, 123, 125, 127 Achieved by the bottom contact plugs 350. The formation of the respective contact plugs is in accordance with conventional forming methods. That is, a plurality of via holes are formed, and the holes are filled with a conductive metal to form a contact plug. As the material of the upper electrode 200, the lower electrode 300, and the contact plugs 250 and 350, a metal used for manufacturing a semiconductor device is preferably used. Therefore, tungsten (W), aluminum (Al), copper (Cu), gold (Au), or the like may be used.

Thus, pairs of insulating layers 120, 122, 124, 126, and 128 and side electrodes 121, 123, 125, and 127 having a step are formed on the substrate 100 or the buffer layer 110, and the insulating layer 120 is formed. , 122, 124, 126, and 128 and through the center of the side electrodes 121, 123, 125, and 127, the resistance change layer 140, the n-type semiconductor layer 142, the p-type semiconductor layer 144, and the upper portion thereof. The vertical electrode 150 is formed. In particular, the insulating layers 120, 122, 124, 126, and 128 and the side electrodes 121, 123, 125, and 127 have a larger area as disposed below and a smaller area as disposed above. A diode and a resistance change layer 140 are provided between the upper vertical electrode 150 and the side electrodes 121, 123, 125, and 127. In addition, the passivation layer 190 is formed through the front surface, and the side electrodes 121, 123, 125, and 127 contacting the passivation layer 190 are electrically connected to the lower electrode 300 through the lower contact plugs 350. do. In addition, the upper electrode 200 is electrically connected to the upper vertical electrode 250 through the upper contact plug 250.

In particular, malfunction of the memory device due to the reverse bias is prevented through the diode formed over the sidewall of the resistance change layer 140.

2nd Example

23 to 25 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory in accordance with a second embodiment of the present invention.

First, the manufacturing method of FIGS. 1 to 4 disclosed in the first embodiment is equally applied to this embodiment. Therefore, the description of the etching process using the hard mask will be omitted.

Referring to FIG. 23, an oxidation process is performed on side surfaces of the side electrodes 421, 423, 425, and 427 exposed to the etched inner region. Through oxidation, the metallic side electrodes 421, 423, 425, and 427 are modified into the resistance change layer 440. Accordingly, the side electrodes 421, 423, 425, and 427 may be formed of titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), or an alloy thereof. It may be formed. However, in order to improve the efficiency of oxidation, it is preferable that a material of the side electrode is easily oxidized, such as Ti.

Referring to FIG. 24, an n-type semiconductor layer 442 and a p-type semiconductor layer 444 may be formed on sidewalls of the side electrodes 421, 423, 425, and 427 and sidewalls of the insulating layers 420, 422, 424, 426, and 428. ) Are sequentially stacked. In addition, an upper vertical electrode 450 is formed on the entire surface of the sidewall of the diode formed by the n-type semiconductor layer 442 and the p-type semiconductor layer 444. The material of the upper vertical electrode 450 is the same as that disclosed in the first embodiment. In addition, the polarity of the formed diode can be changed by the bias applied is the same as described in the first embodiment.

After the formation of the upper vertical electrode 450, the manufacturing method of the nonvolatile memory according to the present embodiment is the same as the manufacturing method of FIGS. 6 to 22 disclosed in the first embodiment. Therefore, the transfer of the pattern using a plurality of photoresist patterns and the formation of a pair of insulating layers 420, 422, 424, 426, 428 and side electrodes 421, 423, 425, and 427 having a step therebetween are described above. Same as disclosed in the first embodiment.

Referring to FIG. 25, pairs of insulating layers 420, 422, 424, 426, and 428 and side electrodes 421, 423, 425, and 427 are formed on the substrate 400 or the buffer layer 410. The upper vertical electrode 450 is formed through the centers of the insulating layers 420, 422, 424, 426, and 428 and the side electrodes 421, 423, 425, and 427. Between the upper vertical electrode 450 and the side electrodes 421, 423, 425, and 427, a diode formed by the modified resistance change layer 440 and the n-type semiconductor layer 442 and the p-type semiconductor layer 444 is formed. It is provided. In addition, the passivation layer 455 is formed through the front surface, and the side electrodes 421, 423, 425, and 427 contacting the passivation layer 455 are electrically connected to the lower electrode 480 through the lower contact plugs 490. do. In addition, the upper electrode 460 is electrically connected to the upper vertical electrode 450 through the upper contact plug 470.

The nonvolatile memory disclosed in the second embodiment omits the process of generating a separate resistance change layer on the side by vapor deposition, etc., and has a technical feature of modifying the metallic side electrode to the resistance change layer through an oxidation process. In addition, a diode is integrally disposed on the sidewalls of the entire resistance change layers 440 to prevent malfunction of the memory.

The third Example

This embodiment applies a nonvolatile memory to a PRAM. Thus, the resistance change layer disclosed in the second embodiment is replaced with a heater layer. In addition, the manufacturing method of the nonvolatile memory according to the present embodiment is the same as the process of FIGS. 1 to 4 disclosed in the first embodiment. Therefore, the corresponding technical description will be omitted.

26 to 28 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory in accordance with a third embodiment of the present invention.

Referring to FIG. 26, a nitriding process is performed on a structure formed by the process of FIGS. 1 to 4 disclosed by the first embodiment. The side electrodes 521, 523, 525, and 527 exposed by the nitriding process are modified by the heater layer 540. Since the degree of nitriding in the nitriding process is to increase the resistance of the modified heater layer 540, it is preferable to avoid complete nitriding. The heater layer 540 is for supplying thermal energy to a phase change layer formed later, the phase of the material constituting the phase change layer is changed by the supplied thermal energy. For easy formation of the heater layer 540, the side electrodes 521, 523, 525, and 527 may be made of titanium (Ti), tungsten (W), aluminum (Al), nickel (Ni), or copper (Cu). Can be.

Referring to FIG. 27, the phase change layer 550, the n-type semiconductor layer 552, the p-type semiconductor layer 554, and the upper vertical electrode 560 are sequentially formed on the structure of FIG. 26.

The phase change layer 550 is composed of a phase-change material (PCM), and the phase change layer 550 and the upper vertical electrode 560 are formed using a sputtering method or a chemical vapor deposition method. In addition, the phase change layer 550 is preferably a chalcogenide (Chalcogenide) compound. In addition, compounds of gallium (Ga) or lanthanide elements (La, Ce, Pr, Nd, etc.) may be used.

In addition, the upper vertical electrode 560 may be any conductive material. The materials presented by the side electrodes 521, 523, 525, and 527 may be used or a metal alloy may be used.

In addition, the n-type semiconductor layer 552 and the p-type semiconductor layer 554 disposed between the phase change layer 550 and the upper vertical electrode 560 are determined mutually depending on the direction in which bias is applied. That is, when a voltage applied to induce a phase change or a voltage applied in a read operation is applied from the upper vertical electrode 560, the n-type semiconductor layer 552 is formed on the sidewall of the phase change layer 550, and p The type semiconductor layer 554 is formed on the sidewall of the n type semiconductor layer 552. Of course, when the applied voltage is applied from the side electrodes 521, 523, 525, and 527, the arrangement order of the n-type semiconductor and the p-type semiconductor is changed.

Subsequent manufacturing processes are the same as those described in Figs. 6 to 22 in the first embodiment.

Thus, referring to FIG. 28, pairs of insulating layers 520, 522, 524, 526, and 528 and side electrodes 521, 523, 525, and 527 are formed on the substrate 500 or the buffer layer 510. And a phase change layer 550, an n-type semiconductor layer 552, and a p-type semiconductor, formed through the centers of the insulating layers 520, 522, 524, 526, 528, and the side electrodes 521, 523, 525, and 527. Layer 554 and upper vertical electrode 560 are formed. The modified heater layer 540 is provided between the phase change layer 550 and the side electrodes 521, 523, 525, and 527. In addition, the passivation layer 565 is formed through the front surface, and the side electrodes 521, 523, 525, and 527 contacting the passivation layer 565 are electrically connected to the lower electrode 580 through the lower contact plugs 585. do. In addition, the upper electrode 570 is electrically connected to the upper vertical electrode 550 through the upper contact plug 575.

Fourth Example

The matters disclosed in this embodiment apply the technical idea of the present invention to a PoRAM. To this end, the resistance change layer and the phase change layer disclosed in the first to third embodiments are replaced with an organic material film. However, the organic material film used in the present embodiment refers to an organic material that can be used as a memory as well as a single molecule, a low molecule and a polymer material.

In addition, the manufacturing method of the nonvolatile memory according to the present embodiment is the same as the process of FIGS. 1 to 4 disclosed in the first embodiment. Therefore, the corresponding technical description will be omitted.

29 to 31 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory in accordance with a fourth embodiment of the present invention.

Referring to FIG. 29, the organic material film 640, the n-type semiconductor layer 642, the p-type semiconductor layer 644, and the upper portion of the structure formed by the process of FIGS. 1 to 4 disclosed by the first embodiment are described. Vertical electrodes 650 are sequentially formed.

As the organic material layer 640, a single molecule (THP-CN ₂ -O-DNB), a low molecule (AIDCN, Alq 3, ZnPc, etc.) or a polymer (PVK, polystyrene, PS: TCNQ, PILC, etc.) may be used.

The upper vertical electrode 650 is formed using a sputtering method, a chemical vapor deposition method or a thermal vapor deposition method. In addition, as shown in FIG. 30, the first organic material film 645 / the intermediate metal layer 646 / the second organic material film 647 / the n-type semiconductor layer 648 for the structure formed by the etching of FIG. 4. ) / p-type semiconductor layer 649 / upper vertical electrode 650 may be formed in a multi-layer structure.

Subsequent manufacturing processes are the same as those described in Figs. 6 to 22 in the first embodiment.

Thus, referring to FIG. 31, pairs of insulating layers 620, 622, 624, 626, and 628 and side electrodes 621, 623, 625, and 627 are formed on the substrate 600 or the buffer layer 610. The organic material film 640, the n-type semiconductor layer 642, and the p-type semiconductor are formed through the centers of the insulating films 620, 622, 624, 626, and 628 and the side electrodes 621, 623, 625, and 627. Layer 644 and top vertical electrode 650 are formed. Accordingly, a structure in which a diode composed of an organic material layer 640 and two semiconductor layers 642 and 644 are disposed between the upper vertical electrode 650 and the side electrodes 621, 623, 625, and 627. In particular, the arrangement of diodes prevents reverse current from applied voltages such as read operations. To this end, it is preferable that the arrangement of the diodes be arranged in the forward direction during normal operation.

In addition, a passivation layer 655 is formed through the front surface, and side electrodes 621, 623, 625, and 627 contacting the passivation layer 655 are electrically connected to the lower electrode 670 through the lower contact plugs 675. do. In addition, the upper electrode 660 is electrically connected to the upper vertical electrode 650 through the upper contact plug 665.

As described above, according to the present invention, a plurality of side electrodes may be formed to manufacture a nonvolatile memory device. The nonvolatile memory device manufactured by the present invention has a three-dimensional structure as a multilayer structure. This results in a high density and high performance nonvolatile memory device.

1 to 22 are cross-sectional views and plan views illustrating a method of manufacturing a nonvolatile memory according to the first embodiment of the present invention.

23 to 25 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory in accordance with a second embodiment of the present invention.

26 to 28 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory in accordance with a third embodiment of the present invention.

29 to 31 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory in accordance with a fourth embodiment of the present invention.

Claims (14)

Side electrodes formed on the substrate and extending in the lateral direction and having a step; A resistance change layer formed in an open area passing through the side electrode and formed on a side surface of the side electrode; A diode formed on a side of the resistance change layer and integrally formed with respect to the entirety of the resistance change layer; And And an upper vertical electrode formed through the side electrodes and filling a space opened by the formation of the diode. The nonvolatile memory as claimed in claim 1, wherein the side electrodes are separated from each other by intervening insulating layers, and the side electrodes disposed on the lower side have a larger area than the side electrodes disposed on the upper side. The method of claim 1, wherein the diode, An n-type semiconductor layer formed integrally with the entirety of the resistance change layer; And And a p-type semiconductor layer formed on sidewalls of the n-type semiconductor layer. The method of claim 1, wherein the resistance change layer is formed of a silicon oxide film (SiO ₂ ), a metal oxide film (TiO ₂ , Al ₂ O ₃ , NiO, HfO ₂ , or Fe ₂ O ₃ ), or a lanthanide oxide film (LaO, CeO). ₂ , or Pr ₂ O ₃ ) or a polymetal oxide (PCMO: Pr _1-x Ca _x MnO ₃ , LCMO: La-Ca-Mn-O). The nonvolatile memory according to claim 1, wherein the resistance change layer is formed on the same layer as the side electrode and is formed by oxidation of the side electrode. 6. The non-volatile electrode according to claim 5, wherein the side electrode is titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), or an alloy thereof. Memory. Side electrodes formed on the substrate, extending laterally and having a step; An upper vertical electrode formed through the side electrodes; A heater layer formed on the same layer as the side electrode and formed by nitriding the side electrode; A phase change layer integrally formed on a side surface of the heater layer; And And a diode integrally formed on a front surface of a side of the phase change layer. The nonvolatile memory of claim 7, wherein the side electrodes are separated from each other by intervening insulating layers, and the side electrodes disposed on the lower side have a larger area than the side electrodes disposed on the upper side. The nonvolatile memory of claim 7, wherein the phase change layer is formed through the side electrodes. The nonvolatile memory as claimed in claim 9, wherein the phase change layer comprises a chalcogenide compound, a gallium (Ga) compound, or a lanthanide element (La, Ce, Pr, or Nd). Side electrodes formed on the substrate, extending laterally and having a step; An upper vertical electrode formed through the side electrodes; An organic material film integrally formed on the entire side surfaces of the penetrating side electrodes; And And a diode formed on the entire side surface of the organic material film and electrically connected to the upper vertical electrode. The nonvolatile memory as claimed in claim 11, wherein the side electrodes are separated from each other by intervening insulating layers, and the side electrodes disposed on the lower side have a larger area than the side electrodes disposed on the upper side. 12. The nonvolatile memory according to claim 11, wherein the organic material film is formed through the side electrodes. The method of claim 11, wherein the diode, A nonvolatile memory, characterized in that it is made of polycrystalline silicon with a forward arrangement in normal operation.

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