KR101113486B1 - Method for manufacturing a Back junction solar cells - Google Patents

Abstract

The present invention relates to a method of manufacturing a back junction solar cell. The present invention plasma-dopes the p + layer 102 on the back surface of the n-type silicon wafer 100. The diffusion barrier layer 104 is patterned on the p + layer 102. In such a state, different gases are supplied in the same chamber to etch an unformed portion of the diffusion barrier film 104, form an n + layer 106 on the surface of the etched silicon wafer 100, and the remaining diffusion barrier film Remove 104. Thereafter, a high temperature process is performed. Then, the dopants included in the p + layer 102 and the n + layer 106 are activated to form p + and n + junctions, thereby forming an activated p + layer 108 and an n + layer 110, and simultaneously forming a thermal oxide film ( 112 is formed. According to the present invention, there is an advantage that the manufacturing process of the back-junction solar cell is shortened and the working conditions are improved.

Back Junction, Solar Cell, Vacuum Chamber, Gas, Dry Etching

Description

Method for manufacturing a back junction solar cells

The present invention relates to a back junction solar cell, and in particular, to perform a doping step of the back of the solar cell in one high-temperature process, and to perform a pre-process to form a base doping region in the same vacuum chamber to manufacture a back junction solar cell It is about how to.

The electrodes of the solar cell are formed on the front and rear surfaces of the solar cell, respectively, but the electrodes formed on the front face reduce the shadowing loss to sunlight.

Therefore, in order to improve the efficiency of solar cells, the general trend is to narrow the area of the electrode formed on the front surface to have a fine pattern as much as possible. However, even in this case, sunlight does not absorb as much as the electrode area formed on the front surface.

Therefore, in order to fundamentally eliminate the reduction of absorption by the electrode at the front of the solar cell, a solar cell having a back junction structure has been developed in which both electrodes are installed at the rear side. That is, the back junction solar cell has a base junction and an n-type (or p-type) that collects p-type (or n-type) charges on the back surface opposite to the front surface where light is incident on the p-type (or n-type) silicon substrate. It refers to the structure where all the emitter junctions that collect charges are located.

However, the back junction solar cell is expected to improve efficiency by improving the absorption rate of the solar light, but the manufacturing process was complicated and costly disadvantages. This can be said to be the cause that limits the commercialization of the solar cell of the back junction structure.

Therefore, back junction solar cells have been proposed that can simplify the process and reduce manufacturing costs. An example thereof is disclosed in US Patent No. US 07339110 (a solar cell and its manufacturing method, hereinafter referred to as a prior patent).

Here, the process of forming the base region and the emitter region on the back surface of the p-type silicon wafer in the manufacturing process of the prior patent will be described.

First, a p + layer is formed on one side (i.e., the opposite side to which sunlight is incident) of the p-type silicon wafer on which the saw damage etching process is completed, and a thermal oxide film is formed thereon.

An etch resist is printed on a portion of the thermal oxide film, that is, a region except for a portion where an n + layer is to be formed.

Thereafter, the thermal oxide layer is etched, and then, the region where the n + layer is to be formed is etched to a predetermined depth to form an n + layer. In this case, the etching depth may be larger than the junction depth of the p + layer. In the above patent, it is illustrated as 3㎛.

When the etching process is completed, the back surface of the silicon wafer is cleaned with a cleaning liquid.

Then, an n + layer is formed on the surface of the etched silicon wafer using a liquid dopant source such as 'POCl ₃ (phosphorus oxychloride)', which is a doping element of the p-type silicon wafer. Of course, when the n-type silicon wafer and p + layer to form a liquid dopant source such as 'BB _r3 ' is used.

As such, in the prior patent, a process of jointly forming a base region for collecting charges of the same conductivity type as the silicon wafer and an emitter region for collecting charges of another conductivity type is complicated on the rear surface of the silicon wafer. have.

In addition, the process of doping the p-type and n-type impurities in the prior patent and the process of forming a thermal oxide film is carried out in a high temperature diffusion furnace, it is carried out at a high temperature of about 900 ℃. In other words, two diffusion processes and one thermal oxide film formation step were necessary at high temperatures.

In general, if the process temperature can be lowered while maintaining the efficiency in the solar cell process, this can help to reduce costs and simplify the process.

However, as described above, when the base region and the emitter region are formed on the back surface of the silicon wafer, the process is performed at a high temperature of 900 ° C. or higher, and the situation is not lowered to a process temperature below that. In addition, since the process is performed at a high temperature of more than 900 ℃ it was difficult to reduce the current number of processes.

In the prior patent, the process of etching the portion where the n + layer is to be formed using the etch register is necessary, which is complicated.

As a result, the prior patent has a substantial problem that it is difficult to sufficiently reduce the manufacturing cost of the solar cell because the energy input amount is increased and the process time is long when the back junction solar cell is manufactured.

Accordingly, an object of the present invention is to solve the above problems, to provide a method of manufacturing a back-junction solar cell for reducing the number of manufacturing process and lowering the process temperature to reduce the manufacturing cost.

According to a feature of the present invention for achieving the above object, a first step of forming a doped region of the second conductivity type on the back surface of the semiconductor substrate of the first conductivity type; Forming a diffusion barrier layer in the doped region of the second conductivity type; A third step of etching the portion where the diffusion barrier layer is not formed; Forming a doped region of the first conductivity type on a surface of the etched semiconductor substrate; A fifth step of removing the diffusion barrier remaining in the doped region of the second conductivity type; And a sixth step of thermally oxidizing the semiconductor substrate in which the diffusion barrier is removed at a predetermined temperature to form a junction of the first and second doped regions and a thermal oxide film on the rear surface of the semiconductor substrate.

The first and third steps are formed by implanting dopant ions into the semiconductor substrate by plasma doping, wherein the plasma doping is ion shower doping, and plasma ion implantation (PIII). Implantation 'method or ion implantation method is used.

The third to fifth steps are performed in the same vacuum chamber.

The third step is performed by dry etching, and the gas used for the dry etching uses a gas having an etching selectivity in which the diffusion barrier is not etched.

The fifth step is performed by dry etching, and the gas used for the dry etching uses a gas having an etching selectivity in which only the diffusion barrier is etched.

In the present invention, in fabricating a back junction solar cell, the p + layer and the n + layer are formed by plasma doping, and the junction and thermal oxide layers are formed in one high temperature process, and the etching, doping, and diffusion barrier removal processes are performed in the same vacuum chamber. I'm doing it within.

Accordingly, the high temperature process required in the conventional back junction solar cell can be reduced, thereby reducing the energy input amount. In addition, processing time is reduced due to the reduction of the high temperature process, and the life of the silicon wafer can be minimized due to the high temperature process. In addition, plasma doping can make the junction depth of the emitter region shallow, thereby reducing the etching depth of silicon.

That is, the process time and cost of the back junction solar cell can be reduced.

First of all, although the conventional etching-doping-diffusion barrier removal processes have been performed in different facilities, the present invention can be made without moving the silicon wafer since the three processes are performed in the same chamber. Conditions of work become convenient.

Hereinafter, a method of manufacturing a back junction solar cell according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the embodiment of the present invention, for convenience of description, a back junction solar cell is manufactured using an n-type silicon wafer. In addition, the specific resistance of a silicon wafer is about 1 micrometer cm, and the thickness is about 150-200 micrometers. However, the specific resistance and thickness are not limited.

1 is a flow chart illustrating a method of manufacturing a back junction solar cell according to a preferred embodiment of the present invention.

First, an etching process for improving the mechanical strength of the silicon wafer is performed by removing saw damage of the silicon surface damaged during the cutting of the silicon wafer (S100). The etching process is to remove the cutting damage by etching the surface of the silicon wafer 10㎛ or more with an acid solution containing hydrofluoric acid and nitric acid or an alkaline solution containing potassium hydroxide, sodium hydroxide and the like. When the etching process is completed, the metal or organic material that may be on the surface of the silicon wafer is cleaned using hydrochloric acid or the like.

When the etching process is completed, a p + layer is formed on the back surface of the silicon wafer (ie, the opposite surface to which sunlight is incident) by using a plasma doping technique (S102). The p + layer at this time has a state before the impurity ions are activated. The plasma doping technique is, for example, 'ion shower doping', 'plasma ion implantation (PIII)' or 'ion implantation'. In the plasma doping method, the silicon wafer is exposed to a plasma containing impurity ions so that impurity ions are implanted into one surface of the silicon wafer. These methods utilize kinetic energy of impurity ions. . Therefore, the high temperature process, which is conventionally performed when doping impurities into a silicon wafer, is not necessary, and thus a p + layer can be formed without heating the silicon wafer. In particular, by using the method, a thin junction can be formed on the surface of the silicon wafer. The junction thickness is formed to be thinner than the p + layer thickness formed when conventionally formed by doping with impurities at high temperature. Therefore, the etching depth can be further reduced in the subsequent etching process, thereby reducing the process time and cost.

After the p + layer is formed, a diffusion barrier layer is patterned on a portion of the p + layer, that is, the portion where the n + layer is not formed (s104). The diffusion barrier layer is formed by chemical vapor deposition (CVD), deposition (Evaporation), sputter (sputter) to form a diffusion barrier on the entire surface of the silicon wafer, screen printing using an etch paste as the diffusion barrier layer of the p + layer, An inkjet, aerosol jet, or the like is removed, or a commercially available diffusion barrier film paste is formed by screen printing.

Next, in the same vacuum chamber, the gas type, the flow rate, and the like are appropriately adjusted to perform an etching process, an n + layer forming process, and the diffusion barrier film removing process. The processes are performed in sequence, and conditions such as the type, flow rate, and the like of the gas supplied to the vacuum chamber during the process are different. Explain this.

First, the silicon wafer formed up to the diffusion barrier is placed in a vacuum chamber. The seated state is a fixed state until the process of removing the diffusion barrier.

In this state, the p + layer and the silicon wafer in the portion where the diffusion barrier film is not formed are etched by a predetermined depth (s106). The etching is dry etching by plasma. The gas used at this time is called a first gas. The etching depth may be larger than the junction depth of the p + layer. In general, the junction depth of the p + layer does not exceed 5 μm.

When the etching process is completed, the first gas is completely discharged from the vacuum chamber, and then a second gas is supplied to form an n + layer on the surface of the etched silicon wafer. The n + layer is formed by phosphor ion (Phosphorus) by the plasma ion implantation (PIII) method (s108). At this time, the dopant gas used in the plasma ion implantation (PIII) method is a gas containing phosphorus such as PH ₃ , PF _3, and the like. At this time, the n + layer is also in a state before being activated.

When the n + layer is formed, the second gas is completely discharged from the vacuum chamber, and then a third gas is supplied to remove the diffusion barrier layer formed on the p + layer (S110).

As such, after the etching process, the n + layer forming process, and the diffusion barrier film removing process are completed in the same vacuum chamber, a thermal oxidation process is performed at a high temperature of about 900 ° C. (s112). When the thermal oxidation process is performed, diffusion is performed while the dopants included in the p + and n + layers formed by the plasma doping are activated. Thus, n + type and p + type junctions are formed on the back surface of the silicon wafer, and a thermal oxide film is formed.

The above process will be described in detail with reference to FIG. 2. 2 is a cross-sectional view showing the manufacturing process of FIG.

FIG. 2A illustrates an n-type silicon wafer 100 having a saw damage etching process and a surface of which has been cleaned with a cleaning liquid.

FIG. 2 (b) shows a plasma doping ion shower doping, plasma ion implantation (PIII) method or ion implantation on the back surface of the silicon wafer 100. Boron doping by the 'method' method to form the p + layer 102.

When the p + layer 102 is formed, a diffusion mask 104 is patterned. The diffusion barrier layer 104 is not formed at the portion where the n + layer is to be formed. This state is shown in Fig. 2C.

Next, Figs. 2 (d) to 2 (f) are performed in the same vacuum chamber.

FIG. 2 (d) shows a state in which the n + layer is to be etched by a predetermined depth by supplying a first gas for etching used in a dry etching method. The first gas is a reaction gas such as F series or CI series. However, the present invention is not limited thereto, and the diffusion barrier layer 104 may be a gas having an etching selectivity in which only the surface of the silicon wafer 100 is etched without etching.

After completely discharging the first gas, a second gas containing phosphorus (Phosphorus) is supplied to form an n + layer 106 on the etched surface. This is the same as in Fig. 2 (e). The n + layer 106 is in non-contact state with the p + layer 102 formed in the previous process.

After the second gas is completely discharged, the third gas is supplied to remove the remaining diffusion barrier film 104 by a dry etching method. The third gas is a reaction gas such as F series or CI series. However, the present invention is not limited thereto, and only the diffusion barrier layer 104 may be etched, and the surface of the silicon wafer 100 may be a gas having an etching selectivity that is not etched.

Next, after removing the silicon wafer from the vacuum chamber, a thermal oxidation process is performed at a temperature of about 900 ℃. When the thermal oxidation process is performed, the dopants included in the p + layer 102 and the n + layer 106 formed in the previous process are diffused, so that the activated p + layer 108 and the n + layer 110 and the thermal oxide film ( 112 is formed. FIG. 2G is an activated state, and FIG. 2H is a state in which a thermal oxide film 112 is formed.

On the other hand, if a series of electrode forming process and anti-reflective film forming process to form a base electrode and an emitter electrode in the base region and the emitter region of the back surface of the silicon wafer 100 formed by the above-described process is performed The battery can be produced simply.

As described above, in the present invention, after forming the p + layer and the n + layer by plasma doping, the bonding and thermal oxide films are formed in one high-temperature process, and the etching, doping, and diffusion barrier removal processes are performed in the same vacuum chamber. It can be seen that.

The rights of the present invention are not limited to the embodiments described above, but are defined by the claims, and those skilled in the art can make various modifications and adaptations within the scope of the claims. It is self-evident.

In other words, in the present embodiment, an n-type silicon wafer is described as an example, but the present invention can be applied to a p-type silicon wafer.

In addition, in the present exemplary embodiment, a doping region of the second conductivity type is formed first and a doping region of the first conductivity type is formed on the back surface of the semiconductor substrate of the first conductivity type, but the present invention can also be applied to the present invention. .

1 is a flowchart of a method of manufacturing a solar cell having a back junction structure according to a preferred embodiment of the present invention.

2 is a cross-sectional view showing a solar cell manufacturing process of FIG.

Explanation of symbols on the main parts of the drawings

100: n-type silicon wafer 102: p + layer

104: diffusion barrier 106: n + layer

108: activated p + layer 110: activated n + layer

112: thermal oxide film

Claims (6)

A first step of forming a doped region of a second conductivity type opposite to the first conductivity type on a rear surface of the first conductivity type semiconductor substrate; Forming a diffusion barrier layer in the doped region of the second conductivity type; A third step of etching the portion where the diffusion barrier layer is not formed; Forming a doped region of the first conductivity type on a surface of the etched semiconductor substrate; A fifth step of removing the diffusion barrier remaining in the doped region of the second conductivity type; And And a sixth step of thermally oxidizing the semiconductor substrate in a state where the diffusion barrier is removed at a predetermined temperature to form a junction between the first and second doped regions and to form a thermal oxide film on the rear surface of the semiconductor substrate. Manufacturing method of solar cell. The method of claim 1, The first and third steps are formed by implanting dopant ions into the semiconductor substrate by plasma doping, The plasma doping method is a method of manufacturing a back junction solar cell, characterized in that the 'ion shower doping', 'Plasma Immersion Ion Implantation' (PIII) method or ion implantation (Ion Implantation) method. The method of claim 1, The first conductive doped region may be formed first, and then the second conductive doped region may be formed. The method of claim 1, The third to fifth steps are performed in the same vacuum chamber manufacturing method of a back junction solar cell. The method of claim 4, wherein The third step is performed by dry etching, The gas used for the dry etching is a method of manufacturing a back-junction solar cell, characterized in that the diffusion barrier using a gas having an etching selectivity that is not etched. The method of claim 4, wherein The fifth step is performed by dry etching, The gas used for the dry etching is a method of manufacturing a back-junction solar cell, characterized in that to use a gas having an etching selectivity to etch only the diffusion barrier.

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