KR101060697B1 - MOS transistor with increased channel width and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor having an increased channel width and a method of manufacturing the same. Forming a device isolation film in an inactive region of the semiconductor substrate, laminating a gate insulating film and a gate electrode over the active region of the semiconductor substrate, and actuating the substrate on the curved uneven surface separated by the gate electrode. Forming a source / drain region in the region.

MOS transistor, channel width increase, gate electrode, H2 anneal, trench

Description

MOS transistor with increased channel width and method for fabricating the same

1 is a vertical sectional view of a MOS transistor according to the prior art,

2A and 2B are a plan view showing a mask plan view for opening an active region in a gate electrode channel length direction during an MOS transistor manufacturing process according to the present invention and an example of an etching process using the same;

3 is a vertical cross-sectional view showing an example of performing an H2 annealing process on a substrate opened and etched in a channel length direction during a manufacturing process of the MOS transistor of the present invention;

4 is a vertical sectional view showing an example of a device isolation film manufacturing process of the MOS transistor of the present invention;

5A and 5B are vertical cross sectional views of a channel length and a channel width direction of a MOS transistor in which a gate electrode and a source / drain region are completed according to the present invention;

Explanation of symbols on the main parts of the drawings

100: inactive area 102: active area

104: mask area to etch a portion of the active area in the longitudinal direction of the channel

106: gate electrode mask 110: semiconductor substrate                 

112: pad insulating film 114: hard mask film

116: trench 116a: uneven surface curved in the longitudinal direction of the channel

118 device isolation film 120 gate insulating film

122: gate electrode 124: spacer

126 source / drain region l channel length

w: channel width

The present invention relates to a method of manufacturing a MOS transistor, and more particularly, to a method of manufacturing a MOS transistor capable of increasing the channel width of the gate electrode without increasing the critical dimension (CD) of the gate electrode.

As the integration of semiconductor devices increases, the device isolation layer adopts a shallow trench isolation (STI) structure rather than a LOCal (LOCal Oxidation of Silicon) structure, and the gate width (CD) of the gate electrode gradually decreases. There is a situation. As the line width of the gate electrode decreases, the threshold voltage decreases rapidly according to the short channel effect, and at the same time, the hot carrier effect occurs severely. In order to reduce the short channel effect and the hot carrier effect, the source / drain region is adopted as a lightly doped drain (LDD) structure.

1 is a vertical cross-sectional view of a MOS transistor according to the prior art. Referring to this, a method of manufacturing a conventional MOS transistor is as follows.

As the semiconductor substrate 10, an element isolation process such as STI is performed on a silicon substrate to form an element isolation layer 12 that defines an active region and a nonactive region of the element. A gate electrode 16 made of a conductive film such as a gate insulating film 14 and a doped polysilicon is sequentially formed on the active region of the semiconductor substrate 10. In this case, an insulating film of a hard mask and an anti reflective coating layer may be further formed on the upper surface of the gate electrode 16. A spacer 20 made of an insulating material is formed on side surfaces of the gate electrode 16 and the gate insulating layer 14. A source / drain ion implantation process is then performed to form the source / drain regions 22 in the substrate separated by the gate electrode 16. In this case, the source / drain regions 22 may have an LDD structure by performing an LDD ion implantation process before the spacer 20 manufacturing process.

However, in such a general MOS transistor, the line width of the gate electrode, that is, the channel length l and its width w, is determined during the patterning process of the gate electrode according to a design rule. In order to maintain or improve the on-current characteristics of the MOS transistor in a situation where the integration of semiconductor devices is rapidly progressing, the gate insulating film thickness of the transistor is also reduced to reduce the gate electrode capacitance by reducing the channel length (L) of the gate electrode. ) And the threshold voltage is also decreasing. In addition, in order to secure the on-current characteristics of the MOS transistor, a method of improving carrier mobility of a channel by a silicon germanium (SiGe) epitaxial growth method has been proposed.

However, these countermeasures usually improve the characteristics of transistors according to MOS transistor size and channel length reduction. Therefore, it is urgent to research / develop the channel width of transistors that are shrinking due to high integration of devices.

An object of the present invention is to provide a method for manufacturing a MOS transistor having an increased channel width by greatly increasing the active area surface area of the channel width direction of the gate electrode in order to solve the above problems of the prior art.
Another object of the present invention is to provide a MOS transistor having a structure with an increased channel width.

In order to achieve the above object, the present invention provides a method of manufacturing a MOS transistor, the method comprising the steps of forming a trench in the longitudinal direction of the gate electrode of the transistor in the active region of the semiconductor substrate, and to make the trench portion of the semiconductor substrate to the curved uneven surface Forming an isolation layer in an inactive region of the semiconductor substrate, laminating a gate insulating film and a gate electrode over the active region of the semiconductor substrate, and a substrate active region of the curved uneven surface separated from each other by the gate electrode. Forming a source / drain region within the substrate.
In order to achieve the above another object, an MOS transistor having an increased channel width according to the present invention includes a semiconductor substrate having an uneven surface curved in a width direction of a gate electrode in an active region defined by an isolation layer, and disposed on the uneven surface. And a source / drain formed under the uneven surface of the semiconductor substrate on both sides of the gate electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are vertical cross-sectional views illustrating mask top views for opening active regions in a gate electrode channel length direction and an etching process using the same in the MOS transistor fabrication process according to the present invention.

2A and 2B, a trench 116 is formed in the length (l) direction of the gate electrode among the active regions 102 in which the transistor of the silicon substrate is to be formed as the semiconductor substrate 110. To this end, as shown in FIG. 2A, the active region 102 and the inactive region 100 of the substrate 110 are separated and a direction (source / drain) in which the channel length ℓ of the transistor in the active region 102 is extended is formed. A photo mask of a layout for opening the portion 104). Unexplained reference numeral 106 is a gate electrode mask.

As shown in FIG. 2B, a thin pad insulating film 112 is formed on the semiconductor substrate 110, the hard mask film 114 is stacked thereon, and the hard mask film is formed by a dry etching process using the photomask pattern of FIG. 2A. Patterning the 114 and the pad insulating layer 112 and etching the active region 102 of the substrate exposed by the patterned layers 114 and 112 to form the trench 116 long in the length (l) direction of the gate electrode. do. In this case, the trench 116 lines are arranged to intersect the width (w) direction of the gate electrode, and at least one trench active region is formed in one transistor active region, and two or more trench 116 lines are formed at predetermined intervals from each other. do.

At this time, the thickness of the trench etching is a factor that determines the on-current characteristics of the transistor, and the deeper the deeper, the on-current increases. Therefore, the limit on the depth is possible within the range that the insulation capability of the device isolation layer allows, but it is determined in consideration of the process margin.

3 is a vertical cross-sectional view showing an example of performing an H 2 annealing process on a substrate opened and etched in a channel length direction during a manufacturing process of the MOS transistor of the present invention.

Referring to FIG. 3, the patterned films 114 and 112 are removed as shown in FIG. 2B, and an H 2 annealing process is performed on the entire surface of the substrate 110 on which the trench 116 is formed at a high temperature of about 900 ° C. or more. The energy of the substrate surface is lower than the energy inside the substrate by the H2 annealing process so that the trench edge of the substrate 110 is stressed to change to the curved uneven surface 116a. This annealing process is a technique performed for trench corner rounding in the device isolation process of STI, which is a level of skill that can be known to those skilled in the art.

On the other hand, the present invention is to split the inside of the substrate active region 102 where the trench is to be formed by an ion beam or X-ray exposure process in a split form, and then, when the trench etching process is performed, Since the surface of the active region has a curved surface, a larger uneven surface area may be secured during the H2 annealing process.

4 is a vertical cross-sectional view illustrating a device isolation film forming step of the MOS transistor of the present invention.

Referring to FIG. 4, a device isolation layer 118 is formed in an inactive region 100 of a device by performing an STI device isolation process on a substrate having a part of the active region 102 having a curved uneven surface 116a. Although not shown in the drawing, a well ion implantation process may be performed in the substrate active region 102 between the device isolation layers 118 to form a well, and an ion implantation process for adjusting a threshold voltage may be used. A threshold voltage regulating impurity region is formed in the active region 102. At this time, after the threshold voltage ion implantation process, the silicon epitaxial growth (SEG) process is performed to grow silicon in the active region, thereby stably adjusting the threshold voltage characteristics of the MOS transistor while improving carrier mobility of the channel. You can.

5A and 5B are vertical cross-sectional views of a channel length and a channel width direction of a MOS transistor in which a gate electrode and a source / drain region are completed according to the present invention.

5A and 5B, an isolation layer 118 is formed in an inactive region 100 and a gate electrode and a source / source of a MOS transistor is formed on a substrate having a curved uneven surface 116a in a portion of the active region 102. Proceed with the drain manufacturing process. Accordingly, the gate insulating layer 120 is formed by thinly depositing an insulating film such as silicon oxide film (SiO 2) on the entire surface of the substrate or by performing a thermal oxidation process. Next, the doped polysilicon is deposited using the conductive layer, and the doped polysilicon is patterned by an etching process using the gate electrode mask to form the gate electrode 122, and the gate insulating layer 120 is also patterned thereunder.

Subsequently, an LDD ion implantation process is performed to form an LDD region (not shown) in the active region of the substrate between the gate electrode 122 and the device isolation layer 118, and to deposit a silicon nitride film (Si3N4) as an insulating film on the entire surface of the substrate. Dry etching may form a spacer 124 on sidewalls of the gate electrode 122 and the gate insulating layer 120. The source / drain ion implantation process is then performed to form the source / drain regions 126 in the substrate active region separated from each other by the gate electrode 122 and the spacer 124.

As shown in FIG. 5A, when the vertical cross-sectional view of the width (direction perpendicular to the length) of the gate electrode 122 is viewed in the MOS transistor completed according to the manufacturing process of the present invention, the width w of the gate electrode 122, that is, It can be seen that the width of the channel is increased in the form of curved irregularities on the surface of the active region.

According to the present invention, since the substrate surface from the source (L) direction, that is, the source to the channel length region under the gate electrode 122 in the drain region direction, the surface of the gate electrode is flat, there is no difference from the general MOS transistor characteristics. However, according to the present invention, the surface of the active region of the source / drain regions 126 is curved and irregular as shown in FIG. 5B by the photo mask for forming the trench in the channel length direction of the gate electrode, thereby increasing its surface area. The resistance of the contact electrode can be reduced by the increased area.

As described above, according to the present invention, before the device isolation process is performed, the active region where the gate electrode width of the MOS transistor is to be formed is partially etched into the trench, and the H2 annealing process is performed to change the trench active region to the curved uneven surface. Subsequently, subsequent gate insulating film, gate electrode, and source / drain fabrication processes may be performed to increase the width of the gate electrode and the surface area of the source / drain active region adjacent thereto, rather than the width of the gate electrode set in the design rule. In addition to current characteristics, channel carrier mobility can be improved.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (7)

In the manufacturing method of the MOS transistor, Forming a trench extending in a channel length direction of a gate electrode of the transistor in an active region of a semiconductor substrate; Performing an H2 annealing process on the trench-formed semiconductor substrate to make the trench portion a curved uneven surface; Forming a device isolation layer in an inactive region of the semiconductor substrate and stacking a gate insulating layer and a gate electrode on the substrate active region between the device isolation layers; And And forming a source / drain region in the substrate active region of the curved concave-convex surface separated from each other by the gate electrode. The method of claim 1, wherein the forming of the trench comprises splitting a curved surface of the active region during the trench etching of the active region after splitting the inside of the active region in which the trench is to be formed by an ion beam or X-ray exposure process. A method of manufacturing a MOS transistor with increased channel width, characterized in that it has. 2. The method of claim 1, wherein the trench is long to cross the width direction of the gate electrode. The method of claim 1, wherein at least one trench is formed, and at least two trenches are formed at predetermined intervals from each other. The channel of claim 1, further comprising, after forming the device isolation layer, implanting impurities into an active region of a substrate and performing a silicon epitaxial growth process to form an impurity region for adjusting a threshold voltage. Method of manufacturing a MOS transistor with increased width. The method of claim 1, The step of making the trench portion a curved uneven surface, And performing a hydrogen (H ₂ ) annealing process on the trench formed semiconductor substrate. A semiconductor substrate having an uneven surface curved in the width direction of the gate electrode in an active region defined by the device isolation film; A gate insulating film and a gate electrode disposed on the uneven surface; And And a source and a drain formed under the uneven surface of the semiconductor substrate on both sides of the gate electrode.

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