KR101055587B1 - Method of manufacturing memory having 3-dimensional structure - Google Patents

Abstract

PURPOSE: A method for manufacturing memory with a three dimensional structure is provided to make a non-volatile memory device with the high degree of integration by making a three dimensional structure and forming a plurality of cell transistors in a multil active layer. CONSTITUTION: A pre-etching film and an insulating film are alternately formed. A selection insulating layer(316), a selection etching film, and a sacrificial insulating film(318) are successively formed in the upper part of the pre-etch film which is a top layer. Multi active layers(330), which are arranged into a first direction, are formed passing through the pre-etching film, the insulating layer, the selection insulating layer, the selection etching film, and the sacrificial insulating film. A cell area, in which a contact area and the multi active layers are formed, is defined. The level difference of a second direction which is vertical to the first direction is formed by the imprint of a pattern in a contact area. A plurality of string areas, which is extended toward the first direction, is formed by selectively etching the cell area after the imprint of the pattern. The selection etching film and the pre-etch film are eliminated. An ONO(Oxide-Nitride-Oxide) layer and a conductive film are formed on the side of the multi active layers.

Description

Method of manufacturing memory having three-dimensional structure {Method of manufacturing Memory having 3-Dimensional Structure}

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a memory having a three-dimensional structure.

Memory devices may be divided into nonvolatile and volatile memory. In particular, the nonvolatile memory has an advantage of maintaining stored data even when power supply is cut off. As nonvolatile memory, flash memory takes an operating mechanism whose state is changed by trapping and erasing charges. Recently, researches on device structures capable of implementing proportional reduction and multi-bit for a unit cell have been conducted.

When the degree of integration of the flash memory is improved, problems such as a short channel effect and a punchthrough phenomenon occur. To overcome this problem, a technique of implementing the structure of a flash memory in three dimensions is discussed.

1 is a perspective view illustrating a structure of a flash memory according to the prior art.

Referring to FIG. 1, a flash memory according to the related art is divided into a cell region 100 and a contact region 200.

The cell region 100 has electrode layers 121, 123, 125, and 127 sequentially stacked and insulating layers 110, 112, 114, and 116. The gate structure 130 is formed through the stacked electrode layers 121, 123, 125, and 127 and the insulating layers 110, 112, 114, and 116.

The gate structure 130 is provided with polycrystalline silicon at a central portion thereof, and has an oxide-nitride-oxide (ONO) structure toward an outer circumferential surface thereof. That is, a tunneling oxide film, a charge trap layer, and a blocking insulating film are sequentially provided outside the polycrystalline silicon. The polycrystalline silicon surrounded by the ONO structure acts as an active region or channel region in the cell transistor of the flash memory.

Select transistors 140 are disposed on the plurality of stacked electrode layers 121, 123, 125, and 127 and the insulating layers 110, 112, 114, and 116. The selection transistor 140 includes a selection electrode film 142 extended in a first direction. The selection electrode film 142 is disposed to be separated from the selection electrode film adjacent to each other in the second direction. In addition, the gate structure 144 penetrates through the select electrode film 142 and is electrically connected to the gate structure 130 penetrating through the electrode films 121, 123, 125, and 127 and the insulating films 110, 112, 114, and 116. Is connected. However, the gate structure 144 penetrating the selection electrode film 142 is composed of only polycrystalline silicon and a gate oxide film. Accordingly, the polycrystalline silicon of the gate structure 144 penetrating through the selection electrode film 142 operates as an active region or a channel region of the semiconductor, and the selection electrode film 142 operates as a gate electrode. In addition, the bit lines 150 are disposed on the gate structure 144 that penetrates the selection electrode layer 142. The bit lines 150 extend in a second direction and are separated from adjacent bit lines in the first direction.

The contact region 200 is formed in contact with the cell region 100, and is a stacked structure integrated with the electrode layers 121, 123, 125, and 127 and the insulating layers 110, 112, 114, and 116 of the cell region 100. Is formed. That is, the electrode films 121, 123, 125, and 127 and the insulating films 110, 112, 114, and 116 extend across the cell region 100 to the contact region 200. In addition, the electrode films 121, 123, 125, and 127 and the insulating films 110, 112, 114, and 116 have a step shape in which the area thereof decreases as it progresses upward. However, the first insulating film 110 and the first electrode film 121 of FIG. 1 have the same profile, and the remaining electrode film and the corresponding insulating film also have the same profile.

One side of the contact region 200 is connected to the cell region 100 because it is integrated with the electrode layers 121, 123, 125, and 127 and the insulating layers 110, 112, 114, and 116 of the cell region 100. The other side of the contact region 200 has a step according to the height, and has a structure of exposing a part of the electrode films 121, 123, 125, and 127 to the outside.

Although not shown, an interlayer insulating film is entirely applied on the electrode film, the insulating film, or the structure opened to the outside. The electrode films 121, 123, 125, and 127 protruding from the contact region 200 are connected to the plug 210. The plug 210 is formed through the coated interlayer insulating film. In addition, an upper portion of the plug 210 is connected to the word line 220. The word line 220 extends in a first direction and is spaced apart from each other in a second direction.

The prior art described above is a typical Bit-Cost Scalable (BiCS) structure. The structure forms a plug 210 contacting the word line 220 on the plurality of electrode layers 121, 123, 125, and 127 having a step. The electrode films 110, 112, 114, and 116 have a technical configuration of transferring a pattern by applying and etching the photoresist and scaling down the remaining photoresist. However, the electrode films 121, 123, 125, and 127 constituting the contact region 200 have a step parallel to a direction extending from the cell region 100. That is, the electrode film protruding from the cell region 100 extends to the electrode layer of the contact region 200 and has a structure that forms a step with other electrode films disposed below or above the stretched direction.

In particular, in order to prevent the plug 210 disposed between the word line 220 and the electrode layers 121, 123, 125, and 127 from being shorted to each other, a predetermined step should be made toward the lower end. Accordingly, the electrode films 121, 123, 125, and 127 also have a wider aspect toward the bottom of the structure.

Therefore, when the number of the electrode films 121, 123, 125, and 127 serving as the control gate of the flash memory increases, the area of the entire memory increases very much, causing loss in the degree of coherence.

An object of the present invention for solving the above problems is to provide a method of manufacturing a memory that can realize a high integration by implementing a three-dimensional structure.

The present invention for achieving the above object, the step of alternately forming a preliminary etching film and the insulating film; Sequentially forming a selective insulating layer, a selective etching layer, and a sacrificial insulating layer on the uppermost preliminary etching layer; Forming multilayer active layers penetrating the preliminary etching layer, the insulating layer, the selection insulating layer, the selection etching layer, and the sacrificial insulating layer and disposed in a first direction; Defining a contact region and a cell region in which the multilayer active layers are formed; Forming a step in a second direction perpendicular to the first direction by transferring the pattern to the contact area; Forming a plurality of string regions extending in the first direction through selective etching of the cell regions after the transfer of the pattern; And removing the selective etching layer and the preliminary etching layer, and forming an ONO layer and a conductive layer on the side surface of the multilayer active layer.

In addition, the object of the present invention, forming a preliminary etching film and the insulating film alternately; Sequentially forming a selective insulating layer, a selective etching layer, and a sacrificial insulating layer on the uppermost preliminary etching layer; Forming multilayer active layers penetrating the preliminary etching layer, the insulating layer, the selection insulating layer, the selection etching layer, and the sacrificial insulating layer and disposed in a first direction; Defining a string region by etching the region in which the multilayer active layers are formed in the first direction; Removing the selective etching layer and the preliminary etching layer, and forming an ONO layer and conductive layers on side surfaces of the multilayer active layer; After forming the ONO layer and the conductive film, defining a cell region including a contact region and a region in which the multilayer active layer etched in the first direction is formed; Forming a step in a second direction perpendicular to the first direction through transfer of the pattern to the contact area; And removing the sacrificial insulating layer exposed through the entire surface etching, and removing the selective insulating layer and the insulating layers exposed at the step, thereby exposing the conductive layers.

According to the present invention described above, the ONO layer and the conductive film are formed on the side of the multilayer active layer exposed through the removal of the selective etching film and the preliminary etching film. Through this, the cell transistor is implemented. In addition, the conductive film is made of a metallic material to control the operation of the cell transistor. A plurality of cell transistors is provided in one multilayer active layer, thereby manufacturing a high integration nonvolatile memory device.

1 is a perspective view illustrating a structure of a flash memory according to the prior art.
2 to 15 are perspective views illustrating a method of manufacturing a three-dimensional structure memory according to a first embodiment of the present invention.
16 to 23 are perspective views illustrating a method of manufacturing a memory according to a second embodiment of the present invention.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

First Example

2 to 15 are perspective views illustrating a method of manufacturing a three-dimensional structure memory according to a first embodiment of the present invention.

Referring to FIG. 2, preliminary etching layers 310, 312, 314, and 316 and insulating layers 320, 322, and 324 are sequentially stacked on a substrate (not shown). In addition, the selection insulating layer 326, the selection etching layer 318, and the sacrificial insulating layer 328 are formed on the uppermost preliminary etching layer 316. The insulating layers 320, 322, and 324, the selection insulating layer 326, and the sacrificial insulating layer 328 may be formed of the same material. In addition, a plurality of multilayer active layers 330 that pass through the stacked insulating layers 320, 322, 324, 326, and 328 and the etching layers 310, 312, 314, 316, and 318 are formed. After the multilayer active layer 330 has a stacked structure, the multilayer active layer 330 is formed by forming holes and embedding polycrystalline silicon in the holes.

The preliminary etching layers 310, 312, 314, and 316 and the selective etching layer 318 may be formed of any material having an etching selectivity with respect to the insulating layers 320, 322, and 324, the selective insulating layer 326, and the sacrificial insulating layer 328. One may be used but silicon nitride material is preferably used. In addition, the insulating layers 320, 322, 324, 326, and 328 preferably use silicon oxide.

Therefore, the first preliminary etch film 310, the first insulating film 320, and the second preliminary etch film 312 may be sequentially stacked from a substrate or other film quality not shown. In addition, according to the embodiment, the number of the insulating films 320, 322, 324 and the preliminary etching films 310, 312, 314, and 316 may be sufficiently changed by those skilled in the art.

Referring to FIG. 3, a patterned hard mask layer 340 is formed on an uppermost sacrificial insulating layer 328. Patterning of the hard mask layer 340 is by a conventional photolithography process. In addition, the contact area 300 and the cell area 305 are separated by the patterned hard mask layer 340. That is, the region opened by the hard mask layer 340 is defined as the contact region 300, and the region occluded by the hard mask layer 340 is defined as the cell region 305.

Referring to FIG. 4, a soft mask layer is formed on the hard mask layer 340 and the open cell region 300. In addition, the soft mask layer is patterned to enable transfer. The soft mask layer is preferably composed of photoresist. The patterned soft mask layer is named first transfer pattern 350.

Subsequently, the sacrificial insulating layer 328 and the selective etching layer 318 of the contact region 300 are etched using the first transfer pattern 350 and the hard mask layer 340 formed as an etching mask. By the sequential etching of the sacrificial insulating film 328 and the selective etching film 318, the sacrificial insulating film 328 and the selective etching film 318 have the same profile as the first transfer pattern 350, and the selective etching film 318. A portion of the lower selection insulating film 326 is exposed.

Referring to FIG. 5, a reduction process is performed on the first transfer pattern 350 to form a second transfer pattern 360. The reduction process is referred to as photoresist shrink or photoresist sliming, which reduces the size of the preformed photoresist. Reduction to the photoresist is achieved by exposure to reactive plasma gas. However, the reactive plasma gas may be differently selected depending on the composition of the photoresist pattern.

A portion of the sacrificial insulating layer 328 is exposed under the second transfer pattern 360 formed by the reduction process. In addition, a part of the selection insulating film 326 is exposed by the process of FIG. 4.

Subsequently, a portion of the exposed surface of the sacrificial insulating layer 328 and a portion of the selection insulating layer 326 may be etched to expose a portion of the selective etching layer 318 and a portion of the fourth preliminary etching layer 316. Therefore, the sacrificial insulating layer 328 has the same profile as the second transfer pattern 360, and the selective etching layer 318 and the selection insulating layer 326 have the same profile as the first transfer pattern 350.

Referring to FIG. 6, etching is performed on the opened selective etching layer 318 and the fourth preliminary etching layer 316. Through etching, the selective etching layer 318 has the same profile as the second transfer pattern 360, and the fourth preliminary etching layer 316 has the same profile as the first transfer pattern 350.

Referring to FIG. 7, the third transfer pattern 370 is formed by performing a reduction process on the second transfer pattern 360.

In addition, etching is performed on the open sacrificial insulating layer 328, the selection insulating layer 326, and the third insulating layer 324. Through the etching, the sacrificial insulating layer 328 has the same profile as the third transfer pattern 370 and exposes a portion of the lower selective etching layer 318. The exposed selective etching layer 318 has the same profile as the second transfer pattern 360. In addition, the selection insulating layer 326 has the same profile as the second transfer pattern 360 and exposes a portion of the lower fourth preliminary etching layer 316. The third insulating layer 324 has the same profile as the first transfer pattern 350 through etching, and exposes a portion of the lower third preliminary etching layer 314.

Referring to FIG. 8, etching is performed on the selective etching layer 318, the fourth preliminary etching layer 316, and the third preliminary etching layer 314 exposed by the etching process of FIG. 7.

Through etching, the selective etching layer 318 has the same profile as the sacrificial insulating layer 328 and the third transfer pattern 370. In addition, the fourth preliminary etching layer 316 has the same profile as the selection insulating layer 326 and has the same profile as the second transfer pattern 360. The third preliminary etching layer 314 has the same profile as the third insulating layer 324 and has the same profile as the first transfer pattern 350. As a result, a part of the surface of the second insulating layer 322 under the third preliminary etching layer 314 is exposed.

Referring to FIG. 9, the remaining transfer pattern 370 and the hard mask layer 340 are removed, and a photoresist pattern 345 is formed on the substrate. The photoresist pattern 345 is obtained by a conventional lithography process. Subsequently, etching is performed using the formed photoresist pattern 345 as an etching mask. Thus, the exposed sacrificial insulating layer 328, the selection insulating layer 326, the third insulating layer 324, and the second insulating layer 322 are etched. In particular, the sacrificial insulating layer 328 may be completely removed from the contact region 300, and the remaining insulating layers 326, 324, and 322 may have a pattern in which the pattern is transferred downward. Subsequently, the exposed selective etching layer 318, the fourth preliminary etching layer 316, the third preliminary etching layer 314, and the second preliminary etching layer 312 are etched. Thus, the structure shown in FIG. 9 is formed through two etchings. In particular, the sacrificial insulating layer 328 and the selective etching layer 318 may be recessed from the contact region 300 toward the cell region 305. As such, each of the etching layers and the insulating layers may have a shape having a stepped step by the transfer of the pattern.

Referring to FIG. 10, the photoresist pattern formed on the sacrificial insulating layer 328 is removed. The upper surface of the sacrificial insulating layer 328 is exposed by removing the photoresist pattern. In addition, ends of the multilayer active layer 330 formed through a plurality of membranes are exposed.

Referring to FIG. 11, the cell region 305 extending in the first direction is patterned through selective etching. That is, the cell region 305 is etched to etch the center of the structure shown in FIG. 10 in the first direction and partition the multilayer active layers 330 aligned in the first direction. The etching is performed until the lowermost first preliminary etching layer 310 is patterned. As a result, the string area 400 of the memory is defined.

In addition, the stepped structure constituting the contact region 300 is not etched and remains circular. However, etching is performed on the center of the structure shown in FIG. 10 so that the stepped structure is symmetrical.

Referring to FIG. 12, wet etching of the structure illustrated in FIG. 11 is performed. The selective etching layer 318 and the preliminary etching layers 310, 312, 314, and 316 are removed through wet etching. That is, since the selective etching film 318 and the preliminary etching films 310, 312, 314, and 316 have an etching selectivity with the disclosed insulating films 320, 322, 324, 326, and 328, selection of an appropriate etchant is performed. The selective etching layer 318 and the preliminary etching layers 310, 312, 314, and 316 are removed by the method. Accordingly, the multilayer active layer 330, the sacrificial insulating layer 328, the selective insulating layer 326, and the plurality of insulating layers 324, 322, and 320 remain, and a portion of the side surface of the multilayer active layer 330 is exposed.

Referring to FIG. 13, an ONO layer is deposited on the exposed side of the multilayer active layer 330. Subsequently, a conductive film is formed over the ONO layer, and the conductive layer embedded between the string regions 400 is removed. Therefore, the space between the insulating layers 328, 326, 324, 322, and 320 formed in contact with the same multilayer active layer 330 is filled with the ONO layer and the conductive layer. The conductive film is preferably made of tungsten. Accordingly, the conductive layers 410, 412, 414, 416, and 418 are formed by replacing the selective etching layer and the preliminary etching layer. That is, the first conductive film 410 to the fourth conductive film 416 are formed from the bottom, and the selective conductive film 418 is formed in the string region 400.

Referring to FIG. 14, front etching of the structure illustrated in FIG. 13 is performed. The insulating layers 328, 326, 324, 322, and 320 exposed to the outside through the entire surface etching are removed. FIG. 14 illustrates a right region separated from the structure of FIG. 13.

In FIG. 14, the top sacrificial insulating layer is removed, and a portion of the plurality of multilayer active layers 330 penetrating through it is exposed. In addition, the selection insulating layer 326 recessed toward the cell region 305 is patterned, and the third insulating layer 324, the second insulating layer 322, and the first insulating layer 320 partially exposed to the outside are removed. As a result, some surfaces of the selection conductive film 418, the fourth conductive film 416, the third conductive film 414, the second conductive film 412, and the first conductive film 410 are exposed.

Referring to FIG. 15, the selection plug 420 is formed in the multilayer active layer 330 exposed on the selection region, and the connection plug 422 is formed on the exposed conductive layers 416, 414, 412, and 410. do. In addition, the selection plug 420 is connected to each first wiring group 430, and the connection plug 422 is connected to the second wiring group 435. Of course, before forming the plugs 420 and 422 and the wiring groups 430 and 435, the memory structure is filled with an interlayer insulating film. Thus, the formation of the plugs is achieved by selective etching of the interlayer insulating film and embedding of the conductor.

As described above, in the present embodiment, the string region is provided to extend in the first direction. In addition, a step is formed in a second direction perpendicular to the first direction, and electrical connection with the wiring is made through the conductive films exposed on the step. Therefore, a higher degree of integration can be obtained as compared with the case where the string has a step formed in the same direction as the first direction in which the strings are aligned.

2nd Example

16 to 23 are perspective views illustrating a method of manufacturing a memory according to a second embodiment of the present invention.

Referring to FIG. 16, preliminary etching layers 510, 512, 514, and 516 and insulating layers 520, 522, and 524 are sequentially stacked on a substrate (not shown). In addition, the selection insulating layer 526, the selection etching layer 518, and the sacrificial insulating layer 528 are formed on the uppermost preliminary etching layer 516. The insulating layers 520, 522, and 524, the selection insulating layer 526, and the sacrificial insulating layer 528 may be formed of the same material. In addition, a plurality of multilayer active layers 530 are formed through the stacked insulating layers 520, 522, 524, 526, and 528 and the etching layers 510, 512, 514, 516, and 518. After the multilayer active layer 530 has a stacked structure, the multilayer active layer 530 is formed by forming holes and embedding polycrystalline silicon in the holes.

The preliminary etching layers 510, 512, 514, and 516 and the selective etching layer 518 may be formed of any material having an etching selectivity with respect to the insulating layers 520, 522, and 524, the selective insulating layer 526, and the sacrificial insulating layer 528. One may be used but silicon nitride material is preferably used. In addition, the insulating layers 520, 522, 524, 526, and 528 preferably use silicon oxide.

Therefore, the first preliminary etching film 510, the first insulating film 520, the second preliminary etching film 512, and the like are sequentially stacked from a substrate or other film quality not shown. In addition, the number of insulating layers 520, 522, and 524 and the preliminary etching layers 510, 512, 514, and 516 may be sufficiently changed according to the exemplary embodiment.

Referring to FIG. 17, the string region 600 is defined through selective etching of the structure disclosed in FIG. 16, and two symmetrical structures are formed by etching the central portion of the structure. Accordingly, the string region 600 has a structure extending in the first direction and is separated from the adjacent string region in the second direction.

Referring to FIG. 18, wet etching of the structure of FIG. 17 is performed. The selective etching layer 518 and the preliminary etching layers 510, 512, 514, and 516 are removed through wet etching. That is, since the selective etching layer 518 and the preliminary etching layers 510, 512, 514, and 516 have an etching selectivity with the disclosed insulating layers 520, 522, 524, 526, and 528, selection of an appropriate etchant is performed. The selective etching layer 518 and the preliminary etching layers 510, 512, 514, and 516 are removed by the method. Accordingly, the multilayer active layer 530, the sacrificial insulating layer 528, the selective insulating layer 526, and the plurality of insulating layers 520, 522, and 524 remain, and a portion of the side surface of the multilayer active layer 530 is exposed.

Referring to FIG. 19, an ONO layer is deposited on the exposed side of the multilayer active layer 530. Subsequently, a conductive film is formed over the ONO layer, and the conductive film embedded between the string regions 600 is removed. Therefore, the space between the insulating layers 520, 522, 524, 526, and 528 formed in contact with the same multilayer active layer 530 is filled with the ONO layer and the conductive layers 610, 612, 614, 616, and 618. The conductive films 610, 612, 614, 616, and 618 are preferably made of tungsten. Accordingly, the conductive layers 610, 612, 614, 616, and 618 are formed to replace the selective etching layer 518 and the preliminary etching layers 510, 512, 514, and 516. That is, the first conductive films 610 to 4th conductive films 616 are formed from the bottom, and the selective conductive film 618 is formed in the string region 600.

Referring to FIG. 20, a portion of the upper portion of the structure in which the ONO layer and the conductive layer 618 are formed is etched to form a hard mask layer 540. That is, the sacrificial insulating film 528 and the selective conductive film 618 recessed into the cell region 505 are formed through partial etching of the sacrificial insulating film 528 and the selective conductive film 618, and the sacrificial insulating film 528 is formed. And a hard mask layer 540 covering the upper portion of the selective conductive film 618. The hard mask layer 550 is formed to open the contact region 500.

Referring to FIG. 21, a first transfer pattern 550 is formed on the hard mask layer 540 and on the contact region 500. When the first transfer pattern 550 is formed, the transfer pattern formed through the sequential etching and the transfer pattern is transferred downward. The result of this process is disclosed in FIG. 22.

That is, as described in FIGS. 4 to 9 of the first embodiment, the first conductive film 610, the first insulating film 520, the second conductive film 612, the second insulating film 522, and the third from the bottom. A structure is formed in which the conductive film 614, the third insulating film 524, the fourth conductive film 616, and the selective insulating film 526 have constant steps. In addition, each of the conductive layers 610, 612, 614, and 616 and the insulating layers 520, 522, 524, and 526 have the same profile in pairs.

Referring to FIG. 22, the transfer pattern and the hard mask layer formed thereon are removed. Thus, the string region 600 and the contact region 500 are exposed to the outside.

Referring to FIG. 23, the front surface etching of the structure illustrated in FIG. 22 is performed. The sacrificial insulating layer 528 on the string region 600 is removed through the entire surface etching. In addition, the selection conductive layer 618 under the sacrificial insulating layer 528 is opened, and the selection insulating layer 526 under the selection conductive layer 618 is etched to have the same profile as the selection conductive layer 618.

The insulating layers exposed to the outside through the entire surface etching are removed. Accordingly, the selection conductive layer 618 and the first to fourth conductive layers 610, 612, 614, and 616 are opened in the contact region 500. A portion of the multilayer active layer 530 that penetrates the structure with the openings of the conductive layers 610, 612, 614, 616, and 618 appears to protrude from the select conductive layer 618. This is shown in FIG.

In addition, the formation of the plug for forming the memory, the formation of the bit line and the word line is the same as that described in Fig. 15 of the first embodiment.

In this embodiment, the string region is provided to extend in the first direction. In addition, a step is formed in a second direction perpendicular to the first direction, and electrical connection with the wiring is made through the conductive films exposed on the step. Therefore, a higher degree of integration can be obtained as compared with the case where the string has a step formed in the same direction as the first direction in which the strings are aligned.

Therefore, according to the present invention, the cell region and the contact region are divided by the presence or absence of a step, and the step is made in a direction perpendicular to the direction in which the string is formed. Therefore, a higher degree of integration can be obtained than in the prior art in which the step is advanced in the same direction as the string is formed. In particular, a plurality of memory cells may be formed in one string by wet etching, removing an etching layer, forming an ONO layer, and forming a conductive layer.

In the present invention, the lowermost part of the plurality of multilayer films is shown as a conductive film. However, this is for convenience of explanation, and a different kind of film quality may be disposed under the conductive film, and the first conductive film disposed at the lowermost part may control the operation of the cell transistors constituting the memory together with the string selection region. Can be used.

300, 500: contact area 305, 505: cell area
320, 322, 324, 520, 522, 524: first to third insulating films
316 and 516 Selective insulating film 318 and 518 Sacrificial insulating film
330, 530: multilayer active layer 400, 600: string region
418 and 618: selective electrode film

Claims (10)

Alternately forming a preliminary etching film and an insulating film;
Sequentially forming a selective insulating layer, a selective etching layer, and a sacrificial insulating layer on the uppermost preliminary etching layer;
Forming multilayer active layers penetrating the preliminary etching layer, the insulating layer, the selection insulating layer, the selection etching layer, and the sacrificial insulating layer and disposed in a first direction;
Defining a contact region and a cell region in which the multilayer active layers are formed;
Forming a step in a second direction perpendicular to the first direction by transferring the pattern to the contact area;
Forming a plurality of string regions extending in the first direction through selective etching of the cell regions after the transfer of the pattern; And
Removing the selective etching layer and the preliminary etching layer, and forming an ONO layer and a conductive layer on side surfaces of the multilayer active layer. The method of claim 1, wherein the defining of the contact area and the cell area comprises:
And forming a hard mask layer on the sacrificial insulating layer to cover the multilayer active layer. The method of claim 1, wherein the removal of the selective etching layer and the preliminary etching layer is performed by wet etching, and the insulating layer, the selective insulating layer, the sacrificial insulating layer, and the multilayer active layers remain by the wet etching. Memory manufacturing method. The method of claim 1, wherein the forming of the ONO layer and the conductive film,
And forming a conductive film filling the insulating films, and forming a conductive film filling the sacrificial insulating film and the selective insulating film. The method of claim 4, wherein after forming the ONO layer and the conductive film,
And etching the exposed sacrificial insulating film, the selection insulating film, and the insulating films. The method of claim 5, wherein the sacrificial insulating layer is removed by the etching, and the selection insulating layer has the same profile as the selection conductive layer. Alternately forming a preliminary etching film and an insulating film;
Sequentially forming a selective insulating layer, a selective etching layer, and a sacrificial insulating layer on the uppermost preliminary etching layer;
Forming multilayer active layers penetrating the preliminary etching layer, the insulating layer, the selection insulating layer, the selection etching layer, and the sacrificial insulating layer and disposed in a first direction;
Defining a string region by etching the region in which the multilayer active layers are formed in the first direction;
Removing the selective etching layer and the preliminary etching layer, and forming an ONO layer and conductive layers on side surfaces of the multilayer active layer;
After forming the ONO layer and the conductive film, defining a cell region including a contact region and a region in which the multilayer active layer etched in the first direction is formed;
Forming a step in a second direction perpendicular to the first direction through transfer of the pattern to the contact area; And
Removing the sacrificial insulating layer exposed through the entire surface etching, and removing the selective insulating layer and the insulating layers exposed at the step to expose the conductive layers. The method of claim 7, wherein the removal of the selective etching layer and the preliminary etching layer is performed by wet etching, and the insulating layer, the selective insulating layer, the sacrificial insulating layer, and the multilayer active layers remain by the wet etching. Memory manufacturing method. The method of claim 7, wherein forming the ONO layer and the conductive film,
And forming a conductive film filling the insulating films, and forming a conductive film filling the sacrificial insulating film and the selective insulating film. The method of claim 9, wherein the selection insulating layer has the same profile as the selection conductive layer by removing the sacrificial insulating layer.

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