KR101006446B1 - Analog amplifier for flat panel display and driving method thereof - Google Patents

Abstract

The present invention relates to an analog amplifier for a flat panel display and a driving method thereof capable of providing a constant output voltage regardless of a change in the threshold voltage of a transistor.

A transistor having a predetermined voltage, and a capacitor storing a predetermined voltage of the transistor, wherein the transistor includes a first terminal connected to a first end of the capacitor, a second terminal connected to a first voltage, and a current source. And a third terminal connected to the second voltage through the second terminal.

In this manner, by storing the threshold voltage in advance in the capacitor and canceling the threshold voltage from the output voltage, a constant output voltage can be obtained regardless of the change of the threshold voltage.

LCD, Switching Device, Transistor, Capacitor, Threshold Voltage, Polycrystalline, Monocrystalline, Amorphous, SOG

Description

Analog amplifier for flat panel display and its driving method {ANALOG AMPLIFIER FOR FLAT PANEL DISPLAY AND DRIVING METHOD THEREOF}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 illustrates an example of an SOG type liquid crystal display device according to an exemplary embodiment of the present invention.

4 is a block diagram of a data driver of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is an example of an analog amplifier circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 is a timing diagram illustrating on / off timings of the switching element illustrated in FIG. 5.

7 is an example of an analog amplifier circuit of a liquid crystal display according to another exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog amplifier for a flat panel display and a driving method thereof, and more particularly, to an analog amplifier circuit for a liquid crystal display device and a driving method thereof.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

On the other hand, amorphous, polycrystalline and monocrystalline silicon are used as the material of such TFTs.

Amorphous silicon (hereinafter referred to as 'a-Si') TFT-LCD is a liquid crystal panel assembly provided on a substrate, a data driver IC for driving the liquid crystal panel assembly, a gate driver IC and a printed circuit board for connecting them It is provided. Such a-Si TFT-LCD has only a pixel in the liquid crystal panel assembly due to low electric field mobility, and separately fabricates a driver IC and mounts it on a glass substrate.

In contrast, poly-silicon (poly silicon) TFT-LCD includes a liquid crystal panel assembly, a data driver IC for driving the liquid crystal panel assembly, and a gate driver IC on a glass substrate. Such poly-Si TFT-LCD integrates driving circuits such as data driver IC and gate driver IC in the liquid crystal panel assembly on the glass substrate, greatly reducing the number of signal lines connected to the outside, improving product reliability and significantly reducing production costs. Can be. In addition, due to the high electric field mobility, the poly-Si TFT having a smaller size than that of the a-Si TFT is used as the switching element of the pixel. For this reason, research on Poly-Si TFT-LCDs is being actively conducted.

The biggest advantage of Poly-Si TFT-LCD is that it can embed a circuit composed of MOS transistors on a low-cost glass substrate used in a-Si TFT-LCD. Currently, low temperature polycrystalline silicon (LTPS) technology can be used to form all of the gate driver ICs or portions of each of the gate driver and data driver ICs on a glass substrate, and further, the entire system including a signal controller. A system on glass (SOG) for integrating on a glass substrate has also been possible.

On the other hand, although there are various obstacles in moving to such SOG, most of the semiconductor elements used in the driving circuit, in particular, is a MOS transistor having a threshold voltage.

The MOS transistor has a threshold voltage between the gate terminal and the source terminal for the on / off operation, which is expressed as a function of the thickness of the gate insulating film formed between the gate electrode and the channel region, the doping concentration of the channel, and the like. . However, these factors may be uneven or change depending on process conditions.

This nonuniformity and change in threshold voltage have a great effect on the operation of the circuit, causing the circuit to malfunction or distort the output.

Accordingly, an object of the present invention is to provide an analog amplifier for a flat panel display device that can operate regardless of a variation or change in threshold voltage.

According to an aspect of the present invention, an analog amplifier for a flat panel display includes a transistor having a predetermined voltage, and a capacitor storing a predetermined voltage of the transistor, wherein the transistor comprises a first stage of the capacitor. And a third terminal connected to the first terminal, a second terminal connected to the first voltage, and a third terminal connected to the second voltage through a current source.

In addition, the first switching element is connected between the second terminal and the third voltage of the capacitor, the second switching element is connected between the third terminal of the transistor and the second end of the capacitor, the second end of the capacitor and The display device may further include a third switching device connected between the fourth voltages, and a fourth switching device connected between the first end of the capacitor and the fourth voltage.

Here, at a first time point, the first, second and fourth switching devices are turned on, at a second time point, the first switching device is turned off, and at a third time point, the second and fourth switching devices are turned off. And the third switching element is turned on.                     

Meanwhile, first and second ends of the capacitor may be selectively connected to the fourth voltage.

In this case, the capacitor and the transistor are connected in parallel at the first time point to receive the third and fourth voltages, respectively, at both ends thereof, and are separated from the third voltage at the second time point. The voltage of the third terminal of the transistor may be output by being separated from the fourth voltage and receiving an input voltage.

Meanwhile, when the first voltage is a driving voltage and the second voltage is a ground voltage, the transistor is an NMOS transistor, the first voltage is a ground voltage, and the second voltage is a driving voltage. The transistor is a PMOS transistor.

The flat panel display may be a liquid crystal display, and may be a system on glass (SOG) type.

A method of driving an analog amplifier for a flat panel display according to another embodiment of the present invention includes a capacitor and a transistor, storing the threshold voltage of the transistor in the capacitor, applying an input voltage to one terminal of the capacitor. And outputting a terminal voltage of the second transistor.

The storing of the threshold voltage may include charging the capacitor with a voltage greater than the threshold voltage, and connecting the capacitor in parallel with the transistor.

According to another exemplary embodiment of the present invention, an analog amplifier for a flat panel display includes a transistor having a threshold voltage and a capacitor storing a threshold voltage of the transistor, wherein the transistor is controlled connected to a first end of the capacitor. A terminal, an input terminal connected to the first voltage, and an output terminal connected to the second voltage through a current source. Here, the second end of the capacitor may be connected to an input voltage, and the input voltage is preferably greater than a target data voltage.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

An analog amplifier for a flat panel display according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention. 3 illustrates an example of an SOG type liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a block diagram of a data driver of the liquid crystal display according to the exemplary embodiment.                     

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminals are connected to the liquid crystal capacitor (C _LC ) and the holding capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

Polarizers (not shown) for polarizing light are attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n .

As illustrated in FIG. 4, the data driver 500 may include a shift register 501, a first latch 503, a second latch 505, a digital-to-analog converter (DAC) 507, and an output buffer 509. It is connected to the data line (D ₁ -D _m ) of the liquid crystal panel assembly 300, and selects the gray voltage from the gray voltage generator 800 to apply to the pixel as a data signal, and consists of a plurality of integrated circuits .

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

In the example shown in FIG. 3, the data driver 500 and the gate driver 400 are integrated in the liquid crystal panel assembly 300, and the signal controller 600 is mounted to the assembly 300 on the substrate in the form of a chip. have. In the drawing, the power supply IC 700 is a circuit element that generates the above-described gate on voltage Von and gate off voltage off. The display area refers to an area where pixels and signal lines G ₁ -G _n and D ₁ -D _m are disposed.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV for controlling the output timing of the gate on pulse, and a gate on pulse. An output enable signal OE or the like that defines a width.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal (LOAD), an inverted signal (RVS) that inverts the polarity of the data voltage with respect to the common voltage (V _com ) (hereinafter referred to as "polarity of the data voltage" by reducing the "polarity of the data voltage for the common voltage") and Data clock signal HCLK and the like.

The shift register 501 of the data driver 500 receives the data clock signal HCLK and the horizontal synchronizing start signal STH from the signal control unit 600 and sequentially shifts the horizontal synchronizing start signal STH to the first latch ( 503).

The first latch 503 sequentially receives the image data R ', G', and B 'corresponding to the pixels in a row based on the signal from the shift register 501 and sends it down to the second latch 505. .

The second latch 505 stores the image data R ', G', and B 'and sends the image data to the DAC 507 according to a predetermined signal. There may be a number of predetermined signals. In FIG. 4, an output enable signal OE is illustrated.

The DAC 507 selects a gray voltage corresponding to each of the image data R ', G', and B 'among the gray voltages from the gray voltage generator 800, thereby making the image data R', G ', and B' different. ) Is converted into a corresponding data voltage, and the converted data voltage is an analog signal.

The output buffer 509 amplifies the data voltage from the DAC 507. This amplification operation will be described later in detail.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame is started and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to the polarity of the previous frame. "). In this case, the polarity of the data voltage flowing through one data line may be changed (“column inversion”) or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( "Dot reversal")

As described above, the data driver 500 of the liquid crystal display outputs an image signal converted into an analog signal through the DAC 507 through the output buffer 509 as a data line. Since the output buffer 509 is formed of an analog amplifier, the embodiment of the present invention is referred to as an analog amplifier. Hereinafter, the structure and operation of the analog amplifier will be described in detail with reference to FIGS. 5 to 7.

FIG. 5 is an example of an analog amplifier of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 6 is a timing diagram illustrating an on / off timing of the switching element illustrated in FIG. 5. 7 is an example of an analog amplifier of a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 5, the analog amplifier 509 includes a plurality of switching elements SW1-SW4, a capacitor C, and a transistor N1.

The transistor N1 is an NMOS transistor, the first terminal of which is connected to the switching element SW4 with the input voltage Vin through the element, the second terminal of which is connected to a constant driving voltage V _DD , and the third terminal. Is connected to ground via a constant current source (I).

Both ends of the capacitor C are connected to the input voltage V _in through the switching elements SW3 and SW4, respectively, and are respectively connected to the third terminal of the transistor N1 through the switching element SW2. .

Next, the operation of the analog amplifier 509 will be described.

First, all the switching elements except for the switching element SW3 are turned on at a time t ₁ . Then, current flows through the turned-on switching elements SW1 and SW2 so that the capacitor C is charged with a voltage corresponding to the voltage difference between the node A and the node B. FIG.

Here, Vc is the initial value _{(V in (initial))} of the capacitor (C) and the voltage across, V _{in (initial)} input voltage (V _in). At this time, the difference between the initial value V _{in (initial)} and the predetermined voltage V ₁ must be a size capable of turning on the transistor N1. That is, the value is larger than the value obtained by adding the rated threshold voltage and the error of the transistor N1 (this is referred to as an "effective threshold voltage").

In this way, when the voltage value is adjusted by the two voltages V _in and V ₁ , a wide range of selection for adjustment can be made, and precise adjustment is possible.

When the voltage Vc becomes equal to or greater than the effective threshold voltage of the transistor N1, the transistor N1 is turned on, and then the switching element SW1 is turned off at a time t ₂ . The capacitor C and the transistor N1 then form a closed circuit. The capacitor C decreases the voltage while flowing a current through the transistor N1, and reaches a voltage corresponding to the effective threshold voltage of the transistor N1. At this time, the transistor N2 is turned off to be in an open state, and the capacitor C stores the effective threshold voltage V _th2 of the transistor N1.

Next, at time t ₃ , only the switching device SW3 is turned on and the remaining switching devices SW1, SW2, and SW4 are all turned off, and the size of the input voltage V _in is changed to V _{in (final)} . Since the input voltage V _in is applied to the node B, the node A voltage becomes a value obtained by adding the voltage charged to the capacitor C and the input voltage V _{in (final)} .

On the other hand, an NMOS transistor is generally composed of three terminals, a gate, a source, and a drain. A channel region exists between the source and the drain, and an insulating film is interposed between the channel region and the gate. Since transistor N1 operates in a saturation area, that is, an active area, as is known, an NMOS transistor can be equivalently replaced by a voltage controlled current source. In FIG. 5, the current flowing between the drain, which is the second terminal of the transistor N1, and the source, which is the third terminal, is the same as that of the constant current source I.                     

Where W and L are the width and length of the channel region, μ is the electron mobility, and C is the capacitance per unit area of the insulating film located under the gate. V _gs is the difference between the gate voltage and the source voltage, and V _th1 is the effective threshold voltage of the transistor N1. At this time, the voltage between the gate source (V _gs ) is V _gs = V _A -V _out ,

Substituting Equation 3 into Equation 5,

Becomes

Therefore, if V _{in (final)} = Vd + (2I / k) ^1/2 , V _out = Vd. For example, when the image data is converted into an analog voltage by the DAC 507, the target data voltage is converted into a value obtained by adding a voltage corresponding to the second right term to the target data voltage in advance. The output voltage V _out then becomes the target data voltage.

Next, the above-described operation is repeated one time (t _4), all the switching elements (SW1-SW4) are turned-off time (t _5).

The above-described switching elements SW1-SW4 may also be implemented with MOS transistors.

As such, if the effective threshold voltage of the transistor N1 is stored in the capacitor C, the output voltage V _out is independent of the threshold voltage of the transistor N1, and thus the threshold according to the process conditions during the manufacturing of the transistor N1. A constant output voltage can be obtained even if the voltage is not uniform or changes.

7 is an example of implementing an analog amplifier of a liquid crystal display according to another exemplary embodiment of the present invention using a PMOS transistor. The structure thereof is symmetrical with the NMOS transistor shown in FIG.

At the time t ₁ , all other switching elements except the switching element SW3 are turned on, and the voltage Vc across the capacitor C is a difference between the input voltage V _{in (initial} ) and the predetermined voltage V ₁ . .

When the switching element SW1 is turned off at time t ₂ , the capacitor C and the transistor P1 form a closed circuit, and the voltage charged in the capacitor C reaches the threshold voltage of the transistor P1. Decreases.

At time t ₃ , switching element SW3 is turned on and switching elements SW2 and SW4 are turned off. Then, the input voltage V _{in (final)} is applied to the node B so that the node A voltage is the sum of the previous charging voltage and the node B voltage. Since the node A voltage is the voltage of the gate terminal which is the first terminal, the transistor P1 is turned on.

When the voltage Vc across the capacitor C becomes equal to or greater than the threshold voltage of the transistor P1, the transistor P1 is turned on, and then the switching element SW1 is turned off at a time t ₂ . The capacitor C and the transistor P2 then form a closed circuit. The capacitor C decreases the voltage while flowing a current through the transistor P1, and reaches a voltage corresponding to the effective threshold voltage of the transistor P1. At this time, the transistor P1 is turned off to be in an open state, and the capacitor C stores the effective threshold voltage V _th1 of the transistor P2.

Next, at time t ₃ , only the switching device SW3 is turned on and all the remaining switching devices are turned off and the size of the input voltage V _in is changed to V _{in (final)} . Since the input voltage V _in is applied to the node B, the node A voltage becomes a value obtained by adding the voltage charged to the capacitor C and the input voltage V _{in (final)} .

On the other hand, since the transistor P1 operates in the active region, the PMOS transistor can be equivalently replaced by a voltage controlled current source. At this time, the current flowing between the drain terminal, which is the second terminal of the transistor P1, and the source terminal, which is the third terminal, is the same as that of the constant current source I. Therefore, as shown in FIG. in summary with respect to _{V out), V out = V} in (final) - is a (2I / k) ^1/2. Therefore, if V _{in (final)} = Vd + (2I / k) ^1/2 , V _out = Vd. In other words, the output voltage V _out becomes the target data voltage.

As described above, even if the threshold voltage of the transistor is uneven or varies, the input voltage can be output as a constant voltage.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

For example, the present invention can be applied to a device requiring an analog amplifier insensitive to a change in threshold voltage, for example, a flat panel display such as an organic light emitting display (OLED).

In other words, the structure of the OLED is almost the same as that of the liquid crystal display except that the organic EL element is disposed in the pixel so that the organic EL element emits light by flowing a current proportional to the applied data voltage. The OLED includes a column driver corresponding to the data driver of the liquid crystal display, converts a digital signal into an analog signal, and then amplifies and applies the digital signal to the pixel. Again, an analog amplifier is needed that is independent of the change in the threshold voltage.

Claims (14)

Input terminal, Output terminal, Transistors, and Capacitor Including; The transistor includes a gate terminal connected to the first end of the capacitor, a drain terminal connected to the first voltage, and a source terminal connected to the second voltage through a current source. A first end and a second end of the capacitor are each selectively connected to the input terminal, A source terminal of the transistor is selectively connected to a second end of the capacitor, A source terminal of the transistor is connected to the output terminal Analog amplifier for flat panel displays. In claim 1, A first switching element connected between the second end of the capacitor and a third voltage, A second switching element connected between the source terminal of the transistor and the second end of the capacitor, A third switching element connected between the second end of the capacitor and the input terminal, and A fourth switching element connected between the first end of the capacitor and the input terminal, Further comprising Analog amplifier for flat panel displays. In claim 2, At a first time point, the first, second and fourth switching devices are turned on. At a second time point, the first switching device is turned off. At a third time point, the second and fourth switching devices are turned off and the third switching devices are turned on. Analog amplifier for flat panel displays. delete In claim 1, The capacitor and the transistor Connected in parallel at the first time point, A first end of the capacitor receives a first input voltage from the input terminal, The second end of the capacitor receives a third voltage, Separate from the third voltage at the second time point, The first end of the capacitor is separated from the input terminal at the third time point, The second end of the capacitor receives a second input voltage from the input terminal Analog amplifier for flat panel displays. In claim 1, The first voltage is a driving voltage and the second voltage is a ground voltage, The transistor is an NMOS transistor Analog amplifier for flat panel displays. In claim 1, The first voltage is a ground voltage and the second voltage is a driving voltage, The transistor is a PMOS transistor Analog amplifier for flat panel displays. In claim 1, And said flat panel display is a liquid crystal display. In claim 8, And the flat panel display is a SOG (system on glass). A method of driving the analog amplifier for flat panel display of claim 1, Storing the effective threshold voltage of the transistor in the capacitor, and Connecting the second end of the capacitor to the input terminal to apply an input voltage Analog amplifier driving method for a flat panel display device comprising a. In claim 10, The effective threshold voltage storage step Charging the capacitor with a voltage greater than the effective threshold voltage, and Connecting the capacitor in parallel with the transistor Analog amplifier driving method for a flat panel display device comprising a. delete delete In claim 10, And the input voltage is larger than an output voltage output from the output terminal.

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