KR100961951B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

Forming a gate line on the substrate, sequentially laminating a gate insulating film and a semiconductor layer on the gate line, depositing a lower conductive film and an upper conductive film on the semiconductor layer, photographing the upper conductive film, the lower conductive film, and the semiconductor layer Etching, depositing a protective film, photolithography the protective film to expose the first and second portions of the upper conductive film, and removing the first and second portions of the upper conductive film to remove the first and second portions of the lower conductive film. Exposing two portions, forming a pixel electrode covering the first portion of the lower conductive layer, and removing a second portion of the lower conductive layer to expose a portion of the semiconductor layer, defined as a gate line and a data line. On the exposed portion of the semiconductor layer of any of the plurality of pixels to form a first spacer pillar by slit exposure, half of the other pixels Method of manufacturing a TFT array panel to above the exposed portions of the layer to form a second pole gap material to complete the exposure.

Thin film transistor display panel, spacer

Description

Thin film transistor array panel and manufacturing method thereof

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor substrate illustrated in FIG. 1 taken along lines IIa-IIa 'and IIb-IIb',

3, 5, 7, and 10 are layout views of the thin film transistor array panel at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 1, 2A, and 2B according to an embodiment of the present invention. The drawings are listed in order,

4A and 4B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 3 taken along lines IVa-IVa 'and IVb-IVb', respectively.

6A and 6B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 5 taken along lines VIa-VIa 'and VIb-VIb', respectively.

8A and 8B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along lines VIIIa-VIIIa 'and VIIIb-VIIIb', respectively.

9A and 9B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along the lines VIIIa-VIIIa 'and VIIIb-VIIIb', respectively, and are views of the next steps of FIGS. 8A and 8B.

11A and 11B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 10 taken along lines XIa-XIa 'and XIb-XIb', respectively.

12A and 12B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 10 taken along the lines XIa-XIa 'and XIb-XIb', respectively, and are views of the next steps of FIGS. 11A and 11B.

FIG. 13 is a view showing a thin film transistor array panel in which a second spacer pillar is formed in one pixel of six pixels, and a first spacer pillar is formed in five pixels.

FIG. 14A is a view illustrating forming a first spacer pillar by slit exposure, and FIG. 14B is a view illustrating forming a second spacer pillar by full exposure.

<Description of the symbols for the main parts of the drawings>

110: substrate 121, 129: gate line

124: gate electrode 140; Gate insulating film

151, 154: semiconductors 161, 163, 165: ohmic contact members

171, 179: data line 173: source electrode

175: drain electrode 180: protective film

181, 182, 185: contact hole 189: opening

190: pixel electrode 81, 82: contact auxiliary member

321: first spacer column 322: the second spacer column

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. Install on the display panel.

Such a liquid crystal display panel has a layered structure in which a plurality of conductive layers and an insulating layer are stacked. The gate line, the data line, and the pixel electrode are made of different conductive layers (hereinafter referred to as gate conductors, data conductors, and pixel conductors, respectively) and separated into insulating layers, which are generally arranged in order from the bottom.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array panel and a method of manufacturing the same, in which the density of the spacer pillar is adjusted to facilitate liquid crystal injection.

A method of manufacturing a thin film transistor array panel according to the present invention includes forming a gate line on a substrate, sequentially laminating a gate insulating film and a semiconductor layer on the gate line, and depositing a lower conductive film and an upper conductive film on the semiconductor layer. Photoetching the upper conductive layer, the lower conductive layer and the semiconductor layer, depositing a passivation layer on the gate insulating layer and the upper conductive layer, and etching the passivation layer to expose the first portion of the upper conductive layer. Forming an opening for exposing a first contact hole and a second portion of the upper conductive layer, removing the first and second portions of the upper conductive layer to expose the first and second portions of the lower conductive layer, A pixel electrode covering the first portion of the lower conductive layer exposed through the first contact hole of the protective layer is formed. And exposing the protrusion of the semiconductor layer by removing the second portion of the lower conductive layer exposed through the opening of the passivation layer, wherein any of a plurality of pixels defined as a gate line and a data line is included. It is preferable to form a first spacer column by slit exposure on the exposed portion of the semiconductor layer of the above, and a second spacer pillar by full exposure on the exposed portion of the semiconductor layer of the other pixels.

In the protective film photolithography step, the first portion of the upper conductive layer and the gate insulating layer adjacent thereto may be exposed together.

In the forming of the pixel electrode, the pixel electrode may be formed by covering the first portion of the lower conductive layer and the exposed gate insulating layer together.

In the protective film photolithography step, it is preferable to form a second contact hole exposing the end portion of the upper conductive film.

In addition, in the removing of the upper conductive layer, it is preferable to remove the end portion of the upper conductive layer to expose the end portion of the lower conductive layer.

In addition, the gate line preferably includes a lower layer and an upper layer.

In addition, the gate insulating layer may be etched together in the passivation layer photolithography to expose the upper layer at the end of the gate line.

In addition, in the removing of the upper conductive layer, it is preferable to remove the exposed portion of the upper layer at the end of the gate line to expose the lower layer at the end of the gate line.

The method may further include forming a contact auxiliary member covering an end portion of the lower conductive layer and an exposed portion of the lower layer at the end portion of the gate line.

In addition, the upper layer and the upper conductive layer of the gate line are preferably made of the same material.

The upper layer and the upper conductive layer of the gate line may be made of Cr, and the lower layer and the lower conductive layer of the gate line may be made of Al or Al-Nd alloy.

In addition, the semiconductor layer may include an intrinsic semiconductor film and an impurity semiconductor film, and further comprising removing the exposed portion of the impurity semiconductor film after removing the lower conductive film.                     

A thin film transistor array panel according to the present invention includes a substrate, a gate line formed on the substrate and including a lower layer and an upper layer, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a semiconductor layer on the semiconductor layer. A resistive contact member formed on the resistive contact member, a source electrode and a drain electrode formed on the resistive contact member and including a lower layer and an upper layer, and formed on the source electrode and the drain electrode; A protective film having a first contact hole for exposing and an opening for exposing a protrusion of the semiconductor layer, and a pixel electrode formed on the protective layer and contacting a lower layer of the drain electrode through the first contact hole; Set by lines and data lines The re-pillar first gap is formed of one of a plurality of pixels the pixel formed on the exposed portion of the semiconductor layer, and it is preferable that the second gap material column above the exposed portion of the semiconductor layer of the other pixel is formed.

In addition, it is preferable that the boundary of the opening coincides with the boundary of the protrusion of the semiconductor layer.

In addition, it is preferable that the boundary of the drain electrode upper film coincides with the boundary of the first contact hole.

In addition, the lower layer at the end of the gate line is exposed to the outside of the upper layer, the protective layer further has a second contact hole for exposing the lower layer at the end of the gate line, the boundary of the lower layer at the end of the gate line is It is preferable to coincide with the boundary of the second contact hole.

In addition, it is preferable to further include a contact auxiliary member covering the lower layer of the end of the gate line.

The lower layer of the gate line and the data line is made of Cr, and the upper layer of the gate line and the data line is made of Al.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1, 2A, and 2B.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B illustrate the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively. One cross section.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a portion of each gate line 121 protrudes upward to form a plurality of gate electrodes 124.

The gate line 121 includes two layers having different physical properties, that is, a lower layer and an upper layer thereon. The upper layer is made of a metal having a low resistivity, such as aluminum (Al) or an aluminum alloy, so as to reduce the delay or voltage drop of the gate signal. In contrast, the underlayer is a material having excellent physical, chemical and electrical contact properties with other materials, in particular indium tin oxide (ITO) or indium zinc oxide (IZO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum-tungsten (MoW). ) Alloy], and chromium (Cr). Preferred examples of the combination of the lower layer and the upper layer include two layers etched under different etching conditions such as Cr / Al, Cr / Al-Nd alloy, and the like. In FIGS. 2A and 2B, the lower and upper layers of the gate electrode 124 are denoted by reference numerals 124p and 124q, respectively. The lower and upper layers of the end portion 129 of the gate line 121 for contact with other portions are respectively represented. Reference numerals 129p and 129q are denoted, and a portion of the upper layer 129q of the end portion 129 is removed to expose the lower layer 129p.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 124.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined, and the inclination angle is 30 to 80 degrees.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165, respectively.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from both data lines 171 to both sides of the drain electrode 175 form a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.                     

The data line 171 and the drain electrode 175 also include the lower layers 171p and 175p and the upper layers 171q and 175q disposed thereon. As in the case of the gate line 121, a preferred example of the combination of the lower layers 171p and 175p and the upper layers 171q and 175q may be etched under different etching conditions such as Cr / Al, Cr / Al-Nd alloy, or the like. Two layers. In FIGS. 2A and 2B, the lower and upper layers of the source electrode 173 are denoted by reference numerals 173p and 173q, respectively. The lower and upper layers of the end portion 179 of the data 171 for contacting with other portions are shown, respectively. Reference numerals 179p and 179q indicate that a portion of the upper layer 179q of the end portion 179 is removed to expose the lower layer 179p.

The lower layers 171p and 175p and the upper layers 171q and 175q of the data line 171 and the drain electrode 175 are also inclined at an angle of about 30 to 80 °, similarly to the gate line 121.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 in the lower portion thereof, the data line 171 and the drain electrode 175 in the upper portion thereof, and serve to lower the contact resistance therebetween. The semiconductor 151 has a planar shape substantially the same as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 below the semiconductor 151 except for the protrusion 154 where the thin film transistor is located.

On the data line 171 and the drain electrode 175, a-Si: C formed by plasma enhanced chemical vapor deposition (PECVD), an organic material having excellent planarization characteristics, and having photosensitivity: A passivation layer 180 made of a low dielectric constant insulating material such as O, a-Si: O: F, or silicon nitride, which is an inorganic material, is formed.

The passivation layer 180 includes a plurality of contact holes 182 exposing the end portion 179 of the data line 171, the drain electrode 175, and the gate insulating layer 140 adjacent to the drain electrode 175. 185 and a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 together with the gate insulating layer 140. The passivation layer 180 also has an opening 189 that exposes a portion of the protrusion 154 of the semiconductor 151.

The contact holes 181 and 182 expose only the bottom films 129p, 179p and 175p of the gate lines 121 and the end portions 129 and 179 of the data lines 171, and the boundaries thereof are defined by the top films 129q, 179q, 175q). The contact hole 185 exposes the lower layer 175p of the drain electrode and the adjacent gate insulating layer 140. In addition, the opening 189 coincides with the exposed portion of the protrusion 154 of the semiconductor 151.

A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180, and they are made of transparent conductive materials such as IZO and ITO. In this case, since the contact hole 185 connecting the drain electrode 175 and the pixel electrode 190 is formed to the adjacent gate insulating layer 140, the upper layer 175q of the drain electrode is undercut by over etching. Can be prevented. Therefore, the contact area between the pixel electrode 190 formed on the gate insulating layer 140 and the lower layer 175p of the drain electrode is large, so that contact failure can be prevented from occurring.                     

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175. The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which the common voltage is applied. Let's do it.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with it, which is called a storage capacitor. The storage capacitor is made by overlapping the pixel electrode 190 with another gate line 121 adjacent thereto (referred to as a prior gate line) or a storage electrode formed separately. The storage electrode is made of the same layer as the gate line 121 and is separated from the gate line 121 to receive a voltage such as a common voltage. In order to increase the capacitance of the storage capacitor, that is, the capacitance, the area of the overlapped portion is increased or the conductor connected to the pixel electrode 190 and overlapped with the front gate line or the storage electrode under the protective film 180 is disposed between the two. You can get close.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line and the end portion 179 of the data line, respectively, through the contact holes 181 and 182. The contact auxiliary members 81 and 82 complement the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and the external device, and do not necessarily serve to protect them. Their application is optional.

Lastly, the first spacer pillar 321 and the second spacer pillar 322 are formed on the exposed portions of the passivation layer 180 and the protrusion 154 of the semiconductor 151. The spacer pillars 321 and 322 may be made of a photosensitive organic layer to maintain a constant gap between two display panels of the liquid crystal display and to protect an exposed portion of the semiconductor 151.

The first spacer pillar 321 is formed in any of the plurality of pixels defined by the gate line and the data line, and the second spacer pillar 322 is formed in the remaining pixels.

The first spacer pillar 321 is formed to have a height lower than the cell gap by slit exposing the photosensitive film to protect the exposed portion of the semiconductor layer 151.

In addition, the second spacer pillar 322 is formed to be substantially the same height as the cell gap by completely exposing the photoresist film, thereby protecting the exposed portion of the semiconductor layer 151 and simultaneously maintaining the cell gap of the liquid crystal display device. do.

Spacer pillars are required to protect the exposed portions of the semiconductor layer 151 of the thin film transistors formed in the pixel region, and exposed portions of the semiconductor layer 151 of the thin film transistors formed at the periphery to prevent static electricity. The number of spacer columns is also increased because spacer columns are also needed to protect them. Conventionally, such spacer columns are formed at almost the same height as the cell gap to simultaneously maintain the cell gap.                     

However, when the number of the second spacer pillars 322, which serves to maintain the cell gap, increases, it becomes difficult to inject liquid crystal, and therefore, it is preferable to lower the density of the second spacer pillars 322. Therefore, the first spacer pillar 321 having a height lower than the cell gap is formed to cover and protect the exposed portion of the semiconductor layer 151, and the density of the second spacer pillar 322 is lowered. Do not disturb the injection.

In an embodiment in which the density of the second spacer pillar 322 is reduced, a second spacer pillar 322 is formed in one of six pixels in FIG. 13, and a first spacer pillar in five pixels. A thin film transistor array panel 321 is illustrated. According to various process conditions, the second spacer pillar 322 may be formed in one pixel out of nine pixels, or the second spacer pillar 322 may be formed in one pixel out of twelve pixels. .

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, ITO or IZO.

Then, referring to FIGS. 3 to 14b and FIGS. 1 to 2a and 2b for a method of manufacturing the thin film transistor array panel for the liquid crystal display device shown in FIGS. 1, 2a and 2b according to an embodiment of the present invention. This will be described in detail.

First, as illustrated in FIGS. 3, 4A, and 4B, a plurality of gate lines 121 including a plurality of gate electrodes 124 are formed on an insulating substrate 110 such as transparent glass by a photolithography process. . The gate line 121 is formed of a double layer of the lower layer 121p and the upper layer 121q, the lower layer 121p is about 500 GPa thick, and the upper layer 121q is about 1,000 GPa to 3,000 GPa, preferably. For example, it is made of Al having a thickness of about 2,500Å.

As shown in FIGS. 5, 6A, and 6B, the gate insulating layer 140, the intrinsic amorphous silicon, and the impurity amorphous silicon layer are chemical vapor deposition (CVD). Then, the lower metal film and the upper metal film are sequentially stacked by sputtering, and then four layers of the upper and lower metal film, the impurity amorphous silicon layer, and the intrinsic amorphous silicon layer are photo-etched to obtain a plurality of upper and lower conductors (174q). , 174p), and a plurality of linear intrinsic semiconductors 151 each including a plurality of linear impurity semiconductors 164 and a plurality of protrusions 154.

As the material of the gate insulating layer 140, silicon nitride is preferable, and the lamination temperature is preferably 250 to 500 占 폚 and a thickness of about 2,000 to 5,000 Pa. The thicknesses of the intrinsic semiconductor 151 and the impurity semiconductor 164 are preferably about 500 mW to 1,500 mW and about 300 mW to 600 mW, respectively. The lower conductor 174p is made of Cr having a thickness of about 500 kV, and the upper conductor 174q is made of Al having a thickness of about 1,000 mW to 3,000 mW, preferably about 2,500 mW. As a target material of the upper conductor 174q, an Al-Nd alloy containing aluminum or 2 atomic% of Nd is suitable, and sputtering temperature is preferably about 150 ° C.

Next, as shown in FIGS. 7, 8A, and 8B, a protective film 180 having a thickness of 3,000 Å or more is stacked, a photoresist film 40 is formed thereon, and then dry-etched together with the gate insulating layer 140. A plurality of contact holes 181, 182, and 185 and a plurality of openings 189 are formed. The contact hole 181 exposes the upper layer 129q of the end portion 129 of the gate line 121, and the contact holes 182 and 185 and the opening 189 are a part of the upper conductor 174q, that is, FIG. 1. 2A and 2B, a portion of an end portion 179 of the data line 171, a portion of the drain electrode 175 and an adjacent gate insulating layer 140, and a source electrode 173 and a drain electrode ( 175) each reveals an area between them. In this case, the contact hole 185 may be formed by slit exposing the passivation layer 180 of the corresponding portion, thereby preventing over-etching of the gate insulating layer 140 exposed in the contact hole 185.

That is, the contact hole 181 completely exposes and develops the passivation layer 180 and the photoresist layer 40 on the gate insulating layer 140 of the corresponding portion, and the passivation layer 180 and the gate insulating layer of the portion where the contact hole 181 is to be formed. 140 is formed by first etching. In this case, the contact hole 185 may be slit-exposed and developed on the photoresist layer 40 on the passivation layer 180 of the corresponding portion so that the passivation layer 180 of the portion where the contact hole 185 is to be formed is not etched. In addition, the protective layer 180 of the portion where the contact hole 185 is to be formed is exposed through an etch back process, and only the protective layer 180 of the portion where the contact hole 185 is to be formed by second etching. To form a contact hole 185. Therefore, when the passivation layer 180 and the gate insulating layer 140 are etched by the first etching to expose the upper layer 129q of the end portion 129 of the gate line 121, the portion where the contact hole 185 is to be formed. Since the passivation layer 180 is not etched, the gate insulating layer 140 under the passivation layer 180 in the portion where the contact hole 185 is to be formed is not overetched.

9A and 9B, the exposed portions of the upper layer 121q and the upper conductor 174q of the gate line 121 are removed while the photosensitive layer 40 is left or removed as it is, and the lower layer 121p is removed. While exposing the lower conductor 174p, the upper layers 171q and 175q of the data line 171 and the drain electrode 175 are completed. In this case, the etching conditions of the upper layer 121q and the upper conductor 174q of the gate line 121 may be set such that the lower layer 121p and the lower conductor 174p are not etched. In this case, the upper conductor 174q to be etched may be over-etched under the passivation layer 180 to cause undercut.

Next, as shown in FIGS. 11A and 11B, a plurality of pixel electrodes 190 and a plurality of contact auxiliary members 81 and 82 are stacked by photolithography by sputtering an IZO or ITO film having a thickness of 400 kHz to 500 kHz. To form. When the material of the pixel electrode 190 and the contact auxiliary members 81 and 82 is IZO, a product called indium x-metal oxide (IDIXO) manufactured by Idemitsu, Japan may be used as a target, and may include In2O3 and ZnO. The content of zinc in the total amount of indium and zinc is preferably in the range of about 15-20 atomic%. In addition, it is preferable that the sputtering temperature of IZO is 250 ° C. or less in order to minimize contact resistance. IZO can be etched with a weak acid such as oxalic acid.

The contact auxiliary members 81 and 82 and the pixel electrode 190 are formed on the lower layer 129p and the lower conductor of the end portion 129 of the gate line 121 exposed through the contact holes 181, 182, and 185. 174p) and a portion of the gate insulating layer 140. However, the portion of the lower conductor 174p exposed through the opening 189 is not covered but is exposed.

12A and 12B, the exposed portion of the lower conductor 174p is removed by full etching to expose the impurity semiconductor 164, while the lower layer of the data line 171 and the drain electrode 175 are exposed. Complete (171p, 171q). Thereafter, the exposed portion of the impurity semiconductor 164 is removed by full etching, and the portion of the protrusion 154 of the semiconductor between the source electrode 173 and the drain electrode 175 is exposed. Oxygen plasma treatment is preferred to stabilize the surface of the exposed portion of the semiconductor 151.

Finally, as shown in FIGS. 1, 2A, and 2B, first and second spacer pillars 321 and 322 are formed on the exposed portions of the semiconductor 151. When the spacer pillars 321 and 322 are formed of a photoresist film, the thickness of the photoresist film can be adjusted only by the rotation speed of the spin coating apparatus, thereby making the process easier.

FIG. 14A is a view illustrating forming a first spacer pillar by slit exposure, and FIG. 14B is a view illustrating forming a second spacer pillar by full exposure.

As shown in FIGS. 14A and 14B, a first lower height than a cell gap is formed by using a mask in which a slit is formed on an exposed portion of a semiconductor 151 of a plurality of pixels defined as a gate line and a data line. A spacer pillar 321 is formed, and a second spacer pillar 322 having a height substantially equal to the cell gap is formed on the exposed portion of the semiconductor 151 of the remaining pixels by full exposure. The spacer pillars 321 and 322 illustrated in FIGS. 14A and 14B are formed using a negative photoresist film, but may be formed using a positive photoresist film.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

 A method of manufacturing a thin film transistor array panel according to the present invention forms a first spacer having a low height on an exposed portion of a semiconductor layer of a plurality of pixels, and has a high height on an exposed portion of a semiconductor layer of other pixels. By forming the second spacer pillar, there is an advantage in that the liquid crystal injection can be facilitated by adjusting the density of the second spacer pillar serving to maintain the cell gap.

Claims (18)

Forming a gate line on the substrate, Sequentially depositing a gate insulating film and a semiconductor layer on the gate line; Depositing a lower conductive layer and an upper conductive layer on the semiconductor layer; Photo etching the upper conductive layer, the lower conductive layer and the semiconductor layer; Depositing a protective film on the gate insulating film and the upper conductive film; Photo-etching the passivation layer to form a first contact hole exposing the first portion of the upper conductive layer and an opening exposing the second portion of the upper conductive layer; Removing the first and second portions of the upper conductive layer to expose the first and second portions of the lower conductive layer; Forming a pixel electrode covering a first portion of the lower conductive layer exposed through the first contact hole of the passivation layer, and Removing the second portion of the lower conductive film exposed through the opening of the protective film to expose the protrusion of the semiconductor layer, A first spacer pillar is formed on the exposed portion of the semiconductor layer of any of the plurality of pixels defined by the gate line and the data line by slit exposure, and the second spacer is completely exposed on the exposed portion of the semiconductor layer of the other pixels. A method of manufacturing a thin film transistor array panel forming a column. In claim 1, And a first portion of the upper conductive layer and a gate insulating layer adjacent thereto are exposed together in the passivation photolithography step. In claim 1, And forming a pixel electrode by covering the first portion of the lower conductive layer and the exposed gate insulating layer in the forming of the pixel electrode. 4. The method of claim 3, And forming a second contact hole exposing an end portion of the upper conductive layer in the protective film photolithography step. In claim 4, And removing an end portion of the upper conductive layer to expose an end portion of the lower conductive layer in the removing of the upper conductive layer. In claim 5, The gate line includes a lower layer and an upper layer. In claim 6, And etching the gate insulating film together in the protective film photolithography step to expose the top layer at the end of the gate line. In claim 7, And removing the exposed portions of the upper layer at the end of the gate line together in the upper conductive layer removing step to expose the lower layer at the end of the gate line. In claim 8, And forming a contact auxiliary member covering an end portion of the lower conductive layer and an exposed portion of the lower layer of the end portion of the gate line. The method of claim 9, The method of manufacturing a thin film transistor array panel of which the upper layer and the upper conductive layer of the gate line are made of the same material. In claim 10, The upper layer and the upper conductive layer of the gate line are made of Cr, and the lower layer and the lower conductive layer of the gate line are made of Al or an Al-Nd alloy. The method according to any one of claims 1 to 11, The semiconductor layer includes an intrinsic semiconductor film and an impurity semiconductor film, And removing the exposed portion of the impurity semiconductor film after removing the lower conductive film. Board, A gate line formed on the substrate and including a lower layer and an upper layer; A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, An ohmic contact formed on the semiconductor layer, A source electrode and a drain electrode formed on the ohmic contact and including a lower layer and an upper layer; A passivation layer formed on the source electrode and the drain electrode, the passivation layer having a first contact hole exposing the drain electrode lower layer and an adjacent gate insulating layer and an opening exposing the protrusion of the semiconductor layer; and A pixel electrode formed on the passivation layer and contacting the lower layer of the drain electrode through the first contact hole;  A first spacer pillar is formed on an exposed portion of the semiconductor layer of a plurality of pixels defined by a gate line and a data line, and a second spacer pillar is formed on an exposed portion of the semiconductor layer of other pixels. Thin film transistor array panel. The method of claim 13, The boundary of the opening coincides with the boundary of the protrusion of the semiconductor layer. The method of claim 13, The boundary of the drain electrode upper layer coincides with the boundary of the first contact hole. The method of claim 13, The lower layer at the end of the gate line is exposed to the outside of the upper layer, the protective layer further has a second contact hole exposing the lower layer at the end of the gate line, and the boundary of the lower layer at the end of the gate line is the second layer. Thin film transistor array panel coinciding with the boundary of the contact hole. The method of claim 16, And a contact auxiliary member covering a lower layer of an end portion of the gate line. The method of claim 13, The lower layer of the gate line and the data line is made of Cr, and the upper layer of the gate line and the data line is made of Al.

Images