KR100965762B1 - Parallel-serial converter - Google Patents

Abstract

The present invention relates to a parallel-to-serial conversion circuit capable of improving performance in high frequency operation by selecting and outputting a plurality of data using only clock signals having different phases. The parallel-to-serial conversion circuit according to the present invention is input in parallel. A data input unit configured to receive a plurality of pieces of data using a plurality of clock signals having different phases for each data; And a parallel-to-serial converter which sequentially selects and outputs an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used by the data input unit.

Data, clock signal, phase

Description

Parallel-to-serial conversion circuit {PARALLEL-SERIAL CONVERTER}

The present invention relates to a parallel-to-serial conversion circuit, and more particularly, to a parallel-to-serial conversion circuit for outputting a plurality of data in parallel using a plurality of clock signals of different phases.

1 is a 4: 1 parallel-to-serial conversion circuit according to the prior art.

As shown in the figure, a 4: 1 parallel-to-serial conversion circuit according to the prior art has four clock signals having different phases having a lower frequency than a plurality of data data0, data1, data2, and data3 than the clock signal clk. Flip-flops 101, 103, 105, and 109 output in synchronization with the rising edges of (iclk, iclkb, qclk, and qclkb) and four clock signals (iclk, iclkb, qclk, and qclkb) having different phases are made. The output signals d0, d1, d2, and d3 of the flip-flops 101, 103, 105, and 109 are selected in the enable period of the selection clock signals clkp0 / 0b, clkp1 / 1b, clk2 / 2b, and clk3 / 3b. Pass gates 109, 111, 113, and 115.

Here, the flip-flops 101, 103, 105, and 109 select the output signals d0, d1, d2, and d3 of the flip-flops 101, 103, 105, and 109 by the pass gates 109, 111, 113, and 115. When it comes to securing margins.

The select clock signals (clkp0 / 0b, clkp1 / 1b, clkp2 / 2b, clkp3 / 3b) pass when the parallel-to-serial conversion circuit outputs a plurality of data (data0, data1, data2, data3) inputted in parallel. Gates 109, 111, 113, and 115 are made to select and output data without overlap. That is, it is made in the form of a pulse of a width adjusted according to the width of the data that the output data should have.

In Fig. 1, iclk and qclkb, qclk and iclk, iclkb and qclk, qclkb and iclkb are inputted to the NAND gate and the inverter by two of the four clock signals (iclk, iclkb, qclk and qclkb) having different phases. / 0b, clkp1 / 1b, clkp2 / 2b, clkp3 / 3b). The four clock signals iclk, iclkb, qclk, and qclkb having different phases are clock signals having a phase difference of 90 degrees, and clock signals input to the NAND gate are clock signals having a phase difference of 90 degrees.

Since the phase difference of 90 degrees, the clock signal passing through the NAND gate and the inverter, respectively, is processed into the selection clock signal (clkp0, clkp1, clkp2, clkp3) having a pulse signal form having a high level in the portion where the high level section overlaps.

Here, the clock signals (iclk, iclkb, qclk, qclkb) used in the combination are combined so that they are output without overlap when the data (data0, data1, data2, data3) are output and the selected clock signals (clkp0 / 0b, clkp1 / 1b). , clkp2 / 2b and clkp3 / 3b) have a form of a pulse signal in which the high level section is an enable period. It is not necessary to combine only as an example of the combination used in FIG. 1 above.

2 is a timing diagram of a 4: 1 parallel-to-serial conversion circuit according to the prior art of FIG.

As shown in the figure, the select clock signals clkp0 / 0b, clkp1 / 1b, clkp2 / 2b, and clkp3 / 3b are combined in four pulse signals with different phases, ilk, iclkb, qclk, and qclkb, in a pulse form. Is made. The selected clock signals clkp0 / 0b, clkp1 / 1b, clkp2 / 2b, and clkp3 / 3b generated at this time are matched with the data widths of the output data a0, b0, c0, and d0 to output data a0, b0, c0, and d0. ) Is not overlapped so that) can be output without overlap.

However, the selected clock signals clkp0 / 0b, clkp1 / 1b, clkp2 / 2b, and clkp3 / 3b are larger than the widths of the high level or low level sections of the four clock signals iclk, iclkb, qclk, and qclkb that are different in phase. Has a small pulse width. That is, when the enable period of four clock signals (iclk, iclkb, qclk, qclkb) having different phases is called a high level or low level period, the selection clock signals (clkp0 / 0b, clkp1 / 1b, clkp2 / 2b, and clkp3). It can be seen that the width of the enable period of / 3b) is narrower than the enable period of four clock signals iclk, iclkb, qclk, and qclkb having different phases.

In this case, the reason why the system uses low frequency clock signals with different phases is that the high frequency clock signal has a narrow width of the high level or low level section, which makes it difficult to swing the high frequency clock signal. However, according to the prior art, four clock signals (iclk, iclkb, qclk, and qclkb) having different phases are again pulsed with narrower enable intervals than four clock signals (iclk, iclkb, qclk and qclkb) having different phases. Since it is processed into a select clock signal of the type (clkp0 / 0b, clkp1 / 1b, clkp2 / 2b, clkp3 / 3b), there is a problem of diluting the advantages of using a clock signal of a different frequency with a different phase.

In addition, by processing the four clock signals (iclk, iclkb, qclk, qclkb) with different phases in the form of pulses, the width of the high level or low level section is reduced to select clock signals (clkp0 / 0b, clkp1 / 1b, clkp2 / 2b, The clkp3 / 3b) may swing and the duty ratio may be shifted, and thus the passgates 109, 111, 113, and 115 may not correctly select the data d0, d1, d2, and d3.

In addition, since the data d0, d1, d2, and d3 are selected using the passgates 109, 111, 113, and 115, the output data a0, b0 is determined by the junction capacitance of the passgates 109, 111, 113, and 115. , c0, d0) limits the swing width and causes jitter.

The present invention has been proposed to solve the above problems, and processes a plurality of clock signals having different phases into pulses having a width smaller than the width of the high level or low level sections of the plurality of clock signals having different phases. Without this, a plurality of clock signals having different phases and a plurality of clock signals having different phases having a predetermined phase are used together to select and output data, thereby providing an advantage of using a plurality of clock signals having different phases. It is an object of the present invention to provide a parallel-to-serial conversion circuit that can select and output data more accurately in high frequency operation.

Another object of the present invention is to provide a parallel-to-serial conversion circuit capable of reducing jitter caused by the junction capacitance of the passgate by not using a passgate.

The present invention for achieving the above object, the data input unit for receiving a plurality of data input in parallel using a plurality of clock signals of different phases for each data; And a parallel-to-serial converter which sequentially selects and outputs an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used by the data input unit.

In addition, the present invention for achieving the above object, the data input unit for receiving a plurality of data input in parallel through the four paths respectively as valid data in the enable interval of the four clock signal phase difference 90 degrees for each data; And a parallel-to-serial converter for sequentially selecting and outputting output signals of the data input unit during an enable period of four clock signals 90 degrees out of phase with the four clock signals used in the data input unit.

According to the present invention, a plurality of clock signals having different phases may be processed without processing a plurality of clock signals having different phases in the form of a pulse having a width smaller than a width of a high level or low level section of the clock signals having different phases. Since data is selected and output using only a clock signal, the advantage of using a plurality of clock signals having different phases can be utilized to more accurately select and output data during high frequency operation.

Also, since passgate is not used, it is effective in reducing jitter caused by passgate junction capacitance.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a diagram illustrating a configuration of a parallel-serial conversion circuit according to an embodiment of the present invention, in which a plurality of data are input through four paths.

As shown in the figure, the present invention provides a plurality of clock signals (qclkb, iclk, qclk, iclkb) having different phases for each of the data (data0, data1, data2, data3) input in parallel through four paths. A data input unit 301 which receives data as valid data in an enable period of the data input unit 301; And the data input unit 301 during the enable period of the four clock signals qclkb, iclk, qclk, and iclkb used by the data input unit 301 and four clock signals iclk, qclk, iclkb, and qclkb that are 90 degrees out of phase with each other. And a parallel-to-serial conversion unit 303 for sequentially selecting and outputting an output signal.

The parallel-to-serial converter 303 is capable of validating a plurality of data (data0, data1, data2, data3) during the enable period of the clock signals iclk, qclk, iclkb, and qclkb used in the parallel-to-serial converter 303. Select as data.

Here, the four clock signals qclkb, iclk, qclk, and iclkb used in the data input unit 301 each have a phase difference of 90 degrees, and the four clock signals iclk, qclk, used in the parallel-serial converter 303, respectively. iclkb, qclkb) also have a phase difference of 90 degrees each. In addition, the four clock signals iclk, qclk, iclkb, and qclkb used in the parallel-to-serial converter 303 are 90 degrees out of phase with the clock signals qclkb, iclk, qclk, and iclkb used in the data input unit 301. Which means

For example, the parallel signal used to process the clock signal qclkb of the data input unit 301 used to process the data data0 input to the first path and the valid data d0 / 0b of the data input unit 301. It means the phase difference of the clock signal iclk of the serial converter 303.

The reason for using the clock signal as described above will be described in detail below, but to compensate for the disadvantages of the prior art, a plurality of data inputted in parallel using only the clock signal without processing the signal in the form of a narrow pulse in the enable period (data0, data1) , data2, data3) to output serially. That is, the data input unit 301 and the parallel-to-serial converter 303 each select and input a plurality of data data0, data1, data2, and data3 as valid data using a clock signal used by the data input unit 301 and the parallel-serial converter 303. out)

The data input unit 301 and NAND gates 305, 307, 309, and 311 that receive clock signals qclkb, iclk, qclk, and iclkb that are different in phase from a plurality of data data0, data1, data2, and data3. And inverters 313, 315, 317, and 319 for inverting the output signals of the gates 305, 307, 309, and 311. By the above configuration, the data input unit 301 receives a plurality of data data0, data1, data2, and data3 as valid data d0 / 0b, d1 / 1b, d2 / 2b, and d3 / 3b. Here, the signals d0b, d1b, d2b, and d3b that do not pass through the inverters 313, 315, 317, and 319 are also output, which is used in the embodiment of the parallel-to-serial conversion unit 303 which will be described later.

Here, valid means that the enable interval of a plurality of clock signals (qclkb, iclk, qclk, iclkb) having different phases among a plurality of data (data0, data1, data2, data3) continuously input to the data input unit 301. This means selecting only data.

For example, data input in an enable period of a plurality of clock signals having different phases may be input at a logic level or inverted logic level of the data, and data input at an interval other than an enable period may be related to a logic level of the data. A constant value is entered without.

When the enable period of four clock signals (qclkb, iclk, qclk, and iclkb) having different phases is referred to as a high level section, the NAND gates 305, 307, 309, and 311 and the inverters 313, 315, and 317 are displayed in the high level section. 319 outputs valid data d0, d1, d2, d3 having the same logical level of the plurality of data data0, data1, data2, and data3. In the low level section, the low level is increased by the NAND gates 305, 307, 309, and 311 and the inverters 313, 315, 317, and 319 regardless of the logic levels of the plurality of data data0, data1, data2, and data3. Is output.

Signals that do not pass through the inverters 313, 315, 317, and 319 are also output. This is for use in the parallel-to-serial conversion unit 303, which will be described later, and the valid data d0b, d1b, d2b, d3b).

That is, as described above, in the enable period of four clock signals qclkb, iclk, qclk, and iclkb having different phases, the data input unit 301 stores a plurality of data (data0, data1, data2, data3) as valid data ( d0 / 0b, d1 / 1b, d2 / 2b, d3 / 3b).

During the enable period of a plurality of clock signals (qclkb, iclk, qclk, iclkb) with different phases, a plurality of data (data0, data1, data2, data3) are valid data (d0 / 0b, d1 / 1b, d2 / 2b, d3 / 3b) is input to a plurality of data (data0, data1, data2, data3) by using the clock signal (iclk, qclk, iclkb, qclkb) used in the parallel-serial converter 303 and a predetermined phase difference. To select and output serially.

The parallel-serial converter 303 may include an A node terminated at a first level; And the second node A in response to the valid data (d0, d1, d2, d3) of the data input unit 301 and the clocks (iclk, qclk, iclkb, qclkb) used in the parallel-to-serial conversion unit 303 simultaneously. It includes a plurality of first driving unit (327 to 330) to drive at a level. In response to the logic level of node A, a plurality of data (data0, data1, data2, data3) are output in series.

As mentioned above, the clock signals iclk, qclk, iclkb, and qclkb used in the parallel-to-serial conversion unit 303 are respectively 90 degrees from the clock signals qclkb, iclk, qclk, and iclkb used in the data input unit 301. Has a phase difference in degrees.

The first drivers 327 to 330 are parallel to serial converters 303 and transistors T1, T3, T5, and T7 that receive one of valid data d0, d1, d2, and d3 of the data input unit 301. Transistors T2, T4, T6, and T8, which receive one of the clock signals iclk, qclk, iclkb, and qclkb used in, are connected in series.

The first driver 327 to 330 may convert the NMOS transistor clock signal iclk, qclk, iclkb, qclkb having a 90 degree phase difference from the valid data d0, d1, d2, and d3 received from the data input unit 301. A plurality of data (data0, data1, data2, data3) are selected by input through T1 through T8. At this time, the NMOS transistors T1 to T8 are connected in series and must be turned on together to output output data out.

Accordingly, the first drivers 327 to 330 of the parallel-serial converter 303 may generate a plurality of pieces of data during the enable period of the clock signals iclk, qclk, iclkb, and qclkb used by the parallel-to-serial converter 303. data0, data1, data2, and data3 are selected as valid data having a phase difference of 90 degrees with the valid data (d0, d1, d2, d3) inputted by the data input unit 301.

Here, valid means the same as the validity described in the data input unit 301.

The first drivers 327 to 330 receive valid data d0, d1, d2, and d3 of the data input unit 301, and do not directly receive a plurality of data data0, data1, data2, and data3. However, valid data (d0, d1, d2, d3) of the data input unit 301 is also output from a plurality of data (data0, data1, data2, data3), and the clock signals qclkb, iclk, qclk, Since the clock signals iclk, qclk, iclkb, and qclkb having a phase difference of 90 degrees with iclkb are used, the parallel-serial converter 303 selects a plurality of data (data0, data1, data2, data3) as valid data. can see.

Therefore, a plurality of data (data0, data1, data2, data3) input in parallel to the data input unit 301 is input as valid data (d0, d1, d2, d3) through the data input unit 301, and parallel to serial conversion It is output as the output data out of the parallel-to-serial conversion circuit 303 only during the section selected as valid data through the section 303.

5 shows an example of selecting as valid data. For example, data0 is selected as valid data d0 by the clock qclkb in the data input unit 301 and selected as valid data by the clock iclk in the parallel-to-serial conversion unit 303. As shown in the figure, other than the section selected as valid data, it is low level regardless of the logic level of the data and has no influence on driving the first drivers 327 to 330. Wherein clkp0 and clkp1 will be described later in FIG.

When Data0 is at a high level, the NMOS transistors T1 to T8 of the first drivers 327 to 330 are connected in series, so that the data input unit 301 can be used for parallel-serial conversion with valid data d0, d1, d2, and d3. The NMOS transistors T1 to T8 are all turned on in one of the first drivers 327 to 330 in the common period of valid data of the unit 303.

That is, in the common enable period of the clock signals (qclkb, iclk, qclk, iclkb) used in the data input unit 301 and the clock signals (iclk, qclk, iclkb, qclkb) used in the parallel-serial conversion unit 303. A plurality of data (data0, data1, data2, data3) are output as output data out. In addition, only one first driver 327 through 330 of the first drivers 327 through 330 is turned on together so that the plurality of data data0, data1, data2, and data3 are turned on. By selecting, output data out is output without overlap.

When there is no low level output signal in the first drivers 327 to 330, the node A is terminated to a high level by the power supply voltage vvd. Therefore, when the logic level of the plurality of data (data0, data1, data2, data3) is low level, the first drivers 327 to 330 are not enabled, the node A is terminated to a high level, and the output data is output by the inverter 321. The logic level of (out) is equal to the logic level of a plurality of data (data0, data1, data2, data3).

When the logic level of the plurality of data data0, data1, data2, and data3 is high level, one of the first drivers 327 through 330 is enabled and the node A becomes low level. By the inverter, the logic level of the output data out is equal to the logic level of the plurality of data data0, data1, data2, and data3.

That is, the inverter 321 outputs a plurality of data (data0, data1, data2, data3) in series in response to the logic level of the A node. The role of the inverter 321 is to match the output data out with the logic level of the plurality of data data0, data1, data2, and data3.

According to the prior art, a plurality of data is selected by a pulse signal of a plurality of clock signals having different phases and a data width of the output data is determined and a plurality of data are output in series. A plurality of different clock signals are used to select a plurality of data, determine a data width of the output data, and output the plurality of data in series.

As a result, according to the present invention, a plurality of clock signals having different phases may be processed into a pulse type signal having a width smaller than a section width of a high level or a low level of the plurality of clock signals having different phases. By using only a plurality of clock signals having different phases, the functions of the conventional parallel-serial conversion circuit can be fulfilled and the object of the present invention can be achieved.

The second signal selector 327 receives the inverted valid data d0b, d1b, d2b, and d3b of the data input unit 301. The reason is that the MOS transistors of the MOS transistor stages 331 to 334 are turned on in the low level period of the plurality of data (data0, data1, data2, data3), which is also the MOS transistor 337 of the first signal output unit 325. This is to turn on to generate an output signal corresponding to a low level section of a plurality of data (data0, data1, data2, data3). Like the first signal selector 321, the MOS transistor 337 of the first signal output unit 325 is turned on when the MOS transistors of the MOS transistor terminals 331 to 334 are turned on together.

The inverter 335 inverts the output signal of the first signal selector 321 and the output signal of the first signal output unit 325 and outputs the inverted signal. The role of the inverter 335 is to match the output data out with the logic level of the plurality of data data0, data1, data2, data3.

4 is another embodiment of a parallel-to-serial converter 303.

As shown in the figure, the parallel-to-serial converter 303 includes valid data (d0, d1, d2, d3) of the data input unit 301 and clocks (iclk, qclk, a plurality of first driving units 401 to 404 for respectively driving A nodes to a first level in response to iclkb and qclkb at the same time; In response to the inverted valid data (d0b, d1b, d2b, d3b) of the data input unit 301 and the clocks (iclk, qclk, iclkb, qclkb) used in the parallel-to-serial conversion unit 303, the B node may be respectively formed. A plurality of second drivers 405 to 408 for driving at two levels; And a third driver 409 for driving the A and B nodes at different logic levels in response to the logic levels of the A and B nodes.

There is a configuration difference from the parallel-to-serial conversion unit 303 in FIG. 3, but the second driving units 405 to 408 are further configured. 3, when the logic level of the plurality of data (data0, data1, data2, data3) is low level, instead of terminating the node A to the high level as shown in FIG. To print. Accordingly, valid data d0b, d1b, d2b, and d3b that are inverted by the data input unit 301 are input, and valid data d0b, d1b, d2b, and d3b that are inverted in FIG. 3 for use in the exemplary embodiment of FIG. 4. Is generated.

The first drivers 401 to 404 are transistors T9 and T11 that receive one of valid data d0, d1, d2, and d3 of the data input unit 301, like the first drivers 327 to 330 of FIG. 3. , T13, T15 and transistors T10, T12, T14, and T16, which receive one of the clock signals iclk, qclk, iclkb, and qclkb used in the parallel-to-serial converter 303, are connected in series. The second driving units 405 to 408 and the transistors T17, T19, T21, and T23 that receive one of the inverted and valid data d0b, d1b, d2b, and d3b of the data input unit 301 and the parallel-to-serial converter are included. Transistors T18, T20, T22, and T24 that receive one of the clock signals iclk, qclk, iclkb, and qclkb used at 303 are connected in series.

Referring to the difference from the parallel-to-serial converter 303 of FIG. 3, the node A becomes low when a plurality of data is high level, and the node B becomes low level when a plurality of data is low level. . When the node A is at the low level, the output data out through the inverter 411 is at the high level. When the node B is at the low level, the PMOS transistor T25 of the third driver 409 is turned on. Therefore, the PMOS transistor T25 passes the power supply voltage vvd so that the output data out becomes low level by the inverter 411. That is, the third driver 409 drives the node A to a high level in response to the low level of the node B.

The role of the inverter 411 is to match the output data out with the logic level of the plurality of data data0, data1, data2, and data3 as shown in FIG. 3.

FIG. 6 is a diagram in which a delay unit 302 is added to the parallel-serial converter 303 of FIG. 4.

The delay unit 302 receives four clock signals iclk, qclk, iclkb, qclkb and the power supply voltage VDD used in the parallel-serial converter 303 of FIG. 4, and receives the parallel-serial converter of FIG. 4. The NAND gate and the inverter which respectively delay the four clock signals iclk, qclk, iclkb, and qclkb used in 303 are included. The delay unit 302 secures a margin between the clocks (qclkb, iclk, qclk, iclkb) used in the data input unit 301 and the clocks (iclk, qclk, iclkb, qclkb) used in the parallel-serial conversion unit 303. do.

Referring to FIG. 5, when data0 is selected, the data input unit 301 is selected as valid data d0 by the clock qclkb, and the parallel-serial converter 303 is selected by the clock iclk. Is selected as valid data. In the case of selecting Data1, it is selected as valid data d1 by the clock iclk in the data input section 301 and as valid data by the clock qclk in the parallel-serial conversion section 303.

At this time, the parallel-serial conversion of the clock signals clkp0, clkp1, clkp2, and clkp3 delayed by a predetermined amount of the four clock signals iclk, qclk, iclkb, and qclkb used in the parallel-serial converter 303 of FIG. 4 is performed. It is used in the section 303. That is, iclk corresponds to clkp0, qclk corresponds to clkp1, ilkcb corresponds to clkp2, and qclkb corresponds to clkp3. Then, between the data selected as valid data by the clock signals clkp0, clkp1, clkp2, and clkp3 respectively delayed by a predetermined amount, the predetermined interval lth corresponding to the predetermined amount, for example, at the falling edge of qclkb of the data input unit 301- The interval lth between the rising edges of clkp1 of the serial converter 303 occurs.

The predetermined period lth is a period in which the transistors of the parallel-serial converter 303 are all turned off. The parallel-serial converter 303 outputs previous data as output data out_c. That is, in this case, data0 is output as the output data out_c.

As a result, the delay unit 302 secures a margin between the data when a plurality of data (data0, data1, data2, data3) is output as the output data out_c, so that the plurality of data (data0, data1, data2, data3) The performance of the present invention can be further improved by preventing overlapping and colliding with the output data out_c. The predetermined amount is sufficient to prevent a plurality of data (data0, data1, data2, data3) from overlapping and colliding with the output data (out_c).

7 is a timing diagram illustrating the overall operation of the present invention.

The clock signal used to process the second data data1 in the data input unit 301 is iclk, and the clock signal used to process the second valid data d1 in the parallel-serial converter 303 has a phase of 90 degrees. Behind it is qclk. The clock signal used for processing the third data data2 in the data input unit 301 is qclk, and the clock signal used for processing the third valid data d2 in the parallel-serial converter 303 has a phase of 90 degrees. It is lagging behind iclkb. The remaining two data (data0, data3) also use the remaining clock signal as above.

Taking the second data data1 as an example, the operation of the embodiment of FIG. 3 will be described in terms of timing.

In a detailed embodiment, the enable section of the four clock signals qclkb, iclk, qclk, and iclkb that are used in the data input unit 301 with different phases is selected as the high level section, so the iclk clock signal in the data input section 301 is selected. The second valid data d1 is input from the second data data1 in the high level interval of.

The four clock signals iclk, qclk, iclkb, and qclkb of different phases used in the parallel-to-serial converter 303 also have a high level by using the NMOS transistors of the MOS transistor stages 327 to 334. Since it is selected as the interval, the output data b0 is output as much as the high level interval of qclk among the interval of the second valid data d1.

8 illustrates a clock signal according to an embodiment of the present invention.

The 6: 1 parallel-to-serial conversion circuit shows how clock signals clk0 to clk5 having different phases select and output data. In the embodiment of FIG. 3, since a plurality of data data0, data1, data2, and data3 are received in parallel through four paths, the clock signal qclkb, iclk, qclk, iclkb) and the clock signals qclkb, iclk, qclk, and iclkb used by the data input unit 301 in the parallel-to-serial conversion unit 303 are clock signals (iclk, qclk, iclkb, qclkb).

However, the present invention is also applicable to a case where a plurality of data are input in parallel through a plurality of paths. For example, when a plurality of data data0 to data5 are input in parallel through six paths, the clock signals clk0 to clk5 having a phase difference of 60 degrees may be used as shown in FIG. 8.

The six clock signals clk0 to clk5 having different phases each have a phase difference of 60 degrees. A clock having a predetermined phase difference of 120 degrees from a clock signal clk0 to clk5 used in the data input unit by setting the high level section as an enable period and using the clock signals clk0 to clk5 used in the parallel-to-serial converter 303. If it corresponds to the signals clk0 to clk5, data can be selected and output.

That is, if the clk0 signal corresponds to the clk2 signal, the clk1 signal to the clk3 signal, the clk2 signal to the clk4 signal, the clk3 signal to the clk5 signal and the clk4 signal to the clk0 signal, and the clk5 signal to the clk1 signal, 6: 1 parallel-serial In the conversion circuit, output data a0, b0, c0, d0, e0, and f0 may be selected and output using only clock signals clk0 to clk5 having different phases.

Although the present invention has been described by means of limited embodiments and drawings, the present invention is not limited thereto and is intended to be equivalent to the technical idea and claims of the present invention by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible.

1 is a block diagram of a parallel-to-serial conversion circuit according to the prior art;

2 is a timing diagram according to the prior art,

3 is a block diagram of a parallel-serial conversion circuit according to an embodiment of the present invention;

4 is a block diagram of a parallel-to-serial conversion unit according to an embodiment of the present invention;

5 is a diagram for selecting valid data;

FIG. 6 is a diagram in which a delay unit is added to the parallel-to-serial conversion circuit of FIG. 4.

7 is a timing diagram showing the overall operation of the present invention;

8 illustrates a clock signal according to an embodiment of the present invention.

Claims (14)

A data input unit which receives a plurality of data input in parallel using a plurality of clock signals having different phases for each data; And A parallel-to-serial converter for sequentially selecting and outputting an output signal of the data input unit by using a plurality of clock signals each having a predetermined phase difference from each of the plurality of clock signals used in the data input unit, and delaying a predetermined amount further Parallel-to-serial conversion circuit comprising a. The method of claim 1, The data input unit Receiving the plurality of data as valid data during the enable period of the clock signal used in the data input unit Parallel-to-serial conversion circuit. 3. The method of claim 2, The parallel-serial converter Selecting the plurality of data as valid data during an enable period of the clock signal used in the parallel-serial converter; Parallel-to-serial conversion circuit. The method of claim 3, wherein A plurality of data input in parallel to the data input unit, Input as valid data through the data input section, and output as valid output data of the parallel-serial conversion circuit only during a section selected as valid data through the parallel-to-serial conversion section. Parallel-to-serial conversion circuit. The method of claim 1, The constant phase is, The output data of the parallel-to-serial conversion circuit is adjusted to have a data width that does not overlap. Parallel-to-serial conversion circuit. The method of claim 1, The parallel-serial conversion circuit, A delay unit for delaying the predetermined amount of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit; Contains more By using the output signal of the delay unit, to secure a margin between the plurality of data output Parallel-to-serial conversion circuit. The method of claim 1, The parallel-serial converter, An A node terminated to a first level; And A plurality of first drivers respectively driving the A node to a second level in response to the received plurality of data and a clock used in the parallel-serial converter; Including Outputting the plurality of data in series in response to a logic level of the A node Parallel-to-serial conversion circuit. The method of claim 7, wherein The first driving unit, A transistor receiving one of the plurality of input data and a clock connected in series with the transistor and receiving one of a clock used in a parallel-serial converter; Parallel-to-serial conversion circuit comprising a. The method of claim 1, The parallel-serial converter, A plurality of first drivers respectively driving A nodes to a first level in response to the plurality of input data and a clock used in the parallel-serial converter; A plurality of second drivers respectively driving B nodes to a second level in response to a signal obtained by inverting the plurality of input data and a clock used in the parallel-serial converter; And A third driver for driving the A and B nodes to different logic levels in response to the logic levels of the A and B nodes Parallel-to-serial conversion circuit comprising a. The method of claim 9, The first driving unit, A transistor receiving one of the plurality of input data and a transistor connected in series with the transistor and receiving one of a clock used in the parallel-serial converter; Including The second drive unit, A transistor configured to receive one of the received signals inverted the plurality of data and a transistor connected in series with the transistor and receiving one of a clock used in the parallel-serial converter; Parallel-to-serial conversion circuit comprising a. A data input unit for receiving a plurality of data inputted in parallel through four paths as valid data in an enable period of four clock signals having a phase difference of 90 degrees for each data; And A parallel-to-serial converter for sequentially selecting and outputting an output signal of the data input unit during an enable period of four clock signals, which are each 90 degrees out of phase with the four clock signals used in the data input unit, respectively. Parallel-to-serial conversion circuit comprising a. The method of claim 11, The parallel-serial converter, Selecting the plurality of data as valid data during an enable period of the clock signal used in the parallel-serial converter; Parallel-to-serial conversion circuit. The method of claim 12, A plurality of data input in parallel to the data input unit, Input as valid data through the data input section, and output as valid output data of the parallel-serial conversion circuit only during a section selected as valid data through the parallel-to-serial conversion section. Parallel-to-serial conversion circuit. The method of claim 11, The parallel-serial conversion circuit, A delay unit for delaying the predetermined amount of four clock signals that are 90 degrees out of phase with the four clock signals used in the data input unit; Contains more By using the output signal of the delay unit, to secure a margin between the plurality of data output Parallel-to-serial conversion circuit.

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