KR100955940B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A method of manufacturing a semiconductor device according to the present invention includes forming an insulating film on a semiconductor substrate including a cell region having a dummy region at an edge portion and a peripheral region; Forming a plurality of storage node contacts in an insulating film of a cell region including the dummy region; Forming a first etch stop layer on the insulating layer of the dummy region and the peripheral region including the storage node contact formed in the dummy region; Forming an insulating layer including a storage node contact in the cell region, a first etch stop layer and a second etch stop layer in the dummy region and the peripheral region; Forming a sacrificial layer and a support layer on the second etch stop layer; Forming a plurality of holes to expose the storage node contact of the cell area and the first etch stop layer of the dummy area; Forming a storage node on sidewalls of each hole; Patterning the support layer in a cell region including the dummy region to connect the storage nodes to form a support pattern; And removing the sacrificial layer of the cell region including the dummy region.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can prevent bunker phenomenon and lining phenomenon occurring during the capacitor forming step.

As the demand for semiconductor memory devices has soared, various techniques for obtaining high capacity capacitors have been proposed. The capacitor has a structure in which a dielectric film is interposed between a storage node and a plate node, and its capacity is proportional to the surface area of the electrode and the dielectric constant of the dielectric film, and the distance between the electrodes, that is, the dielectric film. It is inversely proportional to the thickness.

Therefore, it is required to use a dielectric film having a high dielectric constant, to enlarge the surface area of the electrode, or to reduce the distance between the electrodes in order to obtain a high capacity capacitor. However, reducing the distance between the electrodes, that is, the thickness of the dielectric film has its limitations, and studies for forming a high-capacitance capacitor use a dielectric film having a high dielectric constant or increase the height of the capacitor to increase the surface area of the electrode. It is going to expand.

As a method for increasing the surface area of the electrode, there is a method of forming a capacitor in a three-dimensional structure of a concave shape or a cylinder shape, and the cylinder type capacitor may utilize both sides of the storage node. Since the CIAIC (Cathode-Insulator-Anode-Insulator-Cathode) structure is present, it has a relatively large electrode area compared to the concave-type capacitor, and is advantageous for high integration devices.

Hereinafter, a method of manufacturing a semiconductor device having a cylindrical capacitor according to the prior art will be briefly described. First, an insulating film is formed on each area of the semiconductor substrate including a cell area having a dummy area at the edge and a peripheral area, and then a storage node contact is formed in the insulating film. Thereafter, an etch stop layer and a sacrificial layer are formed on the insulating layer including the storage node contacts, and then holes are formed to expose the storage node contacts of the respective regions. Subsequently, after the storage node material is formed on the sacrificial layer including the hole, the storage node material is etched to separate neighboring storage node materials from each other, and thereafter, a dip for etching and removing the sacrificial films of the respective regions is removed. A dip-out process is performed to form cylindrical storage nodes respectively connected to storage node contacts formed in the respective areas. Then, the dielectric film and the plate node are formed on the surface of each storage node to complete the formation of the cylindrical capacitor.

On the other hand, the dip-out process for forming the conventional cylindrical capacitor is generally a cell region including a full dip-out process and a dummy region to remove the sacrificial film of the cell region, the dummy region and the entire peripheral region. It is a partial dip-out process of removing only the sacrificial film of the.

However, when the hole for forming the storage node is formed smaller than the required size in the dummy area, the storage node may not be exposed during the etching process to form the storage node on the sacrificial insulating layer. Thus, a defect occurs in which the storage node is lost in a subsequent dip-out process.

In addition, when the hole is formed larger than the required size, the storage node is formed up to a portion outside the storage node contact, and the storage node below the hole is lost during the etching process for separating the storage node. Accordingly, a defect such as a bunker phenomenon in which the exposed insulating layer is removed in a subsequent dip-out process occurs in a portion outside the storage node contact under the lost storage node, and the storage node in the dummy region where the bunker phenomenon is severe. Leaning of storage nodes occurs.

In the case where the capacitor is formed by performing the entire dip-out process, when the interlayer insulating film is formed in the cell region and the peripheral region after the capacitor is formed, the step difference of the interlayer insulating layer between the cell region and the peripheral region is increased by the height of the capacitor. Occurs. Accordingly, a mask pattern is formed at a steep slope during a mask process for forming a subsequent plate node, and a residue of the mask pattern is left when the mask pattern is removed, thereby causing plate node patterning defects. In addition, due to the large step of the interlayer insulating film, the interlayer insulating film needs to be formed thick. Accordingly, a planarization process is required, and a mask process and an etching process are additionally required to remove the interlayer insulating film only in the cell region including the dummy region. Done.

In addition, when the capacitor is formed by performing the partial dip-out process, when the size of the guard storage node formed at the outermost part of the dummy area is small or poor patterning, holes for forming the storage node are etched to the etch stop layer. If not, bunker phenomenon occurs. In addition, when the guard storage node is large in size, during the etching process for separating the storage node, an etch stop layer is lost to cause a bunker phenomenon in which the lower interlayer insulating layer is removed. In addition, during the mask process for performing the dip-out process only in the cell region and the dummy region, a bunker phenomenon occurs in which the upper portion of the interlayer insulating layer is removed because the alignment with the guard storage node is not precisely aligned.

The present invention provides a semiconductor device and a method of manufacturing the same that can prevent bunker phenomenon and lining phenomenon that occur during the capacitor forming process.

A semiconductor device according to the present invention includes a semiconductor substrate including a cell region having a dummy region at an edge portion thereof and a peripheral region; An insulating film formed on the semiconductor substrate; A plurality of storage node contacts formed in the insulating film of the cell region including the dummy region; A first etch stop layer formed on the insulating layer including the storage node contact in the dummy area; A plurality of storage nodes formed on the storage node contacts of the cell area and the first etch stop layer of the dummy area; A second etch stop layer formed on the insulating layer of the cell region and the first etch stop layer of the dummy region and the peripheral region; A sacrificial layer formed on the second etch stop layer of the peripheral area; And a support pattern formed between the storage nodes to connect the storage nodes.

The first and second etch stop films are formed of a nitride film.

The support pattern is made of a nitride film.

The semiconductor device may further include a dielectric film formed on the surface of the storage node and a plate node formed on the dielectric film.

The semiconductor device may further include a buffer layer formed between the first etch stop layer and the second etch stop layer of the dummy region.

The semiconductor device may further include a first etch stop layer formed over the insulating layer and under the second etch stop layer in the peripheral region.

The semiconductor device may further include a buffer layer formed between the first etch stop layer and the second etch stop layer in the peripheral area.

The buffer film is made of an oxide film.

Storage nodes formed in the dummy area are alternately arranged in plan view.

Storage nodes formed in the dummy area are integrally formed to be interconnected.

In addition, a method of manufacturing a semiconductor device according to the present invention includes forming an insulating film on a semiconductor substrate including a cell region and a peripheral region having a dummy region at an edge portion thereof; Forming a plurality of storage node contacts in an insulating film of a cell region including the dummy region; Forming a first etch stop layer on the insulating layer of the dummy region and the peripheral region including the storage node contact formed in the dummy region; Forming an insulating layer including a storage node contact in the cell region, a first etch stop layer and a second etch stop layer in the dummy region and the peripheral region; Forming a sacrificial layer and a support layer on the second etch stop layer; Forming a plurality of holes to expose the storage node contact of the cell area and the first etch stop layer of the dummy area; Forming a storage node on sidewalls of each hole; Patterning the support layer in a cell region including the dummy region to connect the storage nodes to form a support pattern; And removing the sacrificial layer of the cell region including the dummy region.

And forming a buffer layer on the first etch stop layer after forming the first etch stop layer and before forming the second etch stop layer.

The buffer film is formed of an oxide film.

The support film is formed of a nitride film.

The sacrificial layer is formed of a double layer having different etching selectivity.

The storage node is formed of TiN.

The first and second etch stop layers are formed of a nitride layer.

After removing the sacrificial layer, the method may further include forming a dielectric layer on a surface of the storage node and forming a plate node formed on the dielectric layer.

The storage nodes formed in the dummy area are formed to be alternately arranged in plan view.

The storage nodes formed in the dummy area are integrally formed to be interconnected.

The present invention forms an etch stop layer on top of a dummy region, forms a storage node on the etch stop layer, and maintains a support pattern on the peripheral area to prevent the storage node from falling down. By manufacturing the semiconductor device through the out process, the bunker phenomenon occurring in the dummy area storage node may be prevented.

In addition, even when the bunker occurs, the storage node of the dummy area is fixed by the etch stop layer, thereby preventing the dummy area storage node from falling down.

In addition, since the storage node of the dummy region is formed on the etch stop layer formed of the nitride layer, the storage node of the dummy region is not connected to the storage node contact of the dummy region, thereby reducing the parasitic capacitance of the bit line.

In addition, since the size of the dummy region storage node can be adjusted, guard patterning of the dummy region storage node, which can be a problem when applying the partial dip-out process, can be performed without great difficulty.

In addition, since the semiconductor device is formed by a partial dip-out process in which a sacrificial film remains in the peripheral area, a step difference between the cell area and the peripheral area is low, so that an interlayer insulating film may be easily formed after the formation of the capacitor.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail.

1 is a diagram illustrating a semiconductor device including a sealer capacitor according to an embodiment of the present invention.

As illustrated, an insulating film is formed in the cell region C and the peripheral region P on the semiconductor substrate 100 including the cell region C having the dummy region C at the edge portion and the peripheral region P. FIG. 102 is formed, and a plurality of storage node contacts 104 made of polysilicon are formed in the cell region C and the dummy region D. FIG.

A first etch stop layer 106 and a buffer layer 108 are provided on the storage node contact 104 and the insulating layer 120 in the dummy region D and the peripheral region P, and the cell region C is provided. A second etch stop layer 110 is provided on the storage node contact 104, the insulating layer 120, and the buffer layer 108 of the dummy region D and the peripheral region P. The first and second etch stop layers 106 and 110 may be formed of a nitride layer, and the buffer layer 108 may be formed of an oxide layer.

Storage nodes 116 made of TiN are formed on the storage node contact 104 of the cell region C except the dummy region D and on the first etch stop layer 106 of the dummy region D, respectively. do. The second etch stop layer 110 of the peripheral region P may be formed of a single layer or a double layer having a different etch selectivity.

Between the storage node 116 and on the sacrificial layer 112 of the peripheral area P, a support pattern made of a nitride layer that prevents the storage node 116 from falling and serves as a mask in a dip-out process. 114 is formed.

The dielectric layer 116 and the plate node 120 are formed on the surface of the storage node 116 and the support pattern 114 of a portion of the cell region C and the peripheral region P including the dummy region D. Thus, the capacitor 122 is formed in the cell region C.

An interlayer insulating layer 124 is provided on the plate node 120 and the sacrificial layer 112 of the peripheral region P.

On the other hand, the semiconductor device including the sealer-type capacitor according to the present invention is formed by the method as shown in Figures 2a to 2h.

Referring to FIG. 2A, an insulating film is formed in the cell region C and the peripheral region P on the semiconductor substrate 100 including the cell region C having the dummy region C at the edge portion and the peripheral region P. FIG. 102 is formed.

Then, an etching process is performed on the insulating layer 102 to form a plurality of contact holes in the cell region C and the dummy region D, respectively, and then a conductive material, preferably polysilicon, in each of the contact holes. Are embedded to form storage node contacts 104, respectively.

Subsequently, a first etch stop layer 106 made of a nitride layer is formed on the storage node contact 104 and the insulating layer 102 in the cell region C and the peripheral region P having the dummy region D. FIG. . The first etch stop layer 106 serves as a barrier layer during an etching process for forming a subsequent storage node, and also serves as a barrier layer for protecting a lower layer during a process of removing a subsequent sacrificial layer. .

Subsequently, after the buffer film 108 formed of an oxide film is formed on the first etch stop layer 106, the buffer film is formed only on the dummy region D and the peripheral region P of the edge of the cell region C. The buffer layer 108 and the first etch stop layer 106 of the cell region C are removed so that the 108 and the first etch stop layer 106 remain. The buffer layer 108 and the first etch stop layer 106 may have an edge portion perpendicular to an edge of the straw node contact 104 formed at the outermost side of the dummy region D in the cell region C. Or may extend so as to extend outside the outermost storage node contact 104 of the dummy area D, that is, in the direction of the cell area C.

Referring to FIG. 2B, a second nitride layer is formed on the storage node contact 104 and the insulating layer 102 of the cell region C and the buffer layer 108 of the dummy region D and the peripheral region P. Referring to FIG. An etch stop layer 110 is formed.

Then, a sacrificial layer 112 is formed on the second etch stop layer 110. The sacrificial layer 112 may be formed as a single layer or a double layer having different etch selectivity.

Subsequently, a supporting layer 114 is formed on the sacrificial layer 112 to prevent the storage node from lining after a subsequent dip-out process.

Referring to FIG. 2C, the support layer 114, the sacrificial layer 112, the second etch stop layer 110, and the buffer layer are formed in the storage node formation region of the cell region C including the dummy region D. An etching process of removing the 108 may be performed to form first and second holes H1 and H2 in the cell region C and the dummy region D, respectively. In this case, the storage node contact 104 is exposed by the first hole H1 in the cell region C excluding the dummy region D by the etching process, and the second hole (D) in the dummy region D. The first etch stop layer 106 is exposed by H2).

Referring to FIG. 2D, sidewalls of the first and second holes H1 and H2 and bottoms of the first and second holes H1 and H2, that is, the storage node contact 104 and the first etch stop are illustrated. A material for the storage node made of TiN is formed on the layer 106 and on the support layer 114 in the cell region C and the peripheral region P.

Then, the material for the storage node on the support layer 114 is removed to separate the material for the storage node so as to be connected to the storage node contact 104 in the cell region C except the dummy area D. In the dummy area D, a plurality of storage nodes 116 are formed on the first etch stop layer 106.

Subsequently, after forming a mask pattern (not shown) on the cell region C and the peripheral region P, an etching process is performed to interconnect the storage nodes 116 to each other. A support pattern 114 remaining on the portion and the peripheral region P is formed.

Since the support pattern 114 remaining in the peripheral region P serves as a mask covering the peripheral region P in a subsequent partial dip-out process, a separate mask process for covering the peripheral region P needs to be performed. There is no. The remaining support layer 114 sufficiently closes the peripheral region P and overlaps the storage node 116 of the dummy region D sufficiently so that the sacrificial layer P may be formed at an upper portion of the peripheral region P due to misalignment. 112) to prevent the occurrence of bunker phenomenon caused by loss.

Referring to FIG. 2E, the sacrificial layer of the cell region C including the dummy region D is removed by performing a partial dip-out process on the semiconductor substrate 100.

In this case, as the portion of the storage node 116 of the dummy region P has a size larger than that of the storage node 116 of the cell region C, the dummy region ( Even if the bottom portion of the storage node of P) is lost, the insulating layer 102 may be prevented by the first etch stop layer 106 disposed under the dip-out process to prevent bunker phenomenon. In addition, even when the bottom portion of the storage node 116 of the dummy region P is lost, the second etch stop layer 110 fixes the lower portion of the storage node 116. 116) The lining phenomenon can be prevented.

In addition, the storage node 116 in the dummy area (D), as shown in Figure 2f, serves as a guard (Guard) for the dip-out process and is formed integrally interconnected to prevent falling And alternately arranged. In the cross-sectional view for explaining an embodiment of the present invention, all of the storage nodes 116 formed in the dummy area D are illustrated for ease of description, and are shown in a shape separated from each other.

Referring to FIG. 2G, the dielectric layer 118 is formed on the support pattern 114 of the cell region C including the dummy region D and the support pattern 114 of the surface and the peripheral region P of the storage node 116. ) And a plate node 120 formed of a laminated film of a titanium nitride film and a polysilicon film to form a cylinder type capacitor 122.

The storage node 116 formed in the dummy area D is not connected to the lower storage node contact 104 by the first etch stop layer 106, thereby reducing the parasitic capacitance of the bit line.

Referring to FIG. 2H, after forming a mask pattern (not shown) on the plate node 120, an etching process is performed, and the plate node 120, the dielectric layer 118, and the support formed on the peripheral region P are formed. Remove the pattern 114. In this case, the mask pattern may be easily formed because there is no step between the cell region C and the peripheral region P. FIG.

Next, an interlayer insulating layer 124 is formed on the plate node 120 and the sacrificial layer 112 of the peripheral region P. Referring to FIG. In this case, since the step difference between the cell region C and the peripheral region P is low, the thickness of the interlayer insulating layer 124 may be reduced and the planarization process may be easily performed.

Subsequently, although not shown, a series of subsequent known processes are sequentially formed to manufacture a semiconductor device according to an embodiment of the present invention.

In addition, as shown in FIG. 3, the semiconductor device according to the present invention may be formed on the insulating layer 102 of the peripheral region P for easy connection between the metal lines formed in the peripheral region P and the bit lines. The first etch stop layer 106 may be formed so as to remain.

As described above, the present invention forms an etch stop layer on top of the dummy region, forms a storage node on top of the etch stop layer, and maintains a support pattern on the peripheral area to prevent the storage node from falling down, thereby providing a separate mask. A semiconductor device is manufactured by a method of performing a partial dip-out process without a process.

Therefore, it is possible to prevent the bunker phenomenon occurring due to the loss of the lower insulating film or during the partial dip-out process by removing the bottom of the dummy region storage node generated during the manufacturing of the semiconductor device using the conventional full-out process.

In addition, even when the bunker occurs, the storage node of the dummy area is fixed by the etch stop layer, thereby preventing the dummy area storage node from falling down.

In addition, since the storage node of the dummy region is formed on the etch stop layer formed of the nitride layer, the storage node of the dummy region is not connected to the storage node contact of the dummy region, thereby reducing the parasitic capacitance of the bit line.

In addition, since the size of the dummy region storage node can be adjusted, guard patterning of the dummy region storage node, which can be a problem when applying the partial dip-out process, can be performed without great difficulty.

In addition, since the semiconductor device is formed by a partial dip-out process in which the sacrificial film remains in the peripheral area, the step difference between the cell region and the peripheral area is low, so that the interlayer thin film can be easily formed after the formation of the capacitor.

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1 is a diagram illustrating a semiconductor device including a shielded capacitor according to an embodiment of the present invention.

2A to 2H are process-specific diagrams for describing a method of manufacturing a semiconductor device including a sealer capacitor according to another embodiment of the present invention.

3 illustrates a semiconductor device in accordance with another embodiment of the present invention.

Claims (20)

A semiconductor substrate including a cell region having a dummy region at an edge portion thereof and a peripheral region; An insulating film formed on the semiconductor substrate; A plurality of storage node contacts formed in the insulating film of the cell region including the dummy region; A first etch stop layer formed on the insulating layer including the storage node contact in the dummy area; A plurality of storage nodes formed on the storage node contacts of the cell area and the first etch stop layer of the dummy area; A second etch stop layer formed on the insulating layer of the cell region and the first etch stop layer of the dummy region and the peripheral region; A sacrificial layer formed on the second etch stop layer of the peripheral area; And A support pattern formed between the storage nodes such that the storage nodes are connected to each other; Semiconductor device comprising a. The method of claim 1, The first and second etching stop film is a semiconductor device, characterized in that consisting of a nitride film. The method of claim 1, The support pattern is a semiconductor device, characterized in that consisting of a nitride film. The method of claim 1, And a plate node formed on the dielectric layer and a plate node formed on the surface of the storage node. The method of claim 1, And a buffer layer formed between the first etch stop layer and the second etch stop layer of the dummy region. The method of claim 1, And a first etch stop layer formed over the insulating layer and under the second etch stop layer in the peripheral region. The method of claim 6, And a buffer layer formed between the first etch stop layer and the second etch stop layer in the peripheral area. The method according to claim 5 or 7, The buffer film is a semiconductor device, characterized in that consisting of an oxide film. The method of claim 1, The storage nodes formed in the dummy region are alternately arranged in plan view. The method of claim 1, And the storage nodes formed in the dummy region are integrally formed to be interconnected. Forming an insulating film on a semiconductor substrate including a cell region and a peripheral region having a dummy region at an edge portion thereof; Forming a plurality of storage node contacts in an insulating film of a cell region including the dummy region; Forming a first etch stop layer on the insulating layer of the dummy region and the peripheral region including the storage node contact formed in the dummy region; Forming an insulating layer including a storage node contact in the cell region, a first etch stop layer and a second etch stop layer in the dummy region and the peripheral region; Forming a sacrificial layer and a support layer on the second etch stop layer; Forming a plurality of holes to expose the storage node contact of the cell area and the first etch stop layer of the dummy area; Forming a storage node on sidewalls of each hole; Patterning the support layer in a cell region including the dummy region to connect the storage nodes to form a support pattern; And Removing the sacrificial layer of the cell region including the dummy region; Method for manufacturing a semiconductor device comprising a. The method of claim 11, And forming a buffer film on the first etch stop layer after the forming of the first etch stop layer and before the forming of the second etch stop layer. . The method of claim 12, And the buffer film is formed of an oxide film. The method of claim 11, The support film is a semiconductor device manufacturing method, characterized in that formed by a nitride film. The method of claim 11, The sacrificial film is a semiconductor device manufacturing method, characterized in that formed as a double film having a different etching selectivity. The method of claim 11, And the storage node is formed of TiN. The method of claim 11, The first and second etching stop film is a semiconductor device manufacturing method, characterized in that formed by the nitride film. The method of claim 11, After removing the sacrificial layer, forming a dielectric layer on a surface of the storage node and forming a plate node formed on the dielectric layer. The method of claim 11, The storage nodes formed in the dummy region are formed to be alternately arranged when viewed in plan view. The method of claim 11, The storage nodes formed in the dummy region are integrally formed to be connected to each other.

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