KR100942952B1 - Method for fabricating semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can improve the short channel margin and reliability of the device while forming a large compressive strain in the channel region, the present invention comprises the steps of forming a gate pattern on a substrate; Forming a separation protection layer on sidewalls of the gate pattern; Etching the substrate by a predetermined thickness using the gate pattern as an etching mask; Growing silicon germanium on the etched substrate; And forming a sidewall protective film on the sidewalls of the gate pattern, wherein in the growing of the germanium, the concentration of germanium in the silicon germanium is controlled to be 5% to 50%. By forming the source / drain region by ion implantation while forming a large compressive strain by growing the, it is possible to improve the short channel margin and reliability of the device.

Silicon germanium, LDD region, source / drain region, ion implantation, compressive deformation

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view for explaining a semiconductor device according to the prior art,

2 is a graph showing channel strain variation according to gate and source / drain distances,

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 substrate 32 device isolation film

33: gate pattern 34: separation protective film

35 recess 36 silicon germanium

37 sidewall protective film 38 source / drain region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of manufacturing a semiconductor device for short channel margin improvement.

Recently, in order to increase the operating current of a semiconductor device, a method of controlling strain in a channel region by applying mechanical stress to the device has been studied. That is, when a constant strain is formed in the channel region, the mobility of the carriers is affected to improve the operating current by using the influence of the mobility of the carriers.

In particular, when compressive strain is formed in the PMOS channel region, mobility of hole carriers is improved.

1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1, an isolation region 12 is formed on a semiconductor substrate 11 to define an active region, and a gate pattern 13 is formed on the semiconductor substrate 11. Here, the gate pattern 13 is formed in a stacked structure of the polysilicon electrode 13A, the tungsten electrode 13B, and the gate hard mask 13C. The passivation layer 14 is formed on the entire surface including the gate pattern 13, and the sidewall passivation layer 15 is formed on the passivation layer 14 of the sidewall of the gate pattern 13. Subsequently, the substrate between the sidewall protective layer 15 and the device isolation layer 12 is partially recessed to form a source / drain region in which the silicon germanium 16 is formed.

As described above, the prior art recesses the substrate in the source / drain region with the sidewall protective film 15 as a barrier, and then grows silicon germanium (SiGe) to form compressive strain in the channel.

However, if silicon germanium is formed only in the source / drain regions, the compressive strain applied to the channel region depends on the distance between the gate channel region and the silicon germanium formed in the source / drain, thereby improving compressive strain. There is a limit. In addition, in order to form a high compressive deformation, it is necessary to deepen the depth of the recess of the source / drain regions or to increase the germanium content in the silicon germanium. However, the deeper the depth of the recess in the source / drain region, the shorter channel margin of the transistor deteriorates, and the higher the germanium (Ge) content in the silicon germanium, such as point defects or dislocations. There arises a problem that the junction region leakage current is degraded by the defect.

2 is a graph showing channel strain variation according to gate and source / drain distances.

Referring to FIG. 2, it can be seen that as the distance between the gate and the source / drain increases from 10 nm to 30 nm, the channel strain decreases from -830 to -750.

The present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device that can secure short channel margin and improve reliability of a device while forming a large compressive strain in a channel region. have.

Method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate pattern on a substrate; Forming a separation protection layer on sidewalls of the gate pattern; Etching the substrate by a predetermined thickness using the gate pattern as an etching mask; Growing silicon germanium on the etched substrate; And forming a sidewall protective film on the sidewalls of the gate pattern, and in the growing silicon germanium, the concentration of germanium in the silicon germanium is controlled to 5% to 50%.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

As shown in FIG. 3A, the device isolation layer 32 is formed on the substrate 31. Here, the substrate 31 may be a semiconductor substrate in which a DRAM process is performed, and in particular, may be a substrate of a PMOS region. In addition, the device isolation layer 32 may be formed by a shallow trench isolation (STI) process.

Subsequently, a gate pattern 33 is formed on the substrate 31. The gate pattern 33 may be formed in a stacked structure of the polysilicon electrode 33A, the metal electrode 33B, and the gate hard mask 33C. In this case, the metal electrode 33B may be formed of metal or metal silicide, and the metal may be formed of tungsten and the metal silicide may be formed of tungsten silicide. The gate hard mask 33C may be formed of a nitride film.

Subsequently, a separation protective film 34 is formed on the entire surface of the resultant product including the gate pattern 33. The isolation protective layer 34 may be formed of an insulating layer to physically separate the channel region and the recess region when the substrate 31 of the LDD region is recessed. In this case, the insulating film may be formed of any one selected from the group consisting of SiO ₂ , Si ₃ N ₄ , SiBN, and SiON. In addition, it can be formed to a thickness of 20 ~ 300 Å to control the optimal LDD extension formation (optimal overlap between the gate and LDD) and the compressive strain of the channel region, and chemical vapor deposition (Chemical Vapor Deposition) Or it may be formed by the atomic layer deposit (Atomic Layer Depositon).

As shown in FIG. 3B, the recess 35 is formed by etching a predetermined thickness of the substrate 31 of the LDD region using the gate pattern 33 and the isolation protective layer 34 as an etching barrier. Here, the recess can be formed to a thickness of 20 kV to 500 kV in consideration of compressive deformation and short channel effects.

Therefore, all of the separation protection layer 34 formed on the substrate 31 is etched when the recess 35 is formed, and the separation protection layer 34A formed in the gate pattern 33 remains. Further, the recess 35 and the gate pattern 33 of the LDD region are physically separated by the thickness of the isolation protective layer 34A formed on the gate pattern 33.

As shown in FIG. 3C, silicon germanium (SiGe) 36 is grown in the recess 35. Here, the silicon germanium 36 may adjust the germanium (Ge) concentration in the silicon germanium 36 to 5% to 50% in order to control compressive deformation. In addition, when the silicon germanium 36 is grown, dopants may not be doped depending on the purpose, or at the same time, boron may be doped in-situ. During in-situ doping, the boron concentration may be adjusted to 1E18 to 4E20 / cm 2 to improve short channel margin.

As described above, by forming the silicon germanium 36 having a large volume in the LDD region, it is possible to form a high compressive strain, thereby increasing the operation speed of the device.

As shown in FIG. 3D, the sidewall protective layer 37 is formed on the sidewall of the gate pattern 33. Here, the sidewall protective layer 37 may be formed by forming an insulating layer on the entire surface of the resultant including the separation protective layer 34A and etching back to remain on the sidewall of the gate pattern 33. May be any one selected from the group of SiO ₂ , Si ₃ N ₄ , SiBN, and SiON.

Subsequently, the source / drain region 38 is formed by implanting the sidewall protective film 37 into the substrate 31 using the ion implantation barrier. Here, ion implantation may be performed by beamline ion implantation or plasma doping, and any one selected from the group of B, BF ₂ , BF ₃ , B + F _2, and BF ₂ + F may be used as a dopant. .

As described above, the LDD region forms the silicon germanium 36 and the source / drain region 38 is formed through ion implantation, thereby eliminating lattice defects caused by the recess 35 and the silicon germanium 36 of the substrate 31. It is possible to form a reliable device.

In the present invention, the LDD region grows silicon germanium 36 to form high compressive strain, and the source / drain region 38 is formed through ion implantation, thereby eliminating lattice defects, thereby forming a reliable device. have.

In addition, it is possible to form a shallow junction through the thickness control of the isolation protective film 34A and the ion implantation method of the source / drain 38 region, thereby improving the short channel margin of the device. There is an advantage.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of increasing the short channel margin and reliability of the device by growing silicon germanium in the channel region to form a large compressive strain while forming a source / drain region by ion implantation.

Claims (13)

Forming a gate pattern on the substrate; Forming a separation protection layer on sidewalls of the gate pattern; Etching the substrate by a predetermined thickness using the gate pattern as an etching mask; Growing silicon germanium on the etched substrate; And Forming a sidewall protective layer on sidewalls of the gate pattern; Including, In the step of growing the silicon germanium, The method of manufacturing a semiconductor device, characterized in that the concentration of germanium in the silicon germanium is adjusted to 5% to 50%. The method of claim 1, The separation protective film is a method of manufacturing a semiconductor device, characterized in that the insulating film. The method of claim 2, The insulating film is a semiconductor device manufacturing method, characterized in that any one selected from the group of SiO ₂ , Si ₃ N ₄ , SiBN and SiON. The method of claim 3, The insulating film is a method of manufacturing a semiconductor device, characterized in that formed by the chemical vapor deposition (Chemical Vapor Deposition) or atomic layer deposition (Atomic Layer Deposition) to a thickness of 20 ~ 300Å. The method of claim 1, Etching the substrate a predetermined thickness, A method for manufacturing a semiconductor device, characterized by etching a thickness of 20 kV to 500 kV. delete The method of claim 1, In the step of growing the silicon germanium, A method of manufacturing a semiconductor device, wherein the boron is doped with a dose of 1E18 to 4E20 / cm 2 in situ. The method of claim 1, And the sidewall protective film is formed of an insulating film. The method of claim 8, The insulating film is a semiconductor device manufacturing method, characterized in that any one selected from the group of SiO ₂ , Si ₃ N ₄ , SiBN and SiON. The method of claim 1, Forming the sidewall protective film, Forming an insulating film on the entire surface including the gate pattern; And And etching back the insulating film. The method of claim 1, After forming the sidewall protective film, Implanting ions into the substrate to form a source / drain Method of manufacturing a semiconductor device further comprising. The method of claim 11, The ion implantation method of the semiconductor device, characterized in that performed by beamline ion implantation or plasma doping. The method of claim 12, The ion implantation is a semiconductor device manufacturing method characterized in that carried out using any one selected from the group of B, BF ₂ , BF ₃ , B + F ₂ and BF ₂ + F as a source gas.

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