KR100936104B1 - Method for Manufacturing of Image Sensor - Google Patents

Abstract

An image sensor manufacturing method according to an embodiment may include forming first and second gates in a pixel region and a logic region of a semiconductor substrate; Forming an LED region on both sides of the first and second gates; Forming a first insulating layer on the semiconductor substrate including the first and second gates; Forming a first contact hole and a second contact hole to selectively expose the LED area in the first insulating layer; Forming a source region in the semiconductor substrate below the first contact hole and the second contact hole; Forming a first contact plug and a second contact plug in the first contact hole and the second contact hole; Forming a second insulating layer on the first insulating layer, the second insulating layer including metal wires respectively connected to the first and second contact plugs; And forming a photodiode on the second insulating layer.

Image Sensors, Photodiodes, Sources / Drains

Description

Method for Manufacturing of Image Sensor

In an embodiment, an image sensor manufacturing method is disclosed.

The image sensor is a semiconductor device that converts an optical image into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor may be divided into a photo diode region that receives a light signal and converts the light signal into an electrical signal, and a transistor region that processes the electrical signal. The CMOS image sensor is a structure in which photodiodes and transistors are horizontally disposed on a semiconductor substrate.

According to the horizontal CMOS image sensor, a photodiode and a transistor are formed adjacent to each other horizontally on a substrate. Accordingly, additional areas for photodiode formation are required.

The embodiment provides a method of manufacturing an image sensor that can provide vertical integration of transistor circuits and photodiodes.

In addition, the embodiment provides an image sensor manufacturing method in which resolution and sensor sensitivity can be improved together.

In addition, the embodiment provides a method of manufacturing an image sensor that suppresses the punch through phenomenon of a transfer transistor for signal processing while employing a vertical photodiode.

An image sensor manufacturing method according to an embodiment may include forming first and second gates in a pixel region and a logic region of a semiconductor substrate; Forming an LED region on both sides of the first and second gates; Forming a first insulating layer on the semiconductor substrate including the first and second gates; Forming a first contact hole and a second contact hole to selectively expose the LED area in the first insulating layer; Forming a source region in the semiconductor substrate below the first contact hole and the second contact hole; Forming a first contact plug and a second contact plug in the first contact hole and the second contact hole; Forming a second insulating layer on the first insulating layer, the second insulating layer including metal wires respectively connected to the first and second contact plugs; And forming a photodiode on the second insulating layer.

According to the image sensor manufacturing method according to the embodiment can provide a vertical integration of the transistor circuit (circuitry) and the photodiode.

In addition, according to the embodiment, the fill factor can be approached to 100% by vertical integration of the transistor circuit and the photodiode.

Further, according to the embodiment, it is possible to provide higher sensitivity at the same pixel size by vertical integration than in the prior art.

In addition, according to the embodiment it is possible to reduce the process cost for the same resolution (Resolution) than the prior art.

In addition, according to the exemplary embodiment, each unit pixel may implement a more complicated circuit without reducing the sensitivity.

In addition, the additional on-chip circuitry that can be integrated by the embodiment can increase the performance of the image sensor and further reduce the size and manufacturing cost of the device.

In addition, according to the embodiment, the photocharge transfer efficiency of the photodiode is improved, thereby improving image characteristics.

An image sensor manufacturing method according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

An image sensor manufacturing method according to an embodiment will be described with reference to FIGS. 1 to 8.

Referring to FIG. 1, a first gate electrode 100 and a second gate electrode 200 are formed on a semiconductor substrate 10.

The semiconductor substrate 10 may be a single crystal p-type substrate (p ++), and a low concentration p-type epi layer (p-Epi) may be formed on the semiconductor substrate 10 by performing an epitaxial process. have.

A plurality of device isolation layers defining an active region and a field region are formed in the semiconductor substrate 10. In addition, a circuit of the pixel area A and a circuit of the logic area B may be formed on the active area.

Although not shown, a channel portion may be formed by implanting p0 ions into the surface of the semiconductor substrate 10 including the pixel region A and the logic region B so as to adjust a threshold voltage and move charges.

The first gate electrode 100 and the second gate electrode 200 are formed in the pixel region A and the logic region B.

The first gate electrode 100 of the pixel region A may be a gate electrode of a transfer transistor. The first gate electrode 100 may be formed for each pixel. Although not shown, gates of a reset transistor, a drive transistor, and a select transistor may also be formed when the first gate electrode 100 is formed.

The first gate electrode 100 and the second gate electrode 200 may be patterned at the same time. That is, the first and second gate electrodes 100 and 200 may be formed by depositing and patterning a gate insulating film and a gate conductive film.

Lightly doped drain regions 110 and 210 are formed in the semiconductor substrate 10 using ion implantation of low concentration dopants on both sides of the first and second gate electrodes 100 and 200. For example, the LED regions 110 and 210 of the first and second gate electrodes 100 and 200 may be formed by ion implantation of n-type impurities.

Although not shown, a spacer may be formed by entirely depositing an oxide layer on the semiconductor substrate 10 including the first and second gate electrodes 100 and 200 and then performing an entire surface etching process. Alternatively, the spacer may not be formed.

Referring to FIG. 2, a first insulating layer 20 is formed on a semiconductor substrate 10 including the first and second gate electrodes 100 and 200. The first insulating layer 20 may be a pre-metal dielectric. For example, the first insulating layer 20 may be formed of an oxide film or a nitride film or may have a structure in which the films are stacked.

Referring to FIG. 3, a first photoresist pattern 310 is formed on the first insulating layer 20. The first photoresist pattern 310 is formed to expose the first insulating layer 20 corresponding to the LED region 110 of the first gate electrode 100 and cover the remaining region. The first photoresist pattern 310 may be formed by forming a photoresist film on the first insulating layer 20 by spin coating, followed by exposure and development processes.

The first insulating layer 20 is etched using the first photoresist pattern 310 as an etching mask. Then, first contact holes 121 and 122 are formed in the first insulating layer 20. The first contact holes 121 and 122 may expose the semiconductor substrate 10 on which the LED region 110 of the first gate electrode 100 is formed.

Thereafter, the first photoresist pattern 310 may be removed by an ashing process.

Referring to FIG. 4, a second photoresist pattern 320 is formed on the first insulating layer 20. The second photoresist pattern 320 is formed to expose the first insulating layer 20 corresponding to the LED region 210 of the second gate electrode 200 and cover the remaining region. The second photoresist pattern 320 may be formed by spin coating a photoresist layer on the first insulating layer 20 and then performing exposure and development processes.

The first insulating layer 20 is etched using the second photoresist pattern 320 as an etching mask. Then, a second contact hole 221 is formed in the first insulating layer 20. The second contact hole 221 may expose the semiconductor substrate 10 on which the LED region 210 of the second gate electrode 200 is formed.

Thereafter, the second photoresist pattern 320 may be removed by an ashing process.

As described above, the first contact holes 121 and 122 may be formed by the first photoresist pattern 310, and the second contact holes 221 may be formed by the second photoresist pattern 320. Then, when the first contact holes 121 and 122 and the second contact hole 221 are formed at the same time, it is possible to form a contact plug in the correct area by preventing misalignment. That is, when the contact hole is simultaneously formed in the pixel area A and the logic area B by one photo process, the formation position may not be exactly matched. Then, the position of the contact plug formed in a subsequent process may be formed in another region, which may cause a decrease in yield and a failure of the device. Accordingly, since the first contact holes 121 and 122 and the second contact hole 221 are formed by two photo processes, the misalignment can be prevented and the reliability of the device can be improved.

Referring to FIG. 5, first contact holes 121 and 122 and a second contact hole 221 are formed in the first insulating layer 20.

The first contact holes 121 and 122 selectively expose the LED areas 110 and 210 of the first gate electrode 100, and the second contact holes 221 may expose the LED areas 110 and 210 of the second gate electrode. ) Is selectively exposed.

Referring to FIG. 6, source regions 130 and 230 and drain regions 131 are formed in the first and second gate electrodes 100 and 200, respectively. The source regions 130 and 230 and the drain region 131 may be formed to be connected to the LED regions 110 and 210 by ion implanting a high concentration of dopant using the first insulating layer 20 as an ion implantation mask. The source region 130.230 and the drain region 131 may be formed of high concentration n-type impurities. Thereafter, a heat treatment process for activating the dopants implanted into the source regions 130 and 230 and the drain region 131 may be performed.

The source region 130 of the first gate electrode 100 may be the electron storage 130, and the drain region 131 may be the floating diffusion 131. That is, the electron storage unit 130 of the first gate electrode 100 may serve to receive the photoelectrons generated by the photodiode 60 formed in a subsequent process and deliver the photoelectrons to the floating diffusion unit 131. . Hereinafter, the source region 230 of the first gate electrode 100 is referred to as an electron storage unit 130, and the drain region 131 is referred to as a floating diffusion unit 131.

Referring to FIG. 7, a first contact plug 140 and a second contact plug 240 are formed in the first contact holes 121 and 122 and the second contact hole 221. It is formed in the first contact holes 121 and 122 and is electrically connected to the electronic storage unit 130. The second contact plug 240 is electrically connected to the source region 230 of the second gate electrode 200 through the second contact hole 221. The first and second contact plugs 140 and 240 may be formed by depositing a metal material in the first insulating layer 20 including the first and second contact holes 221 and then performing a CMP process. For example, the first and second contact plugs 140 and 240 may be formed of tungsten.

As described above, the electron storage unit 130 and the floating diffusion unit 131 may be formed on both sides of the first gate electrode 100 by an ion implantation process through the first contact holes 121 and 122. In addition, since the first contact plug 140 is formed by gap filling through the first contact holes 121 and 122, the first contact plug 140 is formed on the electronic storage unit 130. Therefore, since the first contact plug 140 is correctly connected to the electronic storage unit 130 through the first contact holes 121 and 122, the optoelectronic transmission efficiency may be improved.

In addition, since the electron storage unit 130 is formed by ion implantation through the first contact holes 121 and 122, the surface thereof is not damaged, thereby improving dark and saturation characteristics. This is because the first contact plug 140 is formed in the first contact holes 121 and 122 after the electronic storage unit 130 is formed through the first contact holes 121 and 122, and thus, the first contact plug 140 is formed. This is because the semiconductor substrate 10 is not damaged by the etching process.

Referring to FIG. 8, a metal wiring 40 and a second insulating layer 30 are formed on the first insulating layer 20 to be connected to the first and second contact plugs 140 and 240. The second insulating layer 30 including the metal wire 40 may be formed of a plurality of layers. For example, the second insulating layer 30 may be formed of an oxide film or a nitride film.

The metal wire 40 may be connected to the first and second contact plugs 140 and 240 to transmit photoelectrons generated in the upper portion of the photodiode 60 to the electronic storage 130. The metal wire 40 includes a metal wire M and a plug. The metal wire 40 may be formed of various conductive materials including metal, alloy, or salicide. For example, the metal wire 40 may be any one of aluminum, copper, cobalt, and tungsten.

Therefore, the metal wire 40 is connected to the electronic storage unit 130 formed for each unit pixel so that the photoelectrons generated in the upper photodiode 60 can be transmitted to the electronic storage unit 130.

Referring to FIG. 5, a photodiode 60 is formed on the second insulating layer 30 corresponding to the pixel area A so as to be connected to the metal wire 40.

Before the photodiode 60 is formed, a lower electrode 50 may be formed on the second insulating layer 30 so as to be connected to the metal wire 40. The lower electrode 50 is used to collect photoelectrons generated by the photodiode 60 and is separated for each pixel. In this case, the lower electrode 50 may be formed to have a wide area so that a large amount of electrons are transferred to the metal wire 40.

A photodiode 60 connected to the metal wire 40 is formed on the second insulating layer 30 including the lower electrode 50.

In an embodiment, the photodiode 60 may be a NIP diode. The NIP diode is formed of a structure in which a metal, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type amorphous silicon layer are bonded to each other. The structure of the photodiode may be formed of a structure such as P-I-N or N-I-P, I-P. For example, the n-type amorphous silicon layer, the intrinsic amorphous silicon layer, and the p-type amorphous silicon layer may be formed by a CVD process using a siren gas.

Alternatively, the photodiode 60 may be formed by forming a photodiode on a crystalline semiconductor substrate and then coupling the photodiode 60 onto the semiconductor substrate 10 including the lower electrode 100. That is, the photodiode 60 may be formed by performing an ion implantation process on a crystalline semiconductor substrate.

Accordingly, the photodiode 60 may be collected on the semiconductor substrate 10 including the transistor to bring the fill factor of the photodiode closer to 100%.

An upper electrode 70 is formed on the photodiode 60. The upper electrode 70 may be formed of a transparent electrode having good light transmittance and high conductivity. For example, the upper electrode 70 may be formed of any one of indium tin oxide (ITO), cardium tin oxide (CTO), and ZnO ₂ .

The third insulating layer 80 is formed on the second insulating layer 30 including the upper electrode 70. The third insulating layer 80 may selectively expose a portion of the upper electrode 70 and the metal wiring of the logic region B.

An upper wiring 90 is formed on the third insulating layer 80. The upper wiring 90 may be electrically connected to the upper electrode 70 and the metal wiring 40 of the logic region B through the third insulating layer 80. The upper wiring 90 may be formed of various conductive materials including metals, alloys or salicides.

The color filter 100 is formed on the upper electrode 70. The color filter 100 uses dyed photoresist, and one color filter 100 is formed for each unit pixel to separate colors from incident light. Each of the color filters 100 represents a different color and may be formed of three colors of red, green, and blue.

Although not shown, a micro lens may be additionally formed on the color filter 100.

According to the method of manufacturing the image sensor according to the embodiment, it is possible to provide vertical integration of the transistor circuit and the photodiode.

In addition, the fill factor can be approached to 100% by vertical integration of the transistor circuit and the photodiode.

In addition, the vertical integration can provide higher sensitivity at the same pixel size than the prior art.

In addition, each unit pixel can implement a more complex circuit without reducing the sensitivity.

In addition, in implementing the unit pixel of the photodiode, the light sensing ratio may be improved by increasing the surface area of the photodiode in the unit pixel.

In addition, the connection of the contact plug to which the photocharge of the photodiode is transferred and the electronic storage unit can be made accurately, thereby improving the photoelectron transmission efficiency.

In addition, since the electronic storage unit is formed through the contact hole of the contact plug, it is possible to prevent over-etching or misalignment, thereby improving dark defect and saturation characteristics.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be apparent to those who have

1 to 8 are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims (6)

Forming a first gate in the pixel region of the semiconductor substrate and forming a logic region second gate; Forming LED regions on both sides of the first and second gates, respectively; Forming a first insulating layer on the semiconductor substrate including the first and second gates; Forming a first contact hole in the first insulating layer to expose the LED region of the first gate and forming a second contact hole in the first insulating layer to expose the LED region of the second gate ; Forming a source region in each of the semiconductor substrate under the first contact hole and the second contact hole; Forming a first contact plug and a second contact plug in the first contact hole and the second contact hole, respectively; Forming a second insulating layer on the first insulating layer, the second insulating layer including metal wires respectively connected to the first and second contact plugs; And  And forming a photodiode on the second insulating layer. The method of claim 1, The step of forming the first contact hole, Forming a first photoresist pattern on the first insulating layer to expose the first insulating layer corresponding to the LED region of the first gate; And And etching the first insulating layer by using the first photoresist pattern as an etching mask. The method of claim 1, Forming the second contact hole, Forming a second photoresist pattern on the first insulating layer to expose the first insulating layer corresponding to the LED region of the second gate; And And etching the first insulating layer using the second photoresist pattern as an etching mask. The method of claim 1, The first and second contact plugs are formed by forming a metal layer on the first insulating layer including the first and second contact holes and then performing a CMP process. The method of claim 1, And the source regions of the first and second gates are formed of a high concentration of n-type impurities. The method of claim 1, And a source region of the first gate is used as an electronic storage.

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