KR100894504B1 - Memory self test comparative circuit and System On Chip including the circuit - Google Patents

Abstract

The memory self test comparison circuit and the memory self test comparison circuit can be used to quickly determine the functional error of the memory BIST circuit to be tested and to eliminate the inconvenience of always storing or knowing the expected output value of the MISR. A system on chip (SOC) is disclosed. The memory self-test comparison circuit receives a plurality of reference data output from a built-in self test (BIST) circuit used to self-test an electrical characteristic of the memory, and uses the received plurality of reference data to store the reference data. Outputs a comparison result signal to determine whether the BIST circuit operates normally. The SOC includes a BIST (Built In Self Test) circuit used to self-test an electrical characteristic of a memory, and a BIST signal processing circuit to output reference data processed by a plurality of signals output from the BIST circuit. And a memory self-test comparison circuit for outputting comparison data used for comparison with data and outputting a comparison result signal for determining whether the memory BIST circuit is normally operated.

Memory Built-in Self Test, Built In Self Test, SOC

Description

A memory self test comparative circuit and a system on chip including the circuit having a memory self test comparison circuit and the memory self test comparison circuit

1 is a block diagram of a BIST signal processing circuit used to check for failure of the circuit itself performing BIST.

FIG. 2 is a detailed circuit diagram when the MISR shown in FIG. 1 is 16 bits.

3 is a block diagram of an SOC having a memory self-test comparison circuit and the memory self-test comparison circuit in accordance with the present invention.

4 shows an example of the comparator shown in FIG. 3.

5 shows an example of the reservoir 340 shown in FIG.

6 is a waveform diagram of signals associated with the operation of a memory self-test comparison circuit in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a circuit for memory self-test comparison used for determining an operation error of a circuit which performs a self test of the memory device.

A common function of memory is to store data and to read the stored data externally. The test operation to check whether the memory operates normally is performed by writing a certain data pattern to the memory and reading the data pattern stored in the memory from the outside. In the past, the memory was supplied as a single chip, and users also used the memory by mounting the memory on a system board, but recently, the concept of a system on chip (SOC) system in which a system consists of a single chip has spread. .

If memory is included in one chip that implements the system, it is possible to test only the memory in the entire system, but it is necessary to consider the test in advance when designing and laying out the system. In order to test only the memory except the memory peripheral circuit, the memory test dedicated circuit and the input / output terminals of the memory test dedicated circuit must be designed and laid out simultaneously. The input / output terminal must be connected to a pad PAD and a package pin electrically connected to the pad, so that the memory can be distinguished and tested in a wafer state and a package state.

If a complex system is implemented on a single chip, the number of pins required for the system to exchange information with the outside world is increasing. Nevertheless, having to install pins that are used only for memory testing and not necessary for normal operation reduces chip efficiency. That is, since the pads and the pins need to be increased, the area of the semiconductor chip increases or the size of the package increases.

To solve this drawback, the concept of Design For Testability (DFT) was introduced, and one of them is the memory BIST (Built In Self Test). This method uses a test circuit that distinguishes and tests the memory in the system and outputs a signal to determine whether the memory is operating normally.

In general, the memory BIST should perform three functions.

First, the ability to generate a signal indicating that the test has ended.

Second, a function of generating a test result signal for checking the test result.

Third, the function that can check the failure of the circuit itself performing the BIST.

The first and second contents are used to determine whether the memory operates normally using the memory BIST, but the third contents are different from each other in determining whether the circuit itself that performs the BIST operates normally. Since the signal generated in the first and second processes is half-hearted in the state that the BIST circuit itself is not normally operated, the third process should be tested in parallel while the first and second contents are tested.

As a method of checking a failure of a circuit that performs BIST, a scan test method and a multiple input signature register (MISR) are most commonly used. The scan test circuit used for the scan test is simple, but in addition to the scan test circuit, a general logic circuit must be tested at the same time. There is a problem that it is difficult to determine whether or not it is part of the BIST circuit.

However, the method of using the MISR has the advantage that it is possible to immediately determine whether a failure occurs in the memory BIST circuit itself because only the memory BIST circuit is tested.

1 is a block diagram of a BIST signal processing circuit used to check for failure of the circuit itself performing BIST.

Referring to FIG. 1, the memory BIST signal processing circuit 100 includes a memory BIST signal compression circuit 110 and a MISR 150.

The memory BIST signal compression circuit 110 receives N (N is an integer) compression blocks 111 to 114 that receive a plurality of signals output from the memory BIST circuit used to BIST the memory and compress them into one bit signal. Equipped. The compression block 111 compresses a plurality of bits of signals output from the memory BIST circuit into one bit of signal B1 by using a logic circuit such as EX-OR or EX-NOR in several stages. The remaining compression blocks 112 to 114 also output signals 1 B through NB of 1 bit, respectively, as described above. Using the above compression blocks, the signal output from the memory BIST circuit can be compressed into a certain number of signals.

The MISR 150 compresses the N signals into signals having the characteristics of primitive polynomials shown in Equation 1 and outputs them as serial data (T / O).

The input signals Input0 to Input15 are assumed to be 16 signals output from the BIST signal processing circuit 110 for the convenience of description. The number of the sixteen input signals Input0 to Input15 is assumed for the description of the corresponding MISR, and the number may vary depending on the system.

FIG. 2 is a detailed circuit diagram of the MISR shown in FIG. 1.

Referring to FIG. 2 and Equation 1, a 16-bit (Bits) MISR includes a plurality of delay layers and a plurality of adders. Delays can usually be implemented using registers. MISR has a characteristic that the output (T / O) value changes compared to the expected value even when an unexpected value is applied to one of the plurality of input signals (Input0 to Input15). .

In order to check the functional error of the BIST circuit itself, the actual test result of the BIST circuit itself is obtained by processing the signals output from the BIST circuit in MISR, and the BIST circuit is designed and output in response to the test signal when the BIST circuit is normal. By comparing the expected output obtained by processing the signal to be processed in the MISR, it is determined whether the memory BIST circuit itself is broken.

In the related art, since the comparison process was performed through a test program, the expected output should always be recorded in the test program. The expected output should be taken into account whenever the program is written because the expected output is different depending on the system under test. The test program can be written by the system designer including the memory, but in most cases, the test engineer refers to the design contents provided by the system designer. Thus, it is clear that a test engineer who does not know the exact configuration of the memory will take a lot of time and effort to input the expected output accurately into the data of the program.

In addition, comparing the actual output with the expected output through the program takes a considerable time, and considering the delay time of the signal output from the terminal of the semiconductor chip, the possibility of an error in the comparison itself is always inherent.

The technical problem to be achieved by the present invention is a memory self-test comparison circuit that can quickly determine the functional error of the memory BIST circuit itself to be tested and to eliminate the inconvenience of always storing or know the expected output value of the MISR To provide.

Another object of the present invention is to provide a SOC (System On Chip) including the memory self-test comparison circuit.

The memory self-test comparison circuit according to the present invention for achieving the technical problem, receives a plurality of reference data output from the BIST (Built In Self Test) circuit used to self-test the electrical characteristics of the memory, the received A comparison result signal for determining whether the memory BIST circuit operates normally is output using a plurality of reference data. Here, the plurality of reference data is a signal output from the BIST circuit to determine whether the BIST circuit operates normally.

The SOC according to the present invention for achieving the above another technical problem, and outputs the BIST (Built In Self Test) circuit used to self-test the electrical characteristics of the memory and the reference data processing a plurality of signals output from the BIST circuit A memory self-test comparison circuit having a BIST signal processing circuit and outputting comparison data used to compare with the reference data and outputting a comparison result signal for determining whether the memory BIST circuit is normally operated. It is further provided.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As described above, the present invention is designed to eliminate the inconvenience of always storing or knowing the serial output value of the MISR. The advantage of this method is that it is possible to prevent mistakes made by engineers who make test patterns using the method of the present invention or by engineers who actually test the equipment.

3 is a block diagram of an SOC having a memory self-test comparison circuit and the memory self-test comparison circuit in accordance with the present invention.

Referring to FIG. 3, the SOC 300 includes a BIST signal processing circuit 100 and a memory self test comparison circuit 310.

The BIST signal processing circuit 100 outputs reference data RS that processes a plurality of signals output from a BIST circuit (not shown) used to self-test an electrical characteristic of a memory. The memory self-test comparison circuit 310 outputs the comparison data CS used to compare with the reference data RS and compares the comparison result signal O to determine whether the memory BIST circuit is normally operated. Outputs

The BIST signal processing circuit 100 includes a BIST signal compression block 110 and a multiple input signature register (MISR) 150 for memory self-test output. The BIST signal compression block 110 compresses a plurality of signals output from a BIST circuit (not shown) into N (N is an integer) signals D1 to DN. The memory self test output MISR 150 compresses the N signals D1 to DN output from the BIST signal compression block 110 to output the reference data RS. The MISR 150 for memory self-test output implements primitive polynomials having a characteristic in which an output signal is different even if an error occurs in one of the N signals D1 to DN.

The memory self test comparison circuit 310 includes a memory self test comparison MISR 320, a comparator 330, and a storage 340.

The memory self-test comparison MISR 320 outputs the comparison data CS used for comparison with the reference data RS output from the memory self-test output MISR 150. The elements constituting the memory self-test comparison MISR 320 include a plurality of delayers (squares). Here, the plurality of delay units may be implemented by a register. In the case of applying the present invention, the elements and structure of the memory self-test comparison MISR 320 should be equal to the number of bits of the memory self-test output MISR 150. In addition, the values of the registers constituting the memory self-test comparison MISR 320 output the same signal as the reference data RS output from the memory self-test output MISR 150 when the memory BIST circuit (not shown) normally operates. It is initially set or reset to a certain value so that Since this value is taken into consideration at the beginning of the design and then immediately reflected on the layout, the comparison data CS becomes a parameter that does not require attention in subsequent tests.

The comparator 330 compares the reference data RS and the comparison data CS and outputs a comparison result signal CSO. The comparator 330 includes two input logic gates for receiving the reference data RS and the comparison data CS and outputting a comparison result signal CSO. For example, the two input logic gates are provided. For example, EX-OR or EX-NOR can be used.

4 shows an example of the comparator shown in FIG. 3.

Referring to FIG. 4, as an example of the comparator 330, an EX-OR gate or an EX-NOR gate that receives two inputs RS and CS and outputs a comparison result signal CSO. Gate is shown.

Here, when the memory BIST circuit (not shown) is normally operated, the comparison result signal CSO continuously maintains a logic high or logic low state, and the memory BIST circuit (not shown) In case of abnormal operation, it transitions from logic high state to logic low state or from logic low state to logic high state. Therefore, when it is determined that the value of the comparison result signal CSO is constant, it may be determined that the memory BIST circuit (not shown) operates normally. On the contrary, when the value of the comparison result signal CSO is not constant, it may be determined that the memory BIST circuit (not shown) is abnormally operated. This decision can be easily determined by the test engineer visually or through the test equipment, and the engineer can choose which method to take.

The storage unit 340 stores the comparison result signal CSO for a predetermined time and outputs the result. It is also conceivable to use the storage 340 to ensure time for data transfer from a memory BIST circuit (not shown) to an output buffer (not shown).

5 shows an example of the reservoir 340 shown in FIG.

Referring to FIG. 5, the storage unit 340 may be implemented as a D-type flip-flop.

Outputs the comparison result signal CSO output from the comparator 330 or the comparison result signal O output from the storage 430 to the outside of the SOC so that an error of the memory BIST circuit (not shown) is outside the SOC. It is desirable to be able to judge.

6 is a waveform diagram of signals associated with the operation of a memory self-test comparison circuit in accordance with the present invention.

Here, the clock CLOCK is a signal for operating a register, and one reference data RS and comparison data CS are compared with each clock to output a comparison result signal CSO / O. When the memory BIST circuit is normal, the value of the comparison result signal CSO / O is maintained in a logic high or logic low state.

In the above description, the technical idea of the present invention has been described with the accompanying drawings, which illustrate exemplary embodiments of the present invention by way of example and do not limit the present invention. In addition, it is apparent that any person having ordinary knowledge in the technical field to which the present invention belongs may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

As described above, when the memory self-test comparison circuit and the SOC provided with the circuit according to the present invention are used, the expected output of the conventional memory self-test output MISR is calculated in advance by software, and the actual circuit is not stored in a specific place. It can be easily compared from the chip, and can be easily judged by a test program using an external device or a chip. Therefore, there is an advantage that a memory BIST circuit malfunction can be judged simply and quickly.

Claims (16)

Memory self-test comparison for receiving a plurality of reference data output from a BIST (Built In Self Test) circuit used to self-test the electrical characteristics of the memory, and outputs the comparison data used for comparison with the plurality of reference data signals Multiple Input Signature Register (MISR); And And a comparator for comparing the reference data and the comparison data to output a comparison result signal. delete The method of claim 1, wherein the comparison data, And the data is expected to be output from the memory BIST circuit when the memory BIST circuit operates normally. The method of claim 1, wherein the comparator, And a two input logic gate configured to receive the reference data and the comparison data and to output the comparison result signal. The method of claim 4, wherein the comparison result signal, When the memory BIST circuit operates normally, the logic high or logic low state is continuously maintained. And the memory BIST circuit transitions from a logic high state to a logic low state or from a logic low state to a logic high state when the memory BIST circuit is abnormally operated. The method of claim 1, And a storage unit for storing and outputting the comparison result signal. The method of claim 6, wherein the reservoir, A memory self-test comparison circuit, characterized in that it is a D-type flip-flop. In an SOC comprising a BIST (Built In Self Test) circuit used to self-test the electrical characteristics of the memory and a BIST signal processing circuit for outputting reference data processing a plurality of signals output from the BIST circuit, And a memory self-test comparison circuit for outputting comparison data used for comparison with the reference data and outputting a comparison result signal for determining whether the memory BIST circuit is normally operated. (System On Chip). The circuit of claim 8, wherein the memory self-test comparison circuit comprises: A memory self test comparison MISR for outputting comparison data used for comparison with the reference data signal; And And a comparator for comparing the reference data and the comparison data to output the comparison result signal. The method of claim 9, The memory self test comparison MISR includes a plurality of delay units connected in series. The plurality of delay units SOC, characterized in that the register (Register). The method of claim 10, wherein the memory self-test comparison MISR, And a predetermined value is initially set or reset in the register to output the same signal as the reference data signal when the memory BIST circuit operates normally. The method of claim 9, wherein the comparator, And a two input logic gate for receiving the reference data and the comparison data and outputting the comparison result signal. The method of claim 12, wherein the comparison result signal, When the memory BIST circuit operates normally, the logic high or logic low state is continuously maintained. And when the memory BIST circuit is abnormally operated, transition from a logic high state to a logic low state or from a logic low state to a logic high state. The circuit of claim 9, wherein the memory self test comparison circuit comprises: And a storage unit for storing and outputting a comparison result signal of the comparator. The method of claim 14, wherein the reservoir, SOC characterized in that the D-type flip-flop (Flip-Flop). The method of claim 14, SOC, characterized in that for outputting the comparison result signal output from the comparator or the storage to the outside of the SOC.

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