KR100871835B1 - Memory system and method of signaling of the same - Google Patents

Abstract

Disclosed are a memory system and a signal transmission method of a memory system capable of selectively setting a differential signaling mode and a single-ended signaling mode. The memory system includes a memory module including at least one semiconductor memory device, and a memory controller configured to set a signal transmission mode based on stack position information of each of the semiconductor memory devices. Signal transmission is performed between the memory controller and each of the semiconductor memory devices in a differential signal transmission mode, and signal transmission is performed between the semiconductor memory devices in a single-ended transmission method. Therefore, the memory system consumes less power.

Description

Memory system and signal transmission method of memory system {MEMORY SYSTEM AND METHOD OF SIGNALING OF THE SAME}

1 is a block diagram illustrating a conventional memory system.

2 is a block diagram illustrating a memory system according to a first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a method of identifying semiconductor memory devices included in the memory system shown in FIG. 2.

FIG. 4 is a flowchart illustrating a method of setting a signaling mode of the memory system shown in FIG. 2.

5 is a block diagram illustrating a memory system according to a second embodiment of the present invention.

6 is a block diagram illustrating a memory system according to a third exemplary embodiment of the present invention.

7 is a block diagram illustrating a memory system according to a fourth embodiment of the present invention.

8 is a block diagram illustrating a memory system according to a fifth embodiment of the present invention.

9 is a block diagram illustrating a memory system according to a sixth embodiment of the present invention.

10 is a block diagram illustrating a memory system according to a seventh embodiment of the present invention.

11 is a block diagram illustrating a memory system according to an eighth embodiment of the invention.

12 is a block diagram illustrating a memory system according to a ninth embodiment of the present invention.

13 is a block diagram illustrating a memory system according to a tenth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

Memory system: 100, 200, 300, 400, 500, 550, 600, 700, 800, 900

110, 210, 310, 410, 510, 560, 610, 710, 810, 910: memory module

120, 220, 320, 420, 520, 570, 620, 720, 820, 920: memory controller

The present invention relates to a memory system, and more particularly, to a memory system and a signal transmission method of a memory system capable of selectively setting a differential signaling mode and a single-ended signaling mode.

Since the operating speed of the CPU of a computer system is very high, for example several GHz or more, while the operating speed of the memory is relatively low, for example several hundred MHz, a chipset called a memory controller for interfacing between the computer system and the semiconductor memory device. Connect Data transfers between the computer system and the memory controller at high speed. The data is transferred between the memory controller and the semiconductor memory device at an operating speed of the memory.

As the operation speed of a semiconductor memory device is increased, signaling between a memory controller using a multi-slot method and a memory module equipped with a semiconductor memory device has revealed limitations. In addition, single-ended signal transmission has a limitation in signal transmission due to parasitic inductance generated between a motherboard and a memory module.

In order to solve the problem of signal transmission in such a memory system, a conventional point-to-point signal transmission is adopted instead of the multi-slot method. In addition, conventionally, a bus configuration having a repeater mode has been adopted to configure a high capacity memory module in a point-to-point signal transmission. In addition, in the related art, in order to speed up the signal transmission, a signal is transmitted in a differential signal transmission mode through most buses.

1 is a block diagram illustrating a conventional memory system. Referring to FIG. 1, a memory system includes a memory module 10 and a memory controller 20. The memory module 10 includes semiconductor memory devices 11, 12, 13, and 14. Communication between the memory controller 20 and each of the semiconductor memory devices 11, 12, 13, 14 and between the semiconductor memory devices 11, 12, 13, 14 is performed by buses 1, 2, 3, 4. , 5, 6, 7, 8). In the conventional memory system illustrated in FIG. 1, a signal is transmitted in a differential signaling mode through all buses 1, 2, 3, 4, 5, 6, 7, and 8.

Sending signals in differential signaling mode over all buses increases the power consumption of the memory system.

Accordingly, there is a need for a memory system capable of selectively setting a differential signaling mode and a single-ended signaling mode.

It is an object of the present invention to provide a memory system capable of selectively setting a differential signaling mode and a single-ended signaling mode using stack position information.

Another object of the present invention is to provide a signal transmission method of a memory system capable of selectively setting a differential channel mode and a single-ended channel mode using stack position information.

In order to achieve the above object, a memory system according to an exemplary embodiment includes a memory module including at least one semiconductor memory device, and a memory for setting a signal transmission mode using identifiers corresponding to the semiconductor memory devices. It includes a controller.

According to one embodiment of the present invention, the signal is transmitted in a differential signal transmission mode between the memory controller and each of the semiconductor memory devices, and the signal is transmitted in a single-ended transmission method between the semiconductor memory devices. You can transfer.

According to one embodiment of the present invention, the memory controller may set the signal transmission mode based on stack position information of each of the semiconductor memory devices.

A memory system signal transmission method according to an embodiment of the present invention includes setting a signal transmission mode using identifiers corresponding to semiconductor memory devices, and transmitting a signal in response to the signal transmission mode. .

According to an embodiment of the present invention, the setting of the transfer mode may include: giving the identifiers to the semiconductor memory devices; Setting a signal transmission mode of channels by using identifiers corresponding to the semiconductor memory devices; Performing reverse swizzling on the channels; And providing the set signal transmission mode value to the semiconductor memory devices.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, operations, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

The semiconductor memory device in the memory module according to the embodiment of the present invention may be composed of DRAM, for example, DDR2, DDR3.

2 is a block diagram illustrating a memory system according to a first embodiment of the present invention.

Referring to FIG. 2, the memory system 100 includes a memory module 110 and a memory controller 120.

The memory module 110 includes a first semiconductor memory device (0A) 114, a second semiconductor memory device (1A) 113, a third semiconductor memory device (0B) 112, and a fourth semiconductor memory device 1B. (111). The memory controller 120 sets a signaling mode based on stack position information of each of the semiconductor memory devices 111, 112, 113, and 114.

Signaling is performed between the memory controller 120 and each of the semiconductor memory devices 111, 112, 113, and 114 through the buses 101, 105, and 108, and the semiconductor memory devices 111, Signaling is performed between the buses 102, 103, 104, 106 and 107 between 112, 113 and 114. In FIG. 2, a bus drawn in bold lines represents a bus in which signals are transmitted in a differential signaling mode, and a bus drawn in thin lines represents a bus in which a signal is transmitted in a single-ended signaling mode. Indicates.

The first semiconductor memory device 0A 114 receives a first packet WR / CA from the memory controller 120 in a differential signaling mode through a first port (not shown), and a second port (not shown). The first packet WR / CA is outputted through the C1 and first read data is output through a third port (not shown). The first port (not shown) is electrically coupled to the memory controller 120 through the first bus 101.

The second semiconductor memory device 1A and 113 are coupled to the first semiconductor memory device 0A 114 and the first packet WR / in a single-ended signal transmission mode through a fourth port (not shown). Receive the first read data in a single-ended signaling mode through a fifth port (not shown), generate second read data RD1 through a sixth port (not shown), and generate a differential signal. The second read data RD1 is transmitted to the memory controller 120 in a transfer mode. The second port and the fourth port are electrically coupled through a second bus 102, and the third port and the fifth port are electrically coupled through a third bus 103. The sixth port and the memory controller 120 are electrically coupled through the fourth bus 105.

The third semiconductor memory device (0B) 112 is coupled to the first semiconductor memory device (0A) 114, and the first packet WR / CA in a single-ended signaling mode through a seventh port (not shown). ), The first packet WR / CA is output through the eighth port (not shown), and the third read data is output through the ninth port (not shown). The seventh port and the second port are electrically coupled via a fifth bus 104.

The fourth semiconductor memory device 1B and 111 are coupled to the third semiconductor memory device 0B and 112, and the first packet WR / CA is in a single-ended signal transmission mode through a tenth port (not shown). ) And receive the third read data in the single-ended signaling mode through the eleventh port (not shown), output the fourth read data through the twelfth port (not shown), and output the fourth read data in the differential signaling mode. The fourth read data RD2 is transmitted to the memory controller 120. The eighth port and the tenth port are electrically coupled through a sixth bus 106, and the ninth port and the eleventh port are electrically coupled through a seventh bus 107. The twelfth port and the memory controller 120 are electrically coupled through the eighth bus 108.

In FIG. 2, "0A" and "0B" represent the 0th rank semiconductor memory devices paired with each other, and "1A" and "1B" represent the first rank semiconductor memory devices paired with each other.

The first packet WR / CA is data in which write data, commands, and addresses are merged.

FIG. 3 is a block diagram illustrating a method of identifying semiconductor memory devices included in the memory system 100 illustrated in FIG. 2.

In FIG. 3, the semiconductor memory devices 111, 112, 113, and 114 have a first control pin LASB1 and a second control pin LASB2, respectively, for receiving control signals. Buses 101, 102, 104, 106 in FIG. 2 are subbuses 101a, 101b, subbuses 102a, 102b, subbuses 104a, 104b, and subbuses 106a, respectively. , 106b).

The first control signal CA is input to the first control pin LASB1 of the first semiconductor memory device 0A 114 and the third semiconductor memory device 0B 112 having the same rank number. In addition, the first control signal CA is input to the second control pin LASB2 of the second semiconductor memory device 1A and 113 and the fourth semiconductor memory device 1B and 111 having the same rank number. . The second control signal CB is input to the second control pin LASB2 of the first semiconductor memory device 0A 114 and the third semiconductor memory device 0B 112 having the same rank number. The second control signal CB is input to the first control pin LASB1 of the second semiconductor memory device 1A and 113 and the fourth semiconductor memory device 1B and 111 having the same rank number. . Therefore, the rank number of the semiconductor memory devices 111, 112, 113, and 114 may be determined by the input of the control signals.

The first packet WR / CA is input to the first semiconductor memory device 0A 114 through the sub-buses 101a and 101b, and the first semiconductor memory device (B) through the sub-buses 102a and 102b. 0A). In addition, the first packet WR / CA is input to the second semiconductor memory device 1A 113 through the sub-buses 102a and 102b. In addition, the first packet WR / CA is input to the third semiconductor memory device 0B 112 through the sub-buses 104a and 104b and the third semiconductor memory through the sub-buses 106a and 106b. It is output from the device (0B) 112. In addition, the first packet WR / CA is input to the fourth semiconductor memory device 1B 111 through the sub-buses 106a and 106b.

In FIG. 3, the sub-buses 101a, 102a, 104a, 106a are coupled to ports at the same location of each of the semiconductor memory devices 111, 112, 113, 114, and the sub-buses 101b, 102b, 104b and 106b are coupled to ports at the same location of each of the semiconductor memory devices 111, 112, 113, and 114. The first packet WR / CA output from the first semiconductor memory device 0A 114 is the same as the position of the pin to which the sub-buses 101a and 101b of the first semiconductor memory device 0A 114 are coupled. It is input through the pins of the second semiconductor memory device 1A (113) at the position.

However, the sub-buses 104a and 104b are twisted and coupled when they are coupled to the sub-buses 102a and 102b. This is called swizzling. The sub bus 104a is coupled to the sub bus 102b, and the sub bus 104b is coupled to the sub bus 102a. Therefore, the first packet WR / CA output from the first semiconductor memory device 0A 114 is located at the pin where the sub-buses 101a and 101b of the first semiconductor memory device 0A 114 are coupled. It is input through the pins of the third semiconductor memory device (0B) 112 at a different position from the other. For example, a signal input through the sub-bus 101a is input to the second semiconductor memory device 1A and 113 through the sub-bus 102a and the third semiconductor memory device (through the sub-bus 104b). 0B) 112. The signal input through the sub-bus 101b is input to the second semiconductor memory device 1A and 113 via the sub-bus 102b, but the third semiconductor memory device 0B through the sub-bus 104a. It is entered at 112. Accordingly, the first packet WR / CA is input through the pins at the same positions of the first semiconductor memory device 0A 114 and the second semiconductor memory device 1A 113. 0B) 112 and the fourth semiconductor memory device 1B 111 are input via the same pin. However, the first packet WR / CA is input through pins at different positions of the first semiconductor memory device 0A 114 and the third semiconductor memory device 0B 112. Since the memory system 100 of FIG. 2 has a swizzling scheme, it may identify "0A" and "0B" and may identify "1A" and "1B".

Accordingly, the memory system 100 of FIG. 2 can distinguish rank numbers of the semiconductor memory devices 111, 112, 113, and 114 by input of control signals, and may be distinguished from "A" and "B" by swizzling. Can be distinguished. Semiconductor memory devices having the same rank number operate simultaneously in response to commands.

FIG. 4 is a flowchart illustrating a method of setting a signaling mode of the memory system shown in FIG. 2.

The memory controller sets the signal transmission mode based on the stack position information of each of the semiconductor memory devices.

Referring to FIG. 4, the setting of the transmission mode may include assigning identifiers to semiconductor memory devices (S1), and setting signal transmission modes of channels using identifiers corresponding to the semiconductor memory devices (S2). Performing reverse swizzling on the channels (S3), and providing the set signal transmission mode value to the semiconductor memory devices (S4).

5 is a block diagram illustrating a memory system according to a second embodiment of the present invention.

Referring to FIG. 5, the memory system 200 includes a memory module 210 and a memory controller 220.

The memory module 210 includes a first semiconductor memory device (0A) 212 and a second semiconductor memory device (0B) 211. The memory controller 220 sets a signaling mode based on stack position information of each of the semiconductor memory devices 211 and 212. In FIG. 5, a bus drawn in bold lines represents a bus in which signals are transmitted in a differential signaling mode, and a bus drawn in thin lines is a bus in which a signal is transmitted in a single-ended signaling mode. Indicates.

The first semiconductor memory device (0A) 212 receives a first packet WR / CA from the memory controller in a differential signaling mode through a first port (not shown), and receives a second port (not shown). The first packet WR / CA is output through the first packet, the first read data RD1 is output through a third port (not shown), and the first read data RD1 is output in the differential signal transmission mode. To transmit. The memory controller 220 and the first port are electrically coupled through the first bus 201, and the third port and the memory controller 220 are electrically coupled through the third bus 203.

The second semiconductor memory device (0B) 211 is coupled to the first semiconductor memory device (0A) 212, and the first packet WR / CA in a single-ended signal transmission mode through a fourth port (not shown). ), Generates second read data RD2 through a fifth port (not shown), and transmits second read data RD2 to the memory controller 220 in a differential signaling mode. The second port and the fourth port are electrically coupled through the second bus 202, and the fifth port and the memory controller 220 are electrically coupled through the fourth bus 204.

The first packet WR / CA is data in which write data, commands, and addresses are merged.

6 is a block diagram illustrating a memory system according to a third exemplary embodiment of the present invention.

Referring to FIG. 6, the memory system 300 includes a memory module 310 and a memory controller 320.

The memory module 310 includes a first semiconductor memory device (0A) 312 and a second semiconductor memory device (0B) 311. The memory controller 320 sets a signaling mode based on stack position information of each of the semiconductor memory devices 311 and 312. In FIG. 6, a bus drawn in bold lines represents a bus in which signal transmission is performed in a differential signaling mode.

The first semiconductor memory device 0A 312 receives the first packet WR / CA from the memory controller 320 in the differential signaling mode through the first port (not shown), and the second port (not shown). In this case, the first read data RD1 is generated and the first read data RD1 is transmitted to the memory controller 320 in the differential signal transmission mode. The memory controller 320 and the first port are electrically coupled through the first bus 301, and the second port and the memory controller 320 are electrically coupled through the second bus 303.

The second semiconductor memory device (0B) 311 is coupled to the memory controller 320, and the first packet WR / CA from the memory controller 320 in a differential signaling mode through a third port (not shown). The second read data RD2 is generated through the fourth port (not shown) and the second read data RD2 is transmitted to the memory controller 320 in the differential signal transmission mode. The memory controller 320 and the third port are electrically coupled through the third bus 302, and the fourth port and the memory controller 320 are electrically coupled through the fourth bus 304.

The first packet WR / CA is data in which write data, commands, and addresses are merged.

7 is a block diagram illustrating a memory system according to a fourth embodiment of the present invention.

Referring to FIG. 7, the memory system 400 includes a memory module 410 and a memory controller 420.

The memory module 410 may include a first semiconductor memory device (0A) 414, a second semiconductor memory device (1A) 413, a third semiconductor memory device (0B) 412, and a fourth semiconductor memory device 1B. 411). The memory controller 420 sets a signaling mode based on stack position information of each of the semiconductor memory devices 411, 412, 413, and 414. In FIG. 7, a bus drawn in bold lines represents a bus in which signals are transmitted in a differential signaling mode, and a bus drawn in thin lines is a bus in which a signal is transmitted in a single-ended signaling mode. Indicates.

The first semiconductor memory device (0A) 414 receives the first packet WR / CA from the memory controller 420 in a differential signaling mode through a first port (not shown), and the second port (not shown). The first packet WR / CA is outputted through the C1 and first read data is output through a third port (not shown). The memory controller 420 and the first port (not shown) of the first semiconductor memory device 0A 414 are electrically coupled through the first bus 401.

The second semiconductor memory device (1A) 413 is coupled to the first semiconductor memory device (0A) 414 and is single from the first semiconductor memory device (0A) 414 through a fourth port (not shown). Receives a first packet (WR / CA) in the end-end signaling mode, receives the first read data in a single-ended signaling mode through a fifth port (not shown), and receives the first packet through the sixth port (not shown). The second read data is generated and the second read data is transmitted to the memory controller 420 in the differential signaling mode. The second port and the fourth port are electrically coupled through a second bus 402, and the third port and the fifth port are electrically coupled through a third bus 403. The sixth port and the memory controller 420 are electrically coupled through the fourth bus 405.

The third semiconductor memory device (0B) 412 is coupled to the memory controller 420, and the first packet (WR / CA) in differential signaling mode from the memory controller 420 through a seventh port (not shown). Receive the first packet, output the first packet WR / CA through the eighth port (not shown), and output the third read data through the ninth port (not shown). The seventh port and the second port are electrically coupled via a fifth bus 404.

The fourth semiconductor memory device (1B) 411 is coupled to the third semiconductor memory device (0B) 412 and is single from the third semiconductor memory device (0B) 412 through a tenth port (not shown). Receives the first packet (WR / CA) in the ended signaling mode, receives the third read data in the single ended signaling mode through an eleventh port (not shown), and receives the third packet through the twelfth port (not shown). Four read data RD2 are generated and the fourth read data RD2 is transmitted to the memory controller 420 in a differential signal transmission mode. The eighth port and the tenth port are electrically coupled through a sixth bus 406, and the ninth port and the eleventh port are electrically coupled through a seventh bus 407. The twelfth port and the memory controller 420 are electrically coupled through the eighth bus 408.

The first packet WR / CA is data in which write data, commands, and addresses are merged.

8 is a block diagram illustrating a memory system according to a fifth embodiment of the present invention.

Referring to FIG. 8, the memory system 500 includes a memory module 510 and a memory controller 520.

The memory module 510 includes a first semiconductor memory device (0A) 514, a second semiconductor memory device (1A) 513, a third semiconductor memory device (2A) 512, and a fourth semiconductor memory device 3A. 511, fifth semiconductor memory device (0B) 518, sixth semiconductor memory device (1B) 517, seventh semiconductor memory device (2B) 516, and eighth semiconductor memory device 3B ( 515). The memory controller 520 sets a signaling mode based on stack position information of each of the semiconductor memory devices 511, 512, 513, 514, 515, 516, 517, and 518. In FIG. 8, a bus drawn in bold lines represents a bus for signaling in a differential signaling mode, and a bus drawn in thin lines represents a bus for signaling in a single-ended signaling mode. Indicates.

The first semiconductor memory device 0A 514 receives the first packet WR / CA from the memory controller 520 in the differential signaling mode through the first port (not shown), and the second port (not shown). The first packet WR / CA is outputted through the C1 and first read data is output through a third port (not shown).

The second semiconductor memory device 1A 513 is coupled to the first semiconductor memory device 0A 514 and is single from the first semiconductor memory device 0A 514 via a fourth port (not shown). Receives a first packet (WR / CA) in the end-end signaling mode, receives the first read data in a single-ended signaling mode through a fifth port (not shown), and receives the first packet through the sixth port (not shown). 2 Output read data.

The third semiconductor memory device 2A 512 is coupled to the first semiconductor memory device 0A 514 and the second semiconductor memory device 1A 513 and through a seventh port (not shown). Receives the first packet WR / CA from the first semiconductor memory device 0A 514 in the single-ended signaling mode and transmits the second read data in the single-ended signaling mode through an eighth port (not shown). Receive and output third read data through a ninth port (not shown).

The fourth semiconductor memory device 3A 511 is coupled to the first semiconductor memory device 0A 514 and the third semiconductor memory device 2A 512 and through a tenth port (not shown). Receives the first packet WR / CA from the first semiconductor memory device 0A 514 in the single-ended signaling mode and transmits the third read data in the single-ended signaling mode through an eleventh port (not shown). Receive the fourth read data RD1 through the twelfth port (not shown), and transmit the fourth read data RD1 to the memory controller 520 in the differential signal transmission mode.

The fifth semiconductor memory device (0B) 518 receives the first packet WR / CA from the memory controller 520 in a differential signaling mode through a thirteenth port (not shown), and receives a fourteenth port (not shown). The first packet WR / CA is output through the N-th output terminal, and the fifth read data is output through the fifteenth port (not shown).

The sixth semiconductor memory device (1B) 517 is coupled to the fifth semiconductor memory device (0B) 518 and is single from the fifth semiconductor memory device (0B) 518 through a sixteenth port (not shown). Receives a first packet WR / CA in an ended signaling mode, receives the fifth read data in a single ended signaling mode through a seventeenth port (not shown), and transmits the fifth read data through an eighteenth port (not shown). 6 Output read data.

The seventh semiconductor memory device (2B) 516 is coupled to the fifth semiconductor memory device (0B) 518 and the sixth semiconductor memory device (1B) 517 and through a nineteenth port (not shown). The first packet WR / CA is received from the fifth semiconductor memory device 0B 518 in the single-ended signaling mode, and the sixth read data is transmitted in the single-ended signaling mode through the 20th port (not shown). Receive and output the seventh read data through the twenty-first port (not shown).

An eighth semiconductor memory device (3B) 515 is coupled to a fifth semiconductor memory device (0B) 518 and the seventh semiconductor memory device (2B) 516 and through a twenty-second port (not shown). The first packet WR / CA is received from the fifth semiconductor memory device 0B 518 in the single-ended signaling mode, and the seventh read data is transmitted in the single-ended signaling mode through a twenty-third port (not shown). Receives the eighth read data RD2 through the twenty-fourth port (not shown) and transmits the eighth read data RD2 to the memory controller 520 in the differential signal transmission mode.

The first packet WR / CA is data in which write data, commands, and addresses are merged.

9 is a block diagram illustrating a memory system according to a sixth embodiment of the present invention.

9, a memory system 550 includes a memory module 560 and a memory controller 570.

The memory module 560 includes a semiconductor memory device (0A) 565. The memory controller 570 sets a signaling mode based on the stack position information of the semiconductor memory device 565. In FIG. 9, a bus drawn in bold lines represents a bus in which signal transmission is performed in a differential signaling mode.

The semiconductor memory device 0A 565 receives the first packet WR / CA from the memory controller 570 in a differential signal transmission mode through a first port (not shown), and receives a second port (not shown). The first read data RD1 is output through the second read data RD2 through the third port (not shown), and the first read data RD1 and the second read data RD2 are output in the differential signal transmission mode. To the memory controller 570.

The first packet WR / CA is data in which write data, commands, and addresses are merged.

10 is a block diagram illustrating a memory system according to a seventh embodiment of the present invention.

Referring to FIG. 10, the memory system 600 includes a memory module 610 and a memory controller 620.

The memory module 610 may include a first semiconductor memory device (0A) 614, a second semiconductor memory device (1A) 613, a third semiconductor memory device (2A) 612, and a fourth semiconductor memory device 3A. 611, the fifth semiconductor memory device (0B) 618, the sixth semiconductor memory device (1B) 617, the seventh semiconductor memory device (2B) 616, and the eighth semiconductor memory device (3B) 615. The memory controller 620 sets a signaling mode based on stack position information of each of the semiconductor memory devices 611, 612, 613, 614, 615, 616, 617, and 618. In FIG. 10, a bus drawn in bold lines represents a bus for signaling in a differential signaling mode, and a bus drawn in thin lines represents a bus for signaling in a single-ended signaling mode. Indicates.

The first semiconductor memory device (0A) 614 receives the first packet WR / CA from the memory controller 620 in a differential signaling mode through a first port (not shown), and receives the first packet WR / CA through the second port. Output a first packet (WR / CA), receive first read data in a single-ended signaling mode through a third port, output second read data through a fourth port, and read the second read out in a differential signaling mode The data RD1 is transmitted to the memory controller 620.

The second semiconductor memory device (1A) 613 is coupled to the first semiconductor memory device (0A) 614 and transmits a single-ended signal from the first semiconductor memory device (0A) 614 through a fifth port. The first packet WR / CA is received in the mode, the third read data is received in the single-ended signaling mode through the sixth port, and the first read data is output through the seventh port.

The third semiconductor memory device (2A) 612 is coupled to the first semiconductor memory device (0A) 614 and the second semiconductor memory device (1A) 613, and the first semiconductor memory through the eighth port. Receive a first packet (WR / CA) from device (0A) 614 in single-ended signaling mode and receive fourth read data in single-ended signaling mode through a ninth port, and through the tenth port The third read data is output.

The fourth semiconductor memory device (3A) 611 is coupled to the first semiconductor memory device (0A) 614 and the third semiconductor memory device (2A) 612, and the first semiconductor memory device through the eleventh port. (0A) 614 receives the first packet (WR / CA) in single-ended signaling mode and outputs the fourth read data through the twelfth port.

The fifth semiconductor memory device (0B) 618 receives the first packet WR / CA from the memory controller 620 in a differential signaling mode through a thirteenth port, and receives the first packet (WR / CA) through a fourteenth port. WR / CA) and receives the fifth read data in the single-ended signaling mode through the fifteenth port, outputs the sixth read data through the sixteenth port, and stores the sixth read data in the differential signaling mode. To 620.

The sixth semiconductor memory device (1B) 617 is coupled to the fifth semiconductor memory device (0B) 618, and the first packet WR in the single-ended signal transfer mode from the fifth semiconductor memory device through the seventeenth port. / CA) to receive the seventh read data in the single-ended signaling mode through the eighteenth port, and output the fifth read data through the nineteenth port.

The seventh semiconductor memory device (2B) 616 is coupled to the fifth semiconductor memory device (0B) 618 and the sixth semiconductor memory device (1B) 617, and the fifth semiconductor memory through the 20th port. Receive a first packet (WR / CA) from device (0B) 618 in single-ended signaling mode and receive eighth read data in single-ended signaling mode through port twenty-one, and through the twenty-second port The seventh read data is output.

An eighth semiconductor memory device (3B) 615 is coupled to a fifth semiconductor memory device (0B) 618 and the seventh semiconductor memory device (2B) 616, the fifth semiconductor memory through the twenty-third port Receives a first packet (WR / CA) from device (0B) 618 in single-ended signaling mode and outputs the eighth read data through a twenty-fourth port.

The first packet WR / CA is data in which write data, commands, and addresses are merged.

11 is a block diagram illustrating a memory system according to an eighth embodiment of the invention.

Referring to FIG. 11, the memory system 700 includes a memory module 710 and a memory controller 720.

The memory module 710 includes a first semiconductor memory device (0A) 714, a second semiconductor memory device (1A) 713, a third semiconductor memory device (0B) 712, and a fourth semiconductor memory device 1B. 711. The memory controller 720 sets a signaling mode based on stack position information of each of the semiconductor memory devices 711, 712, 713, and 714. In FIG. 11, a bus drawn in bold lines indicates a bus in which signals are transmitted in a differential signaling mode, and a bus drawn in thin lines indicates a signal in a single-ended signaling mode. Represents a bus.

The first semiconductor memory device (0A) 714 receives the first packet WR / CA from the memory controller 720 through the first port in the differential signaling mode, and receives the first packet WR through the second port. / CA) and receives first read data in a single-ended signaling mode through a third port, outputs second read data through a fourth port, and outputs the second read data in a differential signaling mode to a memory controller. 720). The first port and the memory controller 720 are electrically coupled through the first bus 701, and the second port and the memory controller 720 are electrically coupled through the second bus 708.

The second semiconductor memory device (1A) 713 is coupled to the first semiconductor memory device (0A) 714 and is a single-ended signal transfer mode from the first semiconductor memory device (0A) 714 through a fifth port. The first packet WR / CA is received and the first read data is output through the sixth port. The third port and the fifth port are electrically coupled through a third bus 702, and the fourth port and the sixth port are electrically coupled through a fourth bus 703.

The third semiconductor memory device (0B) 712 is coupled to the first semiconductor memory device (0A) 714 and is in a single-ended signal transfer mode from the first semiconductor memory device (0A) 714 through a seventh port. Receives the first packet (WR / CA) through the first port, outputs the first packet (WR / CA) through the eighth port, and receives the third read data in the single-ended signaling mode through the ninth port; The fourth read data is output through the fourth read data and is transmitted to the memory controller 720 in the differential signal transmission mode. The seventh port and the third port are electrically coupled through the fifth bus 704, and the eighth port and the memory controller 720 are electrically coupled through the sixth bus 705.

The fourth semiconductor memory device (1B) 711 is coupled to the third semiconductor memory device (0B) 712 and has a single-ended signal transfer mode from the third semiconductor memory device (0B) 712 through the eleventh port. The first packet WR / CA is received and the third read data is output through the twelfth port. The ninth port and the eleventh port are electrically coupled through a seventh bus 706, and the tenth port and the twelfth port are electrically coupled through an eighth bus 707.

In FIG. 11, the first packet WR / CA is data in which write data, commands, and addresses are merged.

12 is a block diagram illustrating a memory system according to a ninth embodiment of the present invention.

Referring to FIG. 12, the memory system 800 includes a memory module 810 and a memory controller 820.

The memory module 810 includes a first semiconductor memory device (0A) 814, a second semiconductor memory device (1A) 813, a third semiconductor memory device (0B) 812, and a fourth semiconductor memory device 1B. 811. The memory controller 820 sets a signaling mode based on stack position information of each of the semiconductor memory devices 811, 812, 813, and 814. In FIG. 12, a bus drawn in bold lines represents a bus in which signals are transmitted in a differential signaling mode, and a bus drawn in thin lines represents a bus in which a signal is transmitted in a single-ended signaling mode. Indicates.

The first semiconductor memory device (0A) 814 receives a first packet WR / CA from the memory controller 820 in a differential signaling mode through a first port, and receives the first packet (WR / CA) through a second port. WR / CA) and the first read data through the third port. The first port is electrically coupled to the memory controller 820 via the first bus 801.

The second semiconductor memory device (1A) 813 is coupled to the first semiconductor memory device (0A) 814 and is in a single ended signal transfer mode from the first semiconductor memory device (0A) 814 through a fourth port. Receives the first packet (WR / CA) through the first port and receives the first read data in the single-ended signaling mode through the fifth port, generates the second read data through the sixth port, and transmits the second read data in the differential signaling mode. The second read data is transmitted to the memory controller 820. The second port and the fourth port are electrically coupled to each other via the second bus 802, and the third port and the fifth port are electrically coupled to each other via the third bus 803. The sixth port is electrically coupled to the memory controller 820 via the fifth bus 805.

The third semiconductor memory device (0B) 812 is coupled to the memory controller 820 and receives the first packet WR / CA from the memory controller 820 in a differential signaling mode through a seventh port. The third read data is output through the eight port. The seventh port is electrically coupled to the memory controller 820 via the fourth bus 804.

The fourth semiconductor memory device (1B) 811 is coupled to the first semiconductor memory device (0A) 814 and the third semiconductor memory device (0B) 812, and is connected to the first semiconductor memory through the ninth port. Receive a first packet (WR / CA) from device (0A) 814 in single-ended signaling mode and receive the third read data in single-ended signaling mode through a tenth port and through an eleventh port Outputs fourth read data and transmits the fourth read data to the memory controller 820 in a differential signaling mode. The ninth port and the second port are electrically coupled to each other via the sixth bus 806, and the tenth port and the eighth port are electrically coupled to each other via the seventh bus 807. The eleventh port is electrically coupled to the memory controller 820 through the eighth bus 808.

In FIG. 12, the first packet WR / CA is data in which write data, commands, and addresses are merged.

13 is a block diagram illustrating a memory system according to a tenth embodiment of the present invention.

Referring to FIG. 13, the memory system 900 includes a memory module 910 and a memory controller 920.

The memory module 910 includes a first semiconductor memory device (0A) 914, a second semiconductor memory device (1A) 913, a third semiconductor memory device (0B) 912, and a fourth semiconductor memory device 1B. (911). The memory controller 920 sets a signaling mode based on stack position information of each of the semiconductor memory devices 911, 912, 913, and 914. In FIG. 13, a bus drawn in bold lines represents a bus for signaling in a differential signaling mode, and a bus drawn in thin lines represents a bus for signaling in a single-ended signaling mode. Indicates.

The first semiconductor memory device (0A) 914 receives the first packet WR / CA from the memory controller 920 in a differential signaling mode through a first port, and receives the first packet (WR / CA) through a second port. WR / CA) and receives first read data in a single-ended signaling mode through a third port, outputs second read data through a fourth port, and stores the second read data in a differential signaling mode. To 920. The first port is electrically coupled to the memory controller 920 via the first bus 901 and the second port is electrically coupled to the memory controller 920 via the second bus 908.

The second semiconductor memory device (1A) 913 is coupled to the first semiconductor memory device (0A) 914 and is a single-ended signal transfer mode from the first semiconductor memory device (0A) 914 through a fifth port. The first packet WR / CA is received and the first read data is output through the sixth port. The third and fifth ports are electrically coupled to each other via a third bus 902 and the fourth and sixth ports are electrically coupled to each other via a fourth bus 903.

The third semiconductor memory device (0B) 912 is coupled to the memory controller 920 and receives the first packet WR / CA from the memory controller 920 in the single-ended signaling mode through the seventh port. Receives third read data in a single-ended signaling mode through an eighth port, outputs fourth read data through a ninth port, and transmits the fourth read data to the memory controller 920 in a differential signaling mode. . The seventh port is electrically coupled to the memory controller 920 via the fifth bus 904, and the ninth port is electrically coupled to the memory controller 920 via the seventh bus 905.

The fourth semiconductor memory device (1B) 911 is coupled to the first semiconductor memory device (0A) 914 and is a single-ended signal transfer mode from the first semiconductor memory device (0A) 914 through a tenth port. The first packet WR / CA is received and the third read data is output through the eleventh port. The ninth port and the third port are electrically coupled to each other via the sixth bus 906, and the eleventh port and the eighth port are electrically coupled to each other via the eighth bus 907.

In FIG. 13, the first packet WR / CA is data in which write data, commands, and addresses are merged.

In a memory system having a stack structure as shown in FIGS. 2 to 13, semiconductor memory devices have a differential signaling mode and a single-ended signaling mode at input and output ports, so that differential signal is obtained using stack position information. The transmission mode and single-ended signal transmission mode can be selectively set.

As described above, the memory system according to the present invention may selectively set the differential signaling mode and the single-ended signaling mode using stack position information. In addition, the memory system according to the present invention can reduce power consumption.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (37)

A memory module including at least one semiconductor memory device; And And a memory controller configured to set a signal transmission mode by using identifiers corresponding to the semiconductor memory devices. The method of claim 1, And a signal transmission between the memory controller and each of the semiconductor memory devices in a differential signal transmission mode and a signal transmission between the semiconductor memory devices in a single-ended transmission method. The memory controller of claim 2, wherein the memory controller And setting the signal transmission mode based on stack position information of each of the semiconductor memory devices. The memory module of claim 2, wherein the memory module comprises: A first semiconductor memory receiving a first packet from the memory controller through the first port in the differential signaling mode, outputting the first packet through a second port, and outputting first read data through a third port Device; Is coupled to the first semiconductor memory device, receives the first packet in the single ended signaling mode through a fourth port and receives the first read data in the single ended signaling mode through a fifth port; A second semiconductor memory device generating second read data through a sixth port and transmitting the second read data to the memory controller in the differential signaling mode; Is coupled to the first semiconductor memory device, receives the first packet in the single-ended signaling mode through a seventh port, outputs the first packet through an eighth port, and reads a third through a ninth port A third semiconductor memory device for outputting data; And Is coupled to the third semiconductor memory device, receives the first packet in the single ended signaling mode through a tenth port and receives the third read data in the single ended signaling mode through an eleventh port; And a fourth semiconductor memory device generating fourth read data through a twelfth port and transmitting the fourth read data to the memory controller in the differential signaling mode. The method of claim 4, wherein And the first packet is data in which write data, commands, and addresses are merged. The method of claim 4, wherein And the first semiconductor memory device and the third semiconductor memory device have the same rank, and the second semiconductor memory device and the fourth semiconductor memory device have the same rank. The memory module of claim 2, wherein the memory module comprises: Receive a first packet from the memory controller in the differential signaling mode through a first port, output the first packet through a second port, generate first read data through a third port, and transmit the differential signaling A first semiconductor memory device transferring the first read data to the memory controller in a mode; And Is coupled to the first semiconductor memory device, receives the first packet through the fourth port in the single-ended signaling mode, generates second read data through the fifth port, and generates the second packet in the differential signaling mode. And a second semiconductor memory device for transmitting second read data to the memory controller. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein And the first packet is data in which write data, commands, and addresses are merged. Claim 9 was abandoned upon payment of a set-up fee. And the first semiconductor memory device and the second semiconductor memory device have the same rank. The memory module of claim 2, wherein the memory module comprises: Receive a first packet from the memory controller through the first port in the differential signaling mode, generate first read data through the second port, and send the first read data to the memory controller in the differential signaling mode. A first semiconductor memory device for transmitting; And Is coupled to the memory controller, receives the first packet from the memory controller through a third port in the differential signaling mode, generates second read data through a fourth port, and generates the first packet in the differential signaling mode; And a second semiconductor memory device for transmitting read data to the memory controller. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, And the first packet is data in which write data, commands, and addresses are merged. Claim 12 was abandoned upon payment of a registration fee. The method of claim 10, Claim 13 was abandoned upon payment of a registration fee. The memory module of claim 2, wherein the memory module comprises: A first semiconductor memory receiving a first packet from the memory controller through the first port in the differential signaling mode, outputting the first packet through a second port, and outputting first read data through a third port Device; A first packet coupled to the first semiconductor memory device, the first packet being received from the first semiconductor memory device through a fourth port in the single-ended signaling mode, and the second packet to the single-ended signaling mode through a fifth port; A second semiconductor memory device configured to receive first read data, generate second read data through a sixth port, and transmit the second read data to the memory controller in the differential signaling mode; Is coupled to the memory controller, receives the first packet from the memory controller through the seventh port in the differential signaling mode, outputs the first packet through an eighth port, and reads a third through the ninth port A third semiconductor memory device for outputting data; And Is coupled to the third semiconductor memory device, receives the first packet from the third semiconductor memory device through the tenth port in the single ended signaling mode, and receives the first packet in the single ended signaling mode through an eleventh port; And a fourth semiconductor memory device configured to receive third read data, generate fourth read data through a twelfth port, and transmit the fourth read data to the memory controller in the differential signal transmission mode. Memory system. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, And the first packet is data in which write data, commands, and addresses are merged. Claim 15 was abandoned upon payment of a registration fee. The method of claim 13, And the first semiconductor memory device and the third semiconductor memory device have the same rank, and the second semiconductor memory device and the fourth semiconductor memory device have the same rank. Claim 16 was abandoned upon payment of a setup registration fee. The memory module of claim 2, wherein the memory module comprises: A first semiconductor memory receiving a first packet from the memory controller through the first port in the differential signaling mode, outputting the first packet through a second port, and outputting first read data through a third port Device; Coupled to the first semiconductor memory device, receiving the first packet from the first semiconductor memory device through the fourth port in the single-ended signaling mode and entering the single-ended signaling mode through a fifth port; A second semiconductor memory device configured to receive first read data and output second read data through a sixth port; The first packet is coupled to the first semiconductor memory device and the second semiconductor memory device, and receives the first packet from the first semiconductor memory device in the single-ended signaling mode through a seventh port and through the eighth port; A third semiconductor memory device receiving the second read data in a single ended signal transmission mode and outputting third read data through a ninth port; The first packet is coupled to the first semiconductor memory device and the third semiconductor memory device, and receives the first packet from the first semiconductor memory device in the single-ended signaling mode through a tenth port and through the eleventh port; A fourth semiconductor memory device configured to receive the third read data in a single-ended signaling mode, generate fourth read data through a twelfth port, and transmit the fourth read data to the memory controller in the differential signaling mode; ; A fifth semiconductor receiving the first packet from the memory controller through the thirteenth port in the differential signaling mode, outputting the first packet through a fourteenth port, and outputting fifth read data through a fifteenth port; Memory devices; Is coupled to the fifth semiconductor memory device, receives the first packet from the fifth semiconductor memory device through the sixteenth port in the single-ended signaling mode and in the single-ended signaling mode through the seventeenth port; A sixth semiconductor memory device which receives the fifth read data and outputs sixth read data through the eighteenth port; A first packet coupled to the fifth semiconductor memory device and the sixth semiconductor memory device, the first packet being received from the fifth semiconductor memory device in the single-ended signaling mode through a nineteenth port, and through the twenty-port port; A seventh semiconductor memory device which receives the sixth read data in a single ended signal transmission mode and outputs seventh read data through a twenty-first port; And The first packet is coupled to the fifth semiconductor memory device and the seventh semiconductor memory device, and receives the first packet from the fifth semiconductor memory device through the twenty-second port in the single-ended signaling mode and through the twenty-third port; An eighth semiconductor memory device configured to receive the seventh read data in a single-ended signaling mode, generate eighth read data through a twenty-fourth port, and transmit the eighth read data to the memory controller in the differential signaling mode; Memory system comprising a. Claim 17 was abandoned upon payment of a registration fee. The method of claim 16, And the first packet is data in which write data, commands, and addresses are merged. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 16, The first semiconductor memory device and the fifth semiconductor memory device have the same rank, and the second semiconductor memory device and the sixth semiconductor memory device have the same rank, and the third semiconductor memory device and the third semiconductor device have the same rank. 7 The semiconductor memory device has the same rank, and the fourth semiconductor memory device and the eighth semiconductor memory device having the same rank. Claim 19 was abandoned upon payment of a registration fee. The memory module of claim 2, wherein the memory module comprises: Receive a first packet from the memory controller in the differential signaling mode through a first port, output first read data through a second port, output second read data through a third port, and transmit the differential signal And a semiconductor memory device configured to transmit the first read data and the second read data to the memory controller in a mode. Claim 20 was abandoned upon payment of a registration fee. The method of claim 19, And the first packet is data in which write data, commands, and addresses are merged. Claim 21 was abandoned upon payment of a registration fee. The memory module of claim 2, wherein the memory module comprises: Receive a first packet from the memory controller through the first port in the differential signaling mode, output the first packet through a second port, and read first data in the single-ended signaling mode through a third port. A first semiconductor memory device configured to receive a signal, output second read data through a fourth port, and transmit the second read data to the memory controller in the differential signaling mode; A first packet coupled to the first semiconductor memory device, the first packet being received from the first semiconductor memory device in the single-ended signaling mode through a fifth port, and configured to receive the first packet in the single-ended signaling mode through a sixth port; A second semiconductor memory device which receives three read data and outputs the first read data through a seventh port; The first packet is coupled to the first semiconductor memory device and the second semiconductor memory device, and receives the first packet from the first semiconductor memory device in the single-ended signaling mode through an eighth port and through the ninth port; A third semiconductor memory device receiving fourth read data in a single-ended signal transmission mode and outputting the third read data through a tenth port; The first packet is coupled to the first semiconductor memory device and the third semiconductor memory device, and receives the first packet from the first semiconductor memory device in the single-ended signaling mode through an eleventh port and through the twelfth port; A fourth semiconductor memory device for outputting fourth read data; Receive the first packet from the memory controller through the thirteenth port in the differential signaling mode, output the first packet through the fourteenth port, and read the fifth packet into the single ended signaling mode through the fifteenth port. A fifth semiconductor memory device configured to receive data, output sixth read data through a sixteenth port, and transmit the sixth read data to the memory controller in the differential signaling mode; A first packet coupled to the fifth semiconductor memory device and receiving the first packet from the fifth semiconductor memory device through the seventeenth port in the single-ended signaling mode, and through the eighteenth port to the single-ended signaling mode; A sixth semiconductor memory device which receives seven read data and outputs the fifth read data through a nineteenth port; The first packet is coupled to the fifth semiconductor memory device and the sixth semiconductor memory device, and receives the first packet from the fifth semiconductor memory device in the single-ended signaling mode through a twentieth port and through the twenty-first port; A seventh semiconductor memory device which receives the eighth read data in a single-ended signal transmission mode and outputs the seventh read data through a twenty-second port; The first packet is coupled to the fifth semiconductor memory device and the seventh semiconductor memory device, and receives the first packet from the fifth semiconductor memory device through the twenty-third port in the single-ended signaling mode and through the twenty-fourth port; And an eighth semiconductor memory device for outputting eighth read data. Claim 22 was abandoned upon payment of a registration fee. The method of claim 21, And the first packet is data in which write data, commands, and addresses are merged. Claim 23 was abandoned upon payment of a set-up fee. The method of claim 21, The first semiconductor memory device and the fifth semiconductor memory device have the same rank, and the second semiconductor memory device and the sixth semiconductor memory device have the same rank, and the third semiconductor memory device and the third semiconductor device have the same rank. 7 The semiconductor memory device has the same rank, and the fourth semiconductor memory device and the eighth semiconductor memory device having the same rank. Claim 24 was abandoned when the setup registration fee was paid. The memory module of claim 2, wherein the memory module comprises: Receive a first packet from the memory controller through the first port in the differential signaling mode, output the first packet through a second port, and read first data in the single-ended signaling mode through a third port. A first semiconductor memory device configured to receive a signal, output second read data through a fourth port, and transmit the second read data to the memory controller in the differential signaling mode; A first packet coupled to the first semiconductor memory device and receiving the first packet from the first semiconductor memory device in the single-ended signaling mode through a fifth port and outputting the first read data through a sixth port; A second semiconductor memory device; A first packet coupled to the first semiconductor memory device, the first packet being received from the first semiconductor memory device through the seventh port in the single-ended signaling mode, and outputting the first packet through an eighth port; Receiving third read data in the single-ended signaling mode through a ninth port, outputting fourth read data through the tenth port, and transmitting the fourth read data to the memory controller in the differential signaling mode; 3 semiconductor memory device; And Coupled to the third semiconductor memory device, receiving the first packet from the third semiconductor memory device in the single-ended signaling mode through an eleventh port and outputting the third read data through a twelfth port; And a fourth semiconductor memory device. Claim 25 was abandoned upon payment of a registration fee. The method of claim 24, And the first packet is data in which write data, commands, and addresses are merged. Claim 26 was abandoned upon payment of a registration fee. The method of claim 24, And the first semiconductor memory device and the third semiconductor memory device have the same rank, and the second semiconductor memory device and the fourth semiconductor memory device have the same rank. Claim 27 was abandoned upon payment of a registration fee. The memory module of claim 2, wherein the memory module comprises: A first semiconductor memory receiving a first packet from the memory controller through the first port in the differential signaling mode, outputting the first packet through a second port, and outputting first read data through a third port Device; Coupled to the first semiconductor memory device, receiving the first packet from the first semiconductor memory device through the fourth port in the single-ended signaling mode and entering the single-ended signaling mode through a fifth port; A second semiconductor memory device configured to receive first read data, generate second read data through a sixth port, and transmit the second read data to the memory controller in the differential signaling mode; A third semiconductor memory device coupled to the memory controller, the third semiconductor memory device receiving the first packet from the memory controller through the seventh port in the differential signaling mode and outputting third read data through an eighth port; And The first packet is coupled to the first semiconductor memory device and the third semiconductor memory device and receives the first packet from the first semiconductor memory device in the single-ended signaling mode through a ninth port and through the tenth port; A fourth semiconductor memory device which receives the third read data in a single-ended signaling mode, outputs fourth read data through an eleventh port, and transmits the fourth read data to the memory controller in the differential signaling mode; Memory system comprising a. Claim 28 was abandoned upon payment of a registration fee. And the first packet is data in which write data, commands, and addresses are merged. Claim 29 was abandoned upon payment of a set-up fee. The method of claim 27, And the first semiconductor memory device and the third semiconductor memory device have the same rank, and the second semiconductor memory device and the fourth semiconductor memory device have the same rank. Claim 30 was abandoned upon payment of a registration fee. The memory module of claim 2, wherein the memory module comprises: Receive a first packet from the memory controller through the first port in the differential signaling mode, output the first packet through a second port, and read first data in the single-ended signaling mode through a third port. A first semiconductor memory device configured to receive a signal, output second read data through a fourth port, and transmit the second read data to the memory controller in the differential signaling mode; A first packet coupled to the first semiconductor memory device and receiving the first packet from the first semiconductor memory device in the single-ended signaling mode through a fifth port and outputting the first read data through a sixth port; A second semiconductor memory device; Is coupled to the memory controller, receives the first packet from the memory controller through the seventh port in the differential signaling mode, and receives third read data in the single ended signaling mode through an eighth port, A third semiconductor memory device outputting fourth read data through a ninth port and transmitting the fourth read data to the memory controller in the differential signaling mode; And A first packet coupled to the first semiconductor memory device and receiving the first packet from the first semiconductor memory device in the single-ended signaling mode through a tenth port and outputting the third read data through an eleventh port; And a fourth semiconductor memory device. Claim 31 was abandoned upon payment of a registration fee. The method of claim 30, And the first packet is data in which write data, commands, and addresses are merged. Claim 32 was abandoned upon payment of a registration fee. The method of claim 30, And the first semiconductor memory device and the third semiconductor memory device have the same rank, and the second semiconductor memory device and the fourth semiconductor memory device have the same rank. delete delete delete Setting a signal transmission mode using identifiers corresponding to the semiconductor memory devices; And Transmitting a signal in response to the signal transmission mode. 37. The method of claim 36, wherein setting the transmission mode Assigning the identifiers to the semiconductor memory devices; Setting a signal transmission mode of channels by using identifiers corresponding to the semiconductor memory devices; Performing reverse swizzling on the channels; And And providing the set signal transmission mode value to the semiconductor memory devices.

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