KR100861311B1 - Method of manufacturing isolation layer for semiconductor device - Google Patents

Abstract

A method for forming an isolation layer of a semiconductor device is provided to reduce parasitic capacitance of a sidewall oxide layer by implanting SiCOH into a dielectric film. A hard mask pattern(108) is formed on a semiconductor substrate(102). A trench(T) is formed in the substrate by using the hard mask pattern. A dielectric film(110) is formed in the trench. The dielectric film is firstly baked. A rirst annealing process is performed to the baked dielectric film. A hydrocarbon based compound, such as SiCOH is implanted into the dielectric film. Then, the dielectric film is secondly annealed. The dielectric film is compound of a PZT(Poly Silazane) film.

Description

METHODS OF MANUFACTURING ISOLATION LAYER FOR SEMICONDUCTOR DEVICE}

The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device capable of improving the characteristics of the device isolation film.

With the progress of semiconductor technology, the speed and the high integration of semiconductor devices are progressing rapidly, and with this, the demand for the refinement | miniaturization of a pattern and the high precision of a pattern size is increasing. This requirement applies not only to patterns formed in device regions, but also to device isolation films that occupy a relatively large area.

When the device isolation layer defining the active region of the substrate is formed, a trench for forming the device isolation layer is embedded to form a deposition-etch-deposition (DED) or deposition-etch-deposition using a high density plasma (HDP) oxide film. deposition-etch-deposition) methods have been used. However, as the degree of integration of semiconductor devices increases, the design rules decrease, and the size of the active area decreases. Also, as the depth of the trench increases for the electrical characteristics of the device, the aspect ratio increases, and the trench gap-fill ( gap-fill) problem.

Therefore, in order to solve the gap-fill problem of the above-mentioned trenches, the trench is buried using a method of a high aspect ratio process (HARP) or a pulsed deposition layer (PDL), and the HARP or PDL method as described above. Because of the limitation of the silver conformal deposition method, there is a disadvantage that the buried shape of the trench should have a certain slope.

At this time, the lower end of the trench is deposited with a spin-on dielectric (SOD) film having excellent embedding characteristics, and then a high density plasma (HDP) film is deposited on the SOD film to completely fill the trench. A method of forming a device isolation film made of a laminated film of a film has been proposed. When the device isolation film is formed as a stacked film structure of an SOD film and an HDP film, an SOD film having excellent embedding characteristics in a lower portion of a trench having a high aspect ratio is excellent. The film can be buried without generating voids, and the upper end portion of the trench exposed during the subsequent process can be formed into a HDP film having a relatively low etching rate, thereby preventing deterioration of reliability of the device isolation film caused during the subsequent cleaning process. There is an advantage.

However, in the future, in semiconductor devices having 50 nm or less or a trench aspect ratio of 3 or more, a silicon oxide film having a dielectric constant value (K) of about 3.2 cannot be applied because the stacked structure of the SOD film and the HDP film as described above or the HDP single film cannot be applied. A low dielectric film having a dielectric constant (K) of 2.9 or lower, which is lower than the dielectric constant, is embedded in a spin coating method and thermally treated to be used as an insulating film for device isolation films.

However, when heat treatment is performed by embedding a trench using an HSQ (Hydrogen Silsequioxane) film, which is one of the above-described low dielectric films, pores are formed in the trench, as shown in FIG. This causes rapid etching in the exposed trench portions during the wet cleaning for subsequent processing.

On the other hand, in order to prevent the rapid etching of the exposed trench portion due to the pores as described above, a multi-step heat treatment is performed by wet (H ₂ O / O ₂ ) and dry, in this case, the thickness of the low dielectric film and the lower trench Since the formation thickness of the silicon oxide film having a hard film quality varies depending on the depth, when wet etching is performed in this state, the removal rate is uneven.

In addition, in order to improve the non-uniform etching rate as described above, even if the number of multi-step heat treatments is increased, only the upper layer of a certain thickness continues to be dense or oxidized, so that oxidation occurs to the tunneling oxide or the pad nitride film, resulting in silicon. It will lower the protective function of the surface.

As a result, the coupling phenomenon reduces the characteristics of the device isolation film, thereby degrading subsequent gate characteristics.

The present invention provides a method of forming a device isolation layer of a semiconductor device capable of minimizing a coupling phenomenon.

In addition, the present invention provides a device isolation film forming method of a semiconductor device capable of improving the device isolation film and subsequent gate characteristics by minimizing the coupling phenomenon as described above.

A method of forming a device isolation film of a semiconductor device according to the present invention includes forming a hard mask pattern on a semiconductor substrate; Forming a trench in a semiconductor substrate using the hard mask pattern as a mask pattern; Applying a low dielectric film in the trench; First baking the low dielectric film; Primary annealing the first baked low dielectric film; Injecting a hydrocarbon-based compound into the first annealed low dielectric film; And second annealing the low dielectric film in which the hydrocarbon compound is injected.

And sequentially forming a sidewall oxide film, a linear nitride film, and a linear oxide film on the semiconductor substrate including the trench between forming a trench in the semiconductor substrate and applying a low dielectric film in the trench.

The low dielectric film is formed of a polysilazane (PSZ) film.

The first baking step is performed for 1 to 29 minutes in a wet atmosphere in which the ratio of H ₂ O and O ₂ is 5 to 10:95 to 100 at a temperature of 150 to 350 ° C.

The first annealing is performed at a temperature of 700 to 900 ° C. for 1 to 59 minutes.

And forming a mask pattern exposing only the trench on the semiconductor substrate between the first annealing and the step of injecting the compound.

And performing chemical mechanical polishing (CMP) of the low dielectric layer until the hard mask pattern is exposed between the first annealing and the step of injecting the compound.

The hydrocarbon compound is formed of C _n H _{2n +2} (n ≧ 1, where n is an integer).

The secondary annealing step is carried out dry at a temperature of 700 ~ 900 ℃ and oxygen atmosphere.

The secondary annealing may be performed by a rapid thermal annealing process.

The rapid annealing process is carried out in an atmosphere of oxygen and hydrogen at a temperature of 900 ~ 1000 ℃.

After the secondary annealing, performing the third annealing on the low dielectric film in which the second annealing is performed.

The tertiary annealing is carried out dry at a temperature of 700 to 900 ° C and an atmosphere of oxygen.

After the second annealing, the step of applying the low dielectric film to the second annealing is repeated at least two to five times.

After the secondary annealing, removing the hard mask pattern further comprises.

The present invention forms a device isolation film of a semiconductor device by filling a trench with a low dielectric film made of a SiCOH material, thereby minimizing a coupling phenomenon generated when only a conventional silicon oxide film is applied by the SiCOH material. The parasitic capacitance of the sidewall oxide film can be reduced.

In addition, the present invention may further reduce the parasitic capacitance of the sidewall oxide film by the pores formed in the low dielectric film when forming the SiCOH material.

Therefore, the present invention can reduce the parasitic capacitance of the sidewall oxide film in the trench as described above, thereby improving the device isolation film and subsequent gate characteristics.

According to the present invention, a trench is formed in a semiconductor substrate, and the trench is formed to be filled with a low dielectric layer, and then, at least two heat treatments and a hydrocarbon-based compound injection process are sequentially performed on the low dielectric layer. Form a substance.

In this case, unlike the device isolation film of the conventional semiconductor device formed by filling the trench with an insulating film, such as a conventional silicon oxide film, by forming a device isolation film of the semiconductor device by filling the trench with a low dielectric film, such as SiCOH material as described above, By the SiCOH material, the coupling phenomenon occurring when only the conventional silicon oxide layer is applied may be minimized, thereby reducing the parasitic capacitance of the sidewall oxide layer in the trench.

In addition, when the SiCOH material is formed, the parasitic capacitance of the sidewall oxide layer may be further reduced by pores formed in the low dielectric layer.

Therefore, since the parasitic capacitance of the sidewall oxide film in the trench can be reduced, the device isolation film and subsequent gate characteristics can be improved.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2G are cross-sectional views illustrating processes of forming a device isolation film of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a hard mask 108 including a pad oxide film 106 and a pad nitride film 106 is formed on a semiconductor substrate 102, and the semiconductor substrate is formed by using the hard mask 108 as an etching mask. A trench T is formed in 102.

Then, the sidewall oxide film 103 is formed on the sidewalls and bottom of the trench T by a dry oxidation method, and the linear nitride film 106 is formed on the pad nitride film 106 including the trench T surface on which the sidewall oxide film 103 is formed. 105 and a linear oxide film 107 are formed in this order.

Referring to FIG. 2B, a low dielectric film made of a material such as a polysilazane (PSZ) film is embedded to fill the trench T on a semiconductor substrate 102 including a trench T surface on which the linear oxide film 107 is formed. 110) is applied. Thereafter, the low dielectric film 110, the linear oxide film 107, and the linear nitride film 105 are planarized by a chemical mechanical polishing (CMP) process.

At this time, when applying the low dielectric film 110, it is preferable to consider the maximum penetration depth of the trench (T) that can replace the nitrogen and hydrogen in the subsequent coating to suit the thickness.

Referring to FIG. 2C, a baking 112 process is performed on the low dielectric layer 110 to remove impurities such as solvent in the low dielectric layer 110.

The baking 112 process is performed at a temperature of about 150 to 350 ° C. for about ₁ to 29 minutes in a wet atmosphere having a ratio of H ₂ O and O ₂ 5:95 or 10:90.

Referring to FIG. 2D, the first annealing process 116 is performed to replace nitrogen and hydrogen in the semiconductor substrate 102 with the silicon oxide layer with respect to the low dielectric layer 110 from which impurities are removed by performing the baking process.

The first annealing process 116 is preferably carried out for about 1 to 59 minutes at a temperature of about 700 ~ 900 ℃.

The substrate output is then planarized by a CMP process.

Referring to FIG. 2E, a hydrocarbon-based compound composed of any one of CH ₄ , C ₂ H ₆ and C ₃ H ₈ in the low dielectric film 110 in which the first annealing process is performed to form a silicon oxide film ( 118).

In this case, when the hydrocarbon-based compound 118 is injected into the low dielectric layer 110, ion implantation energy for injecting the hydrocarbon-based compound 118 may be increased or decreased step by step to a depth in the trench T. To be uniformly injected.

On the other hand, when the hydrocarbon-based compound 118 is injected into the low dielectric layer 110, the trench may not be easily controlled as a mask for the compound 118 only by the thickness of the hard mask 108. A photosensitive film pattern may be formed on the pad nitride film 106 except for (T) to be used as a mask for injecting the hydrocarbon-based compound 118.

Referring to FIG. 2F, the SiCOH material formed of a covalent bond of silicon, oxygen, carbon, and hydrogen is formed in the low dielectric layer 110 with respect to the low dielectric layer 110 into which the hydrocarbon compound 118 is injected. Annealing process 122 is performed.

The secondary annealing 122 process is performed dry in a temperature and oxygen atmosphere of about 700 ~ 900 ℃, or rapid thermal annealing (Rapid Thermal Annealing) process in a temperature of about 900 ~ 1000 ℃ and oxygen and hydrogen To do it.

In this case, when the secondary annealing process 122 is performed, the low dielectric film 110 may be damaged by the damage when the hydrocarbon compound 118 is injected into the low dielectric film 110 of the semiconductor substrate 102. Pores 120 are formed in the pores.

Referring to FIG. 2G, the low-k dielectric layer 110 and the hard mask on which the SiCOH film is formed are removed by a CMP process until the semiconductor substrate 102 is exposed, and the device isolation layer 100 of the semiconductor device according to the embodiment of the present invention is removed. To complete.

On the other hand, when the sum of the depths of the low dielectric film and the trench embedded in the trench is larger than the maximum penetration depth of the trench capable of substituting nitrogen and hydrogen, the low dielectric film is formed only at a specific depth within the trench and the size of the pattern And the low dielectric film coating process in the above-described embodiment of the present invention in consideration of the maximum penetration depth of the trench capable of substituting nitrogen and hydrogen so as to simultaneously planarize at different densities, and the first baking of the low dielectric film. At least 2 to 5, a step of first annealing the first baked low dielectric film, a step of injecting a hydrocarbon compound into the first annealed low dielectric film, and a second annealing of the ion implanted low dielectric film. You can repeat the steps.

Thereafter, although not shown, after the low dielectric film is formed in the trench as described above, when the pad nitride film is removed by the CMP process, the low dielectric film positioned on the trench surface and the upper part contains a large amount of moisture by wet cleaning and etching, and thus subsequent gate formation. During the gate oxide film cleaning, the etching rate of the trench may be greatly increased to cause the loss of the device isolation film. Therefore, after the pad nitride film is removed, it is dried at a temperature of about 700 to 900 ° C. and an oxygen atmosphere to prevent this. The annealing process can be performed.

As described above, the present invention provides a device isolation film of a semiconductor device by filling a trench with a low dielectric film and forming a SiCOH material in the low dielectric film to form a device isolation film of a semiconductor device. The phenomenon can be minimized, thereby reducing the parasitic capacitance of the sidewall oxide film in the trench.

In addition, when the SiCOH material is formed, the parasitic capacitance of the sidewall oxide layer may be further reduced by the pores formed by the damage.

Therefore, since the parasitic capacitance of the sidewall oxide film in the trench can be reduced, the device isolation film and subsequent gate characteristics can be improved.

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1 is a photograph showing a conventional problem.

2A to 2G are cross-sectional views of processes for describing a method of forming an isolation layer in a semiconductor device in accordance with an embodiment of the present invention.

Claims (15)

Forming a hard mask pattern on the semiconductor substrate; Forming a trench in a semiconductor substrate using the hard mask pattern as a mask pattern; Applying a low dielectric film in the trench; First baking the low dielectric film; Primary annealing the first baked low dielectric film; Injecting a hydrocarbon-based compound into the first annealed low dielectric film; And Second annealing the low dielectric film in which the hydrocarbon compound is injected; Device isolation film forming method of a semiconductor device comprising a. The method of claim 1, Between forming a trench in the semiconductor substrate and applying a low dielectric film in the trench, Sequentially forming a sidewall oxide film, a linear nitride film, and a linear oxide film on the semiconductor substrate including the trench; Device isolation film forming method of a semiconductor device characterized in that it further comprises. The method of claim 1, The low dielectric film is a method of forming a device isolation film of a semiconductor device, characterized in that formed by a PSZ (Poly Silazane) film. The method of claim 1, The first baking step, A method of forming a device isolation film for a semiconductor device, characterized in that performed for 1 to 29 minutes in a wet atmosphere in which the ratio of H ₂ O and O ₂ is 5 to 10:95 to 100 at a temperature of 150 to 350 ° C. The method of claim 1, The first annealing step, A device isolation film forming method of a semiconductor device, characterized in that performed for 1 to 59 minutes at a temperature of 700 ~ 900 ℃. The method of claim 1, Between the first annealing step and the step of injecting the compound, Forming a mask pattern exposing only the trench on the semiconductor substrate; Device isolation film forming method of a semiconductor device characterized in that it further comprises. The method of claim 1, Between the first annealing step and the step of injecting the compound, Chemical mechanical polishing (CMP) the low-k dielectric until the hard mask pattern is exposed; Device isolation film forming method of a semiconductor device characterized in that it further comprises. The method of claim 1, The hydrocarbon compound is, C _n H _{2n +2} (n ≧ 1, where n is an integer). The method of claim 1, The second annealing step, A method of forming an isolation film in a semiconductor device, characterized in that it is carried out dry at a temperature of 700 to 900 ° C. and an oxygen atmosphere. The method of claim 1, The second annealing step, A method of forming a device isolation film for a semiconductor device, characterized in that it is carried out by a rapid thermal annealing process. The method of claim 10, The rapid annealing process is a device isolation film forming method of a semiconductor device, characterized in that carried out in an atmosphere of oxygen and hydrogen at a temperature of 900 ~ 1000 ℃. The method of claim 1, After the secondary annealing, Performing tertiary annealing on the low dielectric film on which the secondary annealing is performed; Device isolation film forming method of a semiconductor device characterized in that it further comprises. The method of claim 12, The third annealing, A method of forming a device isolation film for a semiconductor device, characterized in that it is carried out dry in a temperature of 700 to 900 ℃ and oxygen. The method of claim 1, After the secondary annealing, And applying the low dielectric film to the second annealing step at least two to five times. The method of claim 1, After the secondary annealing, Removing the hard mask pattern; Device isolation film forming method of a semiconductor device characterized in that it further comprises.

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