KR100861310B1 - Electrostatic discharge device - Google Patents

Abstract

An electrostatic discharge device is provided to reduce the layout size thereof by implementing an electrostatic discharge element with an electrostatic discharge function and a support function for driving another electrostatic discharge element. An electrostatic discharge device includes first and second electrostatic discharge units(20,30). The first electrostatic discharge unit discharges static electricity to a first discharge line when the static electricity is generated in a pad. The second electrostatic discharge unit receives bias and driving voltages from the first electrostatic discharge unit and discharges static electricity generated from the pad to a second discharge line.

Description

Electrostatic Discharge Device

1 is a device diagram showing a conventional electrostatic discharge device.

Figure 2 is a block diagram showing an embodiment of an electrostatic discharge device of the present invention.

3 is a circuit diagram illustrating an example of a detailed configuration of FIG. 2.

Figure 4 is a block diagram showing another embodiment of the electrostatic discharge device of the present invention.

FIG. 5 is a circuit diagram illustrating a first example of a detailed configuration of FIG. 4. FIG.

6 is a circuit diagram illustrating a second example of the detailed configuration of FIG. 4.

7 is a circuit diagram illustrating a third example of the detailed configuration of FIG. 4.

8 is a circuit diagram illustrating a fourth example of the detailed configuration of FIG. 4.

<Description of Main Parts of Drawing>

10: input and output pad 20: first electrostatic discharge unit

22: bias applying unit 24: driving voltage applying unit

26: electrostatic discharge path 30: second electrostatic discharge portion

40: third electrostatic discharge portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to electrostatic discharge (ESD) devices that protect semiconductor devices from static electricity.

In general, when a semiconductor integrated circuit is in contact with a charged human body or a machine, the static electricity charged in the human body or the machine is discharged into the semiconductor through an input / output pad through an external pin of the integrated circuit, and thus has a large energy transient current wave. Can seriously damage the semiconductor internal circuit. In addition, the static electricity that has been charged inside the semiconductor circuit flows through the machine due to the contact of the machine to damage the external circuit.

Thus, most semiconductor integrated circuits have circuits that discharge static electricity between the input / output pads and the semiconductor internal circuitry to protect the main circuit from such damage.

The electrostatic discharge circuit may be composed of various elements. In particular, when an NMOS transistor is used as an electrostatic discharge element, a grounded-gate NMOS having a structure in which a gate and a source are connected is mainly used.

At this time, the input / output pad is connected to the drain of the NMOS transistor, and when the voltage level of the drain rises due to static electricity, an avalanche breakdown occurs between the drain of the NMOS transistor and the substrate so that an electrostatic current flows to the substrate. do.

When the level of the substrate voltage rises above the source voltage level of the NMOS transistor by the electrostatic current flowing to the substrate, the electrostatic current is discharged from the drain to the source of the NMOS transistor by the BJT characteristic of the NMOS transistor.

However, since the electrostatic discharge due to the BJT characteristic of the NMOS transistor is not excellent in the electrostatic discharge effect due to the limitation of the driving capability of the NMOS transistor, a method of improving the driving capability of the NMOS transistor is disclosed by applying a bias to the gate of the NMOS transistor. It became.

As a method of improving the driving capability of a conventional NMOS transistor, as shown in FIG. 1, the NMOS transistor N1 is formed by using a voltage drop caused by a resistor R1 and a diode chain 12 composed of a plurality of diodes connected in series. An electrostatic discharge circuit for driving) may be disclosed.

That is, when static electricity is generated in the pad 10, the static electricity is discharged to the ground voltage VSS from the pad 10 through the NMOS transistor N1 by the BJT characteristic of the NMOS transistor N1, and further, the diode chain ( The NMOS transistor N1 is turned on by the 12 and the resistor R1, thereby improving the driving capability of the NMOS transistor N1.

In addition, in the conventional electrostatic discharge circuit, a diode D1 is further connected between the gate and the ground voltage of the NMOS transistor N1 to further form a path for transferring static electricity generated from the pad 10 to the ground voltage VSS. Can be.

However, the conventional electrostatic discharge circuit which forms an electrostatic discharge path between the pad 10 and the ground voltage further includes a diode chain 12, a resistor R1, and a diode D1 to improve electrostatic discharge performance. However, there is a problem in that the layout area increases.

In addition, a general electrostatic discharge circuit may include an electrostatic discharge element (not shown) connected between the pad 10 and a power supply voltage (not shown), a power supply voltage VDD, and a ground voltage (ie, to provide various electrostatic discharge paths). Electrostatic discharge elements (not shown) connected between the VSSs.

If the electrostatic discharge elements are additionally connected to the conventional electrostatic discharge circuit, there is a problem that the layout area is increased by the existing diode chain 12, the resistor R1, and the diode D1 and the two electrostatic discharge elements added. .

An object of the present invention is to provide an electrostatic discharge device having excellent electrostatic discharge performance of electrostatic discharge elements in each path while providing various discharge paths.

It is still another object of the present invention to provide an electrostatic discharge device having various discharge paths and improved electrostatic discharge performance while not occupying a large layout area.

Electrostatic discharge apparatus according to an embodiment of the present invention for achieving the above object, the first electrostatic discharge unit for discharging the static electricity to the first discharge line when the static electricity from the pad; And a second electrostatic discharge unit configured to receive a bias voltage and a driving voltage from the first electrostatic discharge unit to discharge the static electricity generated from the pad to the second discharge line.

Preferably, the first discharge line is a power supply voltage, and the second discharge line is a ground voltage.

The first electrostatic discharge unit may include a bias applying unit applying a bias voltage to the second electrostatic discharge unit in response to the static electricity generated in the pad; A driving voltage applying unit applying the driving voltage to the second electrostatic discharge unit in response to the bias voltage; And a first electrostatic discharge path for discharging static electricity corresponding to the driving voltage to the first discharge line in response to the driving voltage.

The driving voltage applying unit is preferably connected to the output of the bias applying unit.

The bias applying unit preferably includes at least one diode connected between the pad and the driving voltage applying unit.

The driving voltage applying unit may include at least one diode connected between the bias applying unit and the first electrostatic discharge path.

The first electrostatic discharge path preferably includes at least one diode connected between the driving voltage applying unit and the first discharge line.

Preferably, the first electrostatic discharge path includes a plurality of diodes connected in series between the driving voltage applying unit and the first power voltage.

The second electrostatic discharge unit preferably includes a MOS transistor that forms a current path path between the pad and the second discharge line in response to the bias voltage and the driving voltage applied from the first electrostatic discharge unit.

Preferably, the second electrostatic discharge unit further includes a resistor connected between the gate of the MOS transistor and the second discharge line.

Preferably, the bias voltage is applied to the substrate of the MOS transistor, and the driving voltage is applied to the gate of the MOS transistor.

Between the first discharge line and the second discharge line is further connected to the third electrostatic discharge unit for discharging the static electricity transferred to any one of the first and second discharge line to any one of the second and first discharge line. desirable.

The third electrostatic discharge unit preferably includes a MOS transistor for forming a current path path between the first discharge line and the second discharge line in response to the static electricity transferred to any one of the first and second discharge lines. .

In addition, the electrostatic discharge device according to the present invention includes a first electrostatic discharge unit for discharging the static electricity to the first discharge line when the static electricity generated in the pad; A second electrostatic discharge unit configured to receive a bias voltage and a driving voltage from the first electrostatic discharge unit to discharge static electricity generated from the pad to a second discharge line; And a third electrostatic discharge unit configured to receive the bias voltage and the driving voltage from the first electrostatic discharge unit to discharge static electricity transferred to any one of the first and second discharge lines to any one of the second and first discharge lines. It characterized by including.

Preferably, the first discharge line is a power supply voltage line, and the second discharge line is a ground voltage line.

The first electrostatic discharge unit is a bias-in part for applying a bias voltage to the second electrostatic discharge unit and the third electrostatic discharge unit in response to the static electricity generated in the pad; A driving voltage applying unit applying a driving voltage to the second electrostatic discharge unit and a third electrostatic discharge unit in response to the bias voltage; And an electrostatic discharge path for discharging static electricity corresponding to the driving voltage to the first discharge line in response to the driving voltage.

Preferably, the driving voltage applying unit is connected to an output terminal of the bias applying unit.

The bias applying unit preferably includes at least one diode connected between the pad and the driving voltage applying unit.

The bias applying unit may include one or more MOS transistors connected between the pad and the driving voltage applying unit, and a gate of the MOS transistor is connected to the first discharge line. ,

The bias applying unit may include a plurality of MOS transistors connected in series between the pad and the driving voltage applying unit, and gates of the plurality of MOS transistors are commonly connected to the first discharge line.

The driving voltage applying unit preferably includes at least one diode formed between the bias applying unit and the electrostatic discharge path.

The driving voltage applying unit may include at least one MOS transistor connected between the bias applying unit and the electrostatic discharge path, and the gate of the MOS transistor is connected to the first discharge line.

Preferably, the electrostatic discharge path includes at least one diode connected between the first electrostatic discharge unit and the first discharge line.

The electrostatic discharge path may include at least one MOS transistor connected between the first electrostatic discharge unit and the first discharge line, and the gate of the MOS transistor is connected to the first discharge line.

Preferably, the first electrostatic discharge unit further includes a resistor connected between the first discharge line and the electrostatic discharge path.

The second electrostatic discharge unit preferably includes a MOS transistor forming a current path between the pad and the second discharge line in response to the bias voltage and the driving voltage.

Preferably, the bias voltage is applied to the substrate of the MOS transistor, and the driving voltage is applied to the gate of the MOS transistor.

The second electrostatic discharge unit may further include a resistor connected between the gate of the MOS transistor and the second discharge line.

The third electrostatic discharge unit preferably includes a MOS transistor forming a current path between the first discharge line and the second discharge line in response to the bias voltage and the driving voltage.

Preferably, the bias voltage is applied to the substrate of the MOS transistor, and the driving voltage is applied to the gate of the MOS transistor.

The third electrostatic discharge unit may further include a resistor connected between the gate of the MOS transistor and the second discharge line.

In addition, the electrostatic discharge device according to the present invention includes a diode chain connected to the external input and output pad; A first NMOS transistor having a drain connected simultaneously to the input / output pad and an anode of a diode chain; And a second NMOS transistor having a drain connected to a cathode of the diode chain and a voltage power supply at the same time, wherein the diode chain applies a voltage to substrates and gates of the first and second NMOS transistors.

The voltage applied to the gate is preferably lower than the voltage applied to the substrate.

It is preferable that the first resistance element is connected to the anode side of the diode chain.

Preferably, a second resistance element is connected to the gate terminal of the first NMOS transistor.

Preferably, a third resistance element is connected to the gate terminal of the second NMOS transistor.

It is preferable that a PMOS transistor chain is formed in place of the diode chain.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The electrostatic discharge device of the present invention is composed of a plurality of electrostatic discharge unit for discharging the static electricity generated from the pad, wherein the electrostatic discharge unit connected between the pad and a predetermined voltage serves as an electrostatic discharge and at the same time to drive the other electrostatic discharge unit By helping, the electrostatic discharge performance can be improved and the area occupied by the electrostatic discharge circuit can be reduced.

Specifically, the electrostatic discharge circuit of the present invention may be configured as shown in FIG. 2 as an embodiment. Referring to FIG. 2, the electrostatic discharge circuit of the present invention is connected between the first electrostatic discharge unit 20 connected between the pad 10 and the power supply voltage VDD, and between the pad 10 and the ground voltage VSS. And a second electrostatic discharge unit 30, and a third electrostatic discharge unit 40 may be additionally connected between the power supply voltage VDD and the ground voltage VSS.

When the static electricity occurs in the pad 10, the first electrostatic discharge part 20 delivers the static electricity to the second electrostatic discharge part 30 while simultaneously discharging the static electricity to the power supply voltage VDD.

The second electrostatic discharge unit 30 discharges the static electricity generated from the pad 10 to the ground voltage VSS in response to a bias voltage and a driving voltage input from the first electrostatic discharge unit 20.

In addition, the third electrostatic discharge part 40 discharges the static electricity transferred to the power supply voltage VDD or the ground voltage VSS to the ground voltage VSS or the power supply voltage VDD.

The electrostatic discharge parts 20, 30, and 40 of FIG. 2 may be embodied in, for example, a circuit as shown in FIG. 3.

Referring to FIG. 3, the first electrostatic discharge unit 20 includes a plurality of diodes (hereinafter referred to as diode chains) connected in series to discharge to the power supply voltage VDD in response to static electricity generated from the pad 10.

The diode chain applies a bias voltage and a driving voltage to the second electrostatic discharge unit 30 through two nodes (nodes A and B) as shown. The cathode of the diode is connected in the direction of the power supply voltage VDD, and the anode of the diode is connected in the direction of the pad 10.

The diode chain may be divided into a bias applying unit 22, a driving voltage applying unit 24, and an electrostatic discharge path 26 based on the nodes. The electrostatic discharge path 26 corresponds to an electrostatic discharge unit which finally discharges static electricity to a power supply voltage line, but is a component of the first electrostatic discharge unit 20 and there is a risk of confusion when using the name of the electrostatic discharge unit. The electrostatic discharge path 26 will be referred to.

The bias applying unit 22 applies a bias voltage to the substrate of the NMOS transistor of the second electrostatic discharge unit 30 through the node A, and the driving voltage applying unit 24 to the second electrostatic discharge unit 30. The diode is applied with a driving voltage through the node B. That is, the bias voltage is a voltage dropped through the diode of the bias applying unit 22 in the applied static electricity and the driving voltage is the diode of the bias applying unit 22 and the driving voltage applying unit 24 in the applied static electricity. The voltage drop across the diode.

The second electrostatic discharge unit 30 includes an NMOS transistor N2 that forms a current path path between the pad 10 and the ground voltage VSS in response to the driving voltage, and the NMOS transistor N2 is driven faster. The resistor R2 may be further connected between the gate of the NMOS transistor N2 and the ground voltage VSS.

Here, the gate of the NMOS transistor N2 is connected between the driving voltage applying unit 24 and the electrostatic discharge path 26, the drain (or source) of the NMOS transistor N2 is connected to the pad 10, and the NMOS The source (or drain) of the transistor N2 is connected to the ground voltage VSS.

The third electrostatic discharge part 40 is an NMOS transistor that is turned on as static electricity is transferred to the power supply voltage VDD or the ground voltage VSS to form a current path path between the power supply voltage VDD and the ground voltage VSS. (N3).

Here, the gate and source (or drain) of the NMOS transistor N3 are commonly connected to the ground voltage VSS, and the drain (or source) of the NMOS transistor N3 is connected to the power supply voltage VDD.

In the electrostatic discharge circuit of the present invention having the configuration as shown in FIG. 3, the operation of discharging static electricity generated from the pad 10 is as follows.

Discharge to the power supply voltage (VDD) or ground voltage (VSS) through the electrostatic discharge parts 20, 30, 40, discharge the static electricity generated from the power supply voltage (VDD) or ground voltage (VSS) to the pad 10, The static electricity generated at the power supply voltage VDD or the ground voltage VSS is discharged to the ground voltage VSS or the power supply voltage VDD.

Looking at the operation of discharging the positive static electricity generated in the pad 10 to the power supply voltage (VDD) during the static discharge operation of the electrostatic discharge circuit of the present invention, the positive static electricity generated in the pad 10 is the diode chain (22, 24) Through the power supply voltage VDD. The electrostatic voltage dropped through the bias applying unit 22 of the diode chain is applied as a bias voltage to the substrate of the NMOS transistor N2 through the node A, and the electrostatic voltage dropped through the driving voltage applying unit 24. Is transmitted to the second electrostatic discharge unit 30 through the node B. At this time, a voltage drop occurs in the ESD current by the resistor R2. Therefore, the transistor is turned on by being applied to the gate of the NMOS transistor N2 formed between the pad 10 and the ground voltage VSS.

At this time, since the bias is applied to the substrate of the NMOS transistor through the node A, the trigger voltage is lowered. In this embodiment, since node B passes one more diode than node A, the voltage of node A is approximately 0.7 volts higher than that of node B. That is, by applying a higher bias voltage to the substrate, the threshold voltage of the NMOS transistor N2 can be lowered, and as a result, the NMOS transistor can be easily turned on and discharge of static electricity even with low static electricity. As the NMOS transistor N2 is turned on, the static electricity generated from the pad 10 is transferred to the ground voltage VSS, and the NMOS transistor N3 is turned on by the static electricity transferred to the ground voltage VSS, thereby causing the ground voltage ( The static electricity of VSS is discharged to the power supply voltage VDD.

Next, referring to the operation of discharging the positive static electricity generated in the pad 10 to the ground voltage VSS, the positive static electricity generated in the pad 10 may be different from the bias applying unit 22 of the first electrostatic discharge unit 20. After the power supply voltage VDD is passed through the diode chain of the driving voltage applying unit 24, the discharge voltage is discharged to the ground voltage VSS via the third electrostatic discharge unit 40.

In addition, a static voltage is applied to the substrate of the NMOS transistor N2 through the bias applying unit 22 and output as a driving voltage through the driving voltage applying unit 24, and the driving voltage and the electrostatic discharge unit 40 are applied. The voltage drop occurs in the resistor R2 due to the static electricity discharged to the ground voltage VSS through. The NMOS transistor N2 is turned on by the voltage drop and the bias voltage. Accordingly, the static electricity is discharged to the ground voltage VSS via the turned-on NMOS transistor N2.

Next, referring to the operation of discharging the positive static electricity generated from the ground voltage VSS to the pad 10, the positive static electricity generated from the ground voltage VSS is transferred to the pad 10 by a parasitic diode of the NMOS transistor. Discharged immediately.

Finally, referring to the operation of discharging the positive static electricity generated from the power supply voltage VDD to the pad 10, the NMOS transistor N3 is turned on by the positive static electricity generated from the power supply voltage VDD so that the static electricity is supplied to the power supply voltage. From (VDD) to ground voltage (VSS). The static electricity transferred to the ground voltage VSS is discharged to the pad 10 by the parasitic diode of the NMOS transistor N2.

As such, in an embodiment of the electrostatic discharge circuit of the present invention, the first electrostatic discharge unit 20 connected between the pad 10 and the power supply voltage VDD performs an electrostatic discharge operation and at the same time, a discharge unit different from the pad 10. By applying a bias voltage to the transistor of 30 and improving the driving capability, the area formed on the semiconductor chip is reduced and the electrostatic discharge efficiency is improved.

In another embodiment of the present invention, as shown in FIG. 4, the first electrostatic discharge unit 20, the pad 10, and the ground voltage VSS are connected between the pad 10 and the power voltage VDD. It includes a second electrostatic discharge portion 30 connected between, and a third electrostatic discharge portion 40 connected between the power supply voltage (VDD) and the ground voltage (VSS) is similar to the previous embodiment but the third electrostatic There is a difference in that the bias voltage and the driving voltage can be applied to the discharge portion from the first electrostatic discharge portion.

The first electrostatic discharge part 20 transfers the static electricity to the bias voltage and the driving voltage when the static electricity is generated in the pad 10 and discharges the power to the power supply voltage VDD.

The second and third electrostatic discharge units 30 and 40 discharge static electricity generated from the pad 10 to the ground voltage VSS in response to the bias voltage and the driving voltage.

The electrostatic discharge circuit of FIG. 4 may be embodied in circuits as shown in FIGS. 5 to 8.

First, referring to FIG. 5, the first electrostatic discharge unit 20 may include a bias applying unit 22 applying a bias voltage to the second and third electrostatic discharge units in response to static electricity generated from the pad 10. The driving voltage applying unit 24 transfers the static electricity to the driving voltage in response to the voltage, and an electrostatic discharge path 26 for discharging the static electricity corresponding to the driving voltage to the power supply voltage VDD.

The first electrostatic discharge unit 20 is composed of a diode chain and is divided into a bias applying unit 22, a driving voltage applying unit 24, and an electrostatic discharge path 26 by two nodes (nodes A and B). do. In this case, the cathode of the diode is connected to the power supply voltage VDD, and the anode of the diode is connected to the pad 10 as described above.

That is, the bias applying unit 22, the driving voltage applying unit 24 and the electrostatic discharge path 26 are all made of a diode, the cathode of the diode is connected to the power supply voltage (VDD), the anode of the diode pad 10 Connected to the

The second electrostatic discharge unit 30 includes an NMOS transistor N2 which forms a current path path between the pad 10 and the ground voltage VSS in response to a driving voltage, and the NMOS transistor N2 is faster. The resistor R2 may be further connected between the gate of the NMOS transistor N2 and the ground voltage VSS to be driven. The trigger voltage may be lowered by applying a bias voltage to the substrate of the NMOS transistor N2.

Here, the substrate of the NMOS transistor N2 is connected to the node A of the first electrostatic discharge unit 20 and the gate is connected to the node B. The drain (or source) of the NMOS transistor N2 is connected to the pad 10, and the source (or drain) of the NMOS transistor N2 is connected to the ground voltage VSS.

In the electrostatic discharge circuit having the configuration of FIG. 5, the voltage of the bias applying unit 22 is applied to the substrate of the transistor N3 through the node A, and the voltage of the driving voltage applying unit 24 is the driving voltage through the node B. Since the NMOS transistor N3 may be turned on faster by being applied to the gate of the NMOS transistor N3, the electrostatic discharge performance may be further improved by the electrostatic discharge unit 30.

Meanwhile, in the configuration of FIG. 5, a resistor R5 may be additionally connected between the electrostatic discharge path 26 and the power supply voltage VDD as shown in FIG. 6. As shown in FIG. 6, when the resistor R5 is connected between the electrostatic discharge path 26 and the power supply voltage VDD, the amount of current flowing through the driving voltage applying unit 24 and the diodes constituting the electrostatic discharge path 26 is increased. This decreases and the amount of current discharged toward the NMOS transistor N3 increases.

Therefore, even if the size of the diodes constituting the driving voltage applying unit 24 and the electrostatic discharge path 26 is reduced, the electrostatic discharge performance is not significantly lowered. Therefore, the size of the diodes can be reduced to reduce the area of the electrostatic discharge circuit. have.

Discharge effect by the configuration as described above can be confirmed through FIG. FIG. 7 is a result of simulating a case in which the positive voltage is discharged to the ground voltage VSS when the static electricity is input to the pad 10.

In FIG. 7A, it can be seen that a bias applied to a substrate is higher than that of a general GGNMOS transistor. In addition, it can be seen from FIG. 7B that the NMOS of the present invention has improved performance due to a lower trigger voltage and a higher fail current than a general GGNMOS. The failure current is a current in which a failure occurs. The higher the failure current, the better the performance of the ESD device.

As shown in FIG. 8, the first electrostatic discharge unit 20 includes a bias applying unit 22, a driving voltage applying unit 24, and an electrostatic discharge path 26 each consisting of one or a plurality of PMOS transistors instead of diodes. It may be configured as.

That is, the bias applying unit 22 and the driving voltage applying unit 24 may be composed of at least one PMOS transistor. At this time, the gate of the PMOS transistor is connected to the power supply voltage VDD.

In addition, the electrostatic discharge path 26 may include at least one PMOS transistor connected between the driving voltage applying unit 24 and the power supply voltage VDD, or between the driving voltage applying unit 24 and the power supply voltage VDD. It may be composed of a plurality of PMOS transistors connected in series. At this time, the gate of the PMOS transistor is connected to the power supply voltage VDD.

Likewise, in the configuration of FIG. 8, a resistor R6 may be further connected between the electrostatic discharge path 26 and the power supply voltage VDD as shown in FIG. 9.

As described above, the present invention has a configuration in which the electrostatic discharge element performs an electrostatic discharge operation and at the same time helps drive other electrostatic discharge elements, thereby having an excellent electrostatic discharge performance and reducing the layout area of the electrostatic discharge circuit.

In addition, the present invention can provide an electrostatic discharge device having excellent electrostatic discharge performance by lowering the trigger voltage by applying a bias to the substrate of the transistor.

In addition, the present invention includes electrostatic discharge elements respectively connected between the pad and the voltages, and some of the electrostatic discharge elements serve to drive the other electrostatic discharge elements, thereby providing various discharge paths and at the same time. There is an effect that the electrostatic discharge performance of the electrostatic discharge elements of the can be improved.

In addition, the present invention provides a variety of discharge paths and improved electrostatic discharge performance by disposing the electrostatic discharge elements including the electrostatic discharge elements that serve to drive the electrostatic discharge and other electrostatic discharge elements in various paths, and at the same time the electrostatic discharge circuit There is an effect that the layout area of the can be reduced.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (37)

A first electrostatic discharge unit configured to discharge the static electricity to the first discharge line when static electricity is generated in the pad; And And a second electrostatic discharge unit configured to receive a bias voltage and a driving voltage from the first electrostatic discharge unit to discharge static electricity generated from the pad to a second discharge line. The method of claim 1, And wherein the first discharge line is a power supply voltage and the second discharge line is a ground voltage. The method of claim 1, The first electrostatic discharge unit may include a bias applying unit applying a bias voltage to the second electrostatic discharge unit in response to the static electricity generated in the pad; A driving voltage applying unit applying the driving voltage to the second electrostatic discharge unit in response to the bias voltage; And And a first electrostatic discharge path for discharging static electricity corresponding to the driving voltage to the first discharge line in response to the driving voltage. The method of claim 3, wherein And the driving voltage applying unit is connected to an output of the bias applying unit. The method of claim 3, wherein And the bias applying unit includes at least one diode connected between the pad and the driving voltage applying unit. The method of claim 3, wherein The driving voltage applying unit includes at least one diode connected between the bias applying unit and the first electrostatic discharge path. The method of claim 3, wherein And the first electrostatic discharge path includes one or more diodes connected between the driving voltage applying unit and the first discharge line. The method of claim 3, wherein And the first electrostatic discharge path includes a plurality of diodes connected in series between the driving voltage applying unit and the first power supply voltage. The method of claim 1, The second electrostatic discharge unit includes a MOS transistor for forming a current path path between the pad and the second discharge line in response to the bias voltage and the driving voltage applied from the first electrostatic discharge unit. Discharge device. The method of claim 9, The second electrostatic discharge unit further comprises a resistor connected between the gate of the MOS transistor and the second discharge line. The electrostatic discharge device of claim 9, wherein the bias voltage is applied to a substrate of the MOS transistor, and the driving voltage is applied to a gate of the MOS transistor. The method of claim 1, Between the first discharge line and the second discharge line is further connected to the third electrostatic discharge unit for discharging the static electricity transferred to any one of the first and second discharge line to any one of the second and first discharge line. Electrostatic discharge device characterized in that. The method of claim 12, The third electrostatic discharge unit may include a MOS transistor forming a current path path between the first discharge line and the second discharge line in response to the static electricity transferred to any one of the first and second discharge lines. Electrostatic discharge device. A first electrostatic discharge unit configured to discharge the static electricity to the first discharge line when static electricity is generated in the pad; A second electrostatic discharge unit configured to receive a bias voltage and a driving voltage from the first electrostatic discharge unit to discharge static electricity generated from the pad to a second discharge line; And A third electrostatic discharge unit configured to receive the bias voltage and the driving voltage from the first electrostatic discharge unit and discharge static electricity transferred to any one of the first and second discharge lines to any one of the second and first discharge lines; Electrostatic discharge device comprising a. The method of claim 14, And wherein the first discharge line is a power supply voltage line and the second discharge line is a ground voltage line. The method of claim 14, The first electrostatic discharge unit is a bias applying unit for applying a bias voltage to the second electrostatic discharge unit and the third electrostatic discharge unit in response to the static electricity generated in the pad; A driving voltage applying unit applying a driving voltage to the second electrostatic discharge unit and a third electrostatic discharge unit in response to the bias voltage; And And an electrostatic discharge path for discharging static electricity corresponding to the driving voltage to the first discharge line in response to the driving voltage. The method of claim 16, And the driving voltage applying unit is connected to an output terminal of the bias applying unit. The method of claim 16, And the bias applying unit includes at least one diode connected between the pad and the driving voltage applying unit. The method of claim 16, And the bias applying unit includes at least one MOS transistor connected between the pad and the driving voltage applying unit, and a gate of the MOS transistor is connected to the first discharge line. The method of claim 16, And the bias applying unit includes a plurality of MOS transistors connected in series between the pad and the driving voltage applying unit, and gates of the plurality of MOS transistors are commonly connected to the first discharge line. The method of claim 16, The driving voltage applying unit includes at least one diode formed between the bias applying unit and the electrostatic discharge path. The method of claim 16, The driving voltage applying unit includes at least one MOS transistor connected between the bias applying unit and the electrostatic discharge path, and the gate of the MOS transistor is connected to the first discharge line. The method of claim 16, And the electrostatic discharge path comprises at least one diode connected between the first electrostatic discharge and the first discharge line. The method of claim 16, The electrostatic discharge path includes at least one MOS transistor connected between the first electrostatic discharge unit and the first discharge line, wherein the gate of the MOS transistor is connected to the first discharge line. . The method of claim 16, The first electrostatic discharge unit further comprises a resistor connected between the first discharge line and the electrostatic discharge path. The method of claim 14, The second electrostatic discharge unit includes a MOS transistor for forming a current path between the pad and the second discharge line in response to the bias voltage and the driving voltage. The method of claim 26, The bias voltage is applied to the substrate of the MOS transistor, and the driving voltage is applied to the gate of the MOS transistor. The method of claim 26, The second electrostatic discharge unit further comprises a resistor connected between the gate of the MOS transistor and the second discharge line. The method of claim 14, The third electrostatic discharge unit includes a MOS transistor for forming a current path between the first discharge line and the second discharge line in response to the bias voltage and the driving voltage. The method of claim 29, The bias voltage is applied to the substrate of the MOS transistor, and the driving voltage is applied to the gate of the MOS transistor. The method of claim 29, The third electrostatic discharge unit further comprises a resistor connected between the gate of the MOS transistor and the second discharge line. A diode chain connected to an external input / output pad; A first NMOS transistor having a drain connected simultaneously to the input / output pad and an anode of a diode chain; And And a second NMOS transistor whose drain is simultaneously connected to a cathode of the diode chain and a voltage power supply. And the diode chain applies a voltage to substrates and gates of the first and second NMOS transistors. The method of claim 32, And a voltage applied to the gate is lower than a voltage applied to the substrate. The method of claim 32, Electrostatic discharge device, characterized in that the first resistance element is connected to the cathode side of the diode chain. The method of claim 32, And a second resistance element is connected to the gate terminal of the first NMOS transistor. The method of claim 32, And a third resistance element is connected to the gate terminal of the second NMOS transistor. A PMOS transistor chain connected to an external input / output pad; A first NMOS transistor having a drain connected simultaneously to the input / output pad and one end of the PMOS transistor chain; And A second NMOS transistor whose drain is simultaneously connected to the other end of the PMOS transistor chain and a voltage power supply; Wherein said PMOS transistor chain applies a voltage to substrates and gates of said first and second NMOS transistors.

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