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KR100842508B1 - Method for manufacturing device isolation layer of semiconductor device - Google Patents

Method for manufacturing device isolation layer of semiconductor device Download PDF

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KR100842508B1
KR100842508B1 KR1020060135970A KR20060135970A KR100842508B1 KR 100842508 B1 KR100842508 B1 KR 100842508B1 KR 1020060135970 A KR1020060135970 A KR 1020060135970A KR 20060135970 A KR20060135970 A KR 20060135970A KR 100842508 B1 KR100842508 B1 KR 100842508B1
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oxide film
film
device isolation
etching
sccm
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KR1020060135970A
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장정렬
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)

Abstract

A method for manufacturing an isolation layer of a semiconductor device is provided to form effectively the isolation layer by defining an isolation layer without forming a spacer oxide layer of a sidewall. A first oxide layer(202), a nitride layer(204), and a second oxide layer(206) are deposited on a silicon substrate(200). An inclined surface of the nitride layer is formed by dry-etching the second oxide layer and the nitride layer under C4F6, N2, Ar, and O2 gas atmosphere along a photoresist pattern. The photoresist pattern is removed. An isolation region is defined by etching the first oxide layer by using the second oxide layer and the inclined nitride layer as masks. A trench is formed on the isolation layer by using the first oxide layer, the nitride layer, and the second oxide layer as masks. An isolation layer is formed by burying an insulating material into the trench.

Description

반도체 소자의 소자 분리막 제조 방법{METHOD FOR MANUFACTURING DEVICE ISOLATION LAYER OF SEMICONDUCTOR DEVICE}METHODS FOR MANUFACTURING DEVICE ISOLATION LAYER OF SEMICONDUCTOR DEVICE

도 1a 내지 도 1f는 종래 방법의 일 실시 예에 따라 스페이서 산화막을 통해 소자 분리막을 형성하는 과정을 나타내는 공정 순서도,1A to 1F are process flowcharts illustrating a process of forming a device isolation film through a spacer oxide film according to an embodiment of the related art method;

도 2a 내지 도 2e는 본 발명의 일 실시 예에 따라 제 1 산화막, 질화막 및 제 2 산화막을 하드 마스크로 하여 소자 분리막을 형성하는 과정을 나타내는 공정 순서도.2A to 2E are flowcharts illustrating a process of forming a device isolation film using a first oxide film, a nitride film, and a second oxide film as hard masks according to an embodiment of the present invention.

본 발명은 반도체 소자의 소자 분리막에 관한 것으로, 더욱 상세하게는 반도체 소자의 소자간 전기적 절연을 위한 섀로우 트렌치 분리(STI : Shallow Trench Isolation) 방식의 소자 분리막을 형성하는데 적합한 반도체 소자의 소자 분리막 제조 방법에 관한 것이다.The present invention relates to a device isolation film of a semiconductor device, and more particularly to manufacturing a device isolation film of a semiconductor device suitable for forming a device for shallow trench isolation (STI: Shallow Trench Isolation) for the electrical isolation between devices of the semiconductor device It is about a method.

잘 알려진 바와 같이, 반도체 소자에는 트랜지스터, 커패시터 등의 단위 소자들이 반도체 소자의 용량에 따라 제한된 다수 개(예를 들면, 수천 내지 수십 억 등)가 집적되는데, 이러한 반도체 소자들은 독립적인 동작 특성을 위해 전기적으로 분리(또는 격리)하는 것이 필요하다.As is well known, semiconductor devices have a large number of unit devices, such as transistors and capacitors, limited by the capacity of the semiconductor device (eg, thousands to billions), which are integrated for independent operation. It is necessary to isolate (or isolate) electrically.

따라서, 이러한 반도체 소자들 간의 전기적인 분리를 위한 방법으로서, 실리콘 기판을 리세스(recess)하고 필드 산화막을 성장시키는 실리콘 부분 산화(LOCOS : LOCal Oxidation of Silicon) 방식과 실리콘 기판을 수직 방향으로 식각하여 절연 물질로 매립하는 섀로우 트렌치 분리(STI : Shallow Trench Isolation) 방식이 잘 알려져 있다.Therefore, as a method for electrical separation between such semiconductor devices, a silicon partial oxidation (LOCOS) method of recessing a silicon substrate and growing a field oxide layer and etching the silicon substrate in a vertical direction Shallow Trench Isolation (STI) is a well known method of filling with insulating material.

이 중에서 섀로우 트렌치 분리 방식의 소자 분리막은 반응성 이온 식각, 플라즈마 식각 등과 같은 건식 식각법을 사용하여 좁고 깊은 섀로우 트렌치를 형성하고, 그 속에 절연막을 갭필하는 방법으로서, 절연막이 채워진 트렌치 표면을 평탄하게 하므로 소자 분리 영역이 차지하는 면적을 줄여 미세화에 유리한 방법이다.The shallow trench isolation device isolation layer is a method of forming a narrow and deep shallow trench by using dry etching such as reactive ion etching or plasma etching, and gap fill the insulating film therein to planarize the trench surface filled with the insulating film. Therefore, it is an advantageous method for miniaturization by reducing the area occupied by device isolation regions.

도 1a 내지 도 1f는 종래 방법의 일 실시 예에 따라 스페이서 산화막을 통해 소자 분리막을 형성하는 과정을 나타내는 공정 순서도로서, 이들 도면을 참조하여 종래 방법에 따른 소자 분리막 제조 방법을 설명한다.1A to 1F are process flowcharts illustrating a process of forming a device isolation film through a spacer oxide film according to an exemplary embodiment of the related art. Referring to these drawings, a method of manufacturing a device isolation film according to the related art will be described.

도 1a를 참조하면, 실리콘 기판(100) 상부에 제 1 산화막(102), 질화막(104) 및 제 2 산화막(106)을 순차 증착한 후에, 그 상부에 제 1 산화막(102), 질화막(104) 및 제 2 산화막(106)을 패터닝하기 위한 포토 레지스트 패턴(108)을 형성한다. 여기에서, 포토레지스트 패턴(108)은 예를 들면, ArF를 이용하여 형성할 수 있다.Referring to FIG. 1A, after the first oxide film 102, the nitride film 104, and the second oxide film 106 are sequentially deposited on the silicon substrate 100, the first oxide film 102 and the nitride film 104 are disposed thereon. ) And a photoresist pattern 108 for patterning the second oxide film 106. Here, the photoresist pattern 108 may be formed using, for example, ArF.

그리고, 도 1b에 도시한 바와 같이 형성된 포토 레지스트 패턴(108)에 따라 제 2 산화막(106) 및 소정 깊이의 질화막(104)까지 건식 식각 방식 등의 방식으로 식각한다. 이 후, 포토 레지스트 패턴(108)을 소정의 애싱 공정을 통해 제거한다.The second oxide film 106 and the nitride film 104 having a predetermined depth are etched by a dry etching method according to the photoresist pattern 108 formed as shown in FIG. 1B. Thereafter, the photoresist pattern 108 is removed through a predetermined ashing process.

다음에, 실리콘 기판(100) 상부 전면에 산화 물질을 증착한 후 그 상부를 제 2 산화막 및 소정 깊이의 질화막(104)의 표면이 드러나도록 블랭킷(blanket) 식각하여 도 1c에 도시한 바와 같이 그 측벽에 스페이서 산화막(110)을 형성한다.Next, an oxide material is deposited on the entire upper surface of the silicon substrate 100, and then the upper portion is blanket-etched to expose the surface of the second oxide film and the nitride film 104 having a predetermined depth, as shown in FIG. 1C. A spacer oxide film 110 is formed on the sidewalls.

그리고, 스페이서 산화막(110)이 형성된 제 2 산화막(106) 및 소정 깊이의 질화막(104)을 하드 마스크로 하여 나머지 질화막(104) 및 제 1 산화막(102)을 실리콘 기판(100)이 드러나도록 식각하여 도 1d에 도시한 바와 같이 소자 분리막이 형성될 영역(A)을 정의한다.Then, using the second oxide film 106 having the spacer oxide film 110 and the nitride film 104 having a predetermined depth as a hard mask, the remaining nitride film 104 and the first oxide film 102 are etched to expose the silicon substrate 100. 1D, the region A in which the device isolation layer is to be formed is defined.

또한, 제 1 산화막(102), 질화막(104), 제 2 산화막(106) 및 스페이서 산화막(110)을 포함하는 구조물을 하드 마스크로 하여 소자 분리막이 형성될 영역의 실리콘 기판(100)을 식각하여 도 1e에 도시한 바와 같이 트렌치(112)를 형성한다.In addition, the silicon substrate 100 in the region where the device isolation layer is to be formed is etched by using a structure including the first oxide film 102, the nitride film 104, the second oxide film 106, and the spacer oxide film 110 as a hard mask. As shown in FIG. 1E, the trench 112 is formed.

이어서, 실리콘 기판(100)에 형성된 트렌치(112)에 절연 물질을 매립하여 도 1f에 도시한 바와 같이 섀로우 트렌치 분리 방식의 소자 분리막(114)을 형성한다. 이 후, 제 1 산화막(102), 질화막(104), 제 2 산화막(106) 및 스페이서 산화막(110)을 포함하는 구조물은 소정의 식각 과정을 통해 제거된다.Subsequently, an insulating material is embedded in the trench 112 formed in the silicon substrate 100 to form a device isolation film 114 having a shallow trench isolation method as illustrated in FIG. 1F. Thereafter, the structure including the first oxide film 102, the nitride film 104, the second oxide film 106, and the spacer oxide film 110 is removed through a predetermined etching process.

하지만, 상술한 바와 같은 종래의 소자 분리막 형성 방법에서는 스페이서 산화막을 형성하기 위해 산화막 증착 및 그에 따른 블랭킷 식각 공정이 수행되어야만 함으로써, 공정이 복잡해지고, 이에 따른 공정 상 오류로 인한 소자 분리막 특성이 저하되는 문제점이 있었다.However, in the conventional method of forming a device isolation layer as described above, an oxide layer deposition and a blanket etching process have to be performed to form a spacer oxide layer, thereby complicating the process and deteriorating device isolation characteristics due to a process error. There was a problem.

따라서, 본 발명은 상기한 종래 기술의 문제점을 해결하기 위한 것으로, 실리콘 기판 상부에 형성된 제 1 산화막, 질화막 및 제 2 산화막을 하드 마스크로 하여 소자 분리막이 형성될 영역을 정의할 수 있는 반도체 소자의 소자 분리막 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems of the prior art, a semiconductor device capable of defining the region where the device isolation film is to be formed by using the first oxide film, the nitride film and the second oxide film formed on the silicon substrate as a hard mask It is an object of the present invention to provide a method for manufacturing a device separator.

본 발명의 다른 목적은, 제 1 산화막, 질화막 및 제 2 산화막을 하드 마스크로 사용함으로써, 공정 횟수를 감소시켜 공정 상 오류 발생을 미연에 방지할 수 있는 반도체 소자의 소자 분리막 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a device isolation film manufacturing method of a semiconductor device which can prevent the occurrence of an error in a process by reducing the number of steps by using the first oxide film, the nitride film and the second oxide film as a hard mask. .

상기 목적을 달성하기 위하여 본 발명은, 반도체 소자에서 소자간 전기적 절연을 위한 소자 분리막을 제조하는 방법으로서, 실리콘 기판 상부에 제 1 산화막, 질화막 및 제 2 산화막을 순차 증착하는 단계와, 상기 제 2 산화막과 상기 질화막을 포토 레지스트 패턴에 따라 CCP(Capacitive Coupled Plasma) 방식으로 C4F6, N2, Ar, O2 가스 분위기에서 건식 식각하되, 상기 질화막의 식각면이 경사지도록 식각하는 단계와, 상기 포토 레지스트 패턴을 제거한 후 상기 제 2 산화막 및 경사진 질화막을 마스크로 하여 상기 실리콘 기판이 노출되도록 상기 제 1 산화막을 식각하여 소자 분리 영역을 정의하는 단계와, 상기 제 1 산화막, 질화막 및 제 2 산화막을 마스크로 하여 상기 소자 분리 영역에 트렌치를 형성하는 단계와, 상기 형성된 트렌치에 절연 물질을 매립하여 상기 소자 분리막을 형성하는 단계를 포함하는 반도체 소자의 소자 분리막 제조 방법을 제공한다.In order to achieve the above object, the present invention provides a method for manufacturing a device isolation film for electrical isolation between devices in a semiconductor device, comprising the steps of sequentially depositing a first oxide film, a nitride film and a second oxide film on a silicon substrate; Etching the oxide film and the nitride film in a C4F6, N2, Ar, O2 gas atmosphere in a capacitive coupled plasma (CCP) method according to a photoresist pattern, but etching the etching surface of the nitride film to be inclined; After removal, etching the first oxide film to expose the silicon substrate using the second oxide film and the inclined nitride film as a mask to define a device isolation region, and using the first oxide film, the nitride film, and the second oxide film as a mask. Forming a trench in the isolation region, and filling an insulating material in the formed trench It provides a device isolation film manufacturing method of a semiconductor device comprising the step of forming a magnetic separator.

본 발명의 상기 및 기타 목적과 여러 가지 장점은 이 기술분야에 숙련된 사 람들에 의해 첨부된 도면을 참조하여 하기에 기술되는 본 발명의 바람직한 실시 예로부터 더욱 명확하게 될 것이다.The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예에 대하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명의 기술요지는, 실리콘 기판 상부에 제 1 산화막, 질화막 및 제 2 산화막을 순차 증착하고, 제 2 산화막을 포토 레지스트 패턴에 따라 건식 식각한 후 질화막을 식각면이 경사지도록 건식 식각하며, 제 2 산화막 및 경사진 질화막을 마스크로 하여 제 1 산화막을 식각하여 소자 분리 영역을 정의하고, 제 1 산화막, 질화막 및 제 2 산화막을 마스크로 하여 상기 소자 분리 영역에 트렌치를 형성하며, 형성된 트렌치에 절연 물질을 매립하여 소자 분리막을 형성한다는 것으로, 이러한 기술적 수단을 통해 본 발명에서 목적으로 하는 바를 쉽게 달성할 수 있다.SUMMARY OF THE INVENTION A technical aspect of the present invention is to sequentially deposit a first oxide film, a nitride film, and a second oxide film on a silicon substrate, dry etch the second oxide film according to a photoresist pattern, and dry etch the nitride film so that the etching surface is inclined. A first oxide film is etched using an oxide film and an inclined nitride film as a mask to define a device isolation region, and a trench is formed in the device isolation region using a first oxide film, a nitride film, and a second oxide film as a mask, and an insulating trench is formed. By embedding the material to form the device isolation film, it is easy to achieve the object of the present invention through this technical means.

도 2a 내지 도 2e는 본 발명의 일 실시 예에 따라 제 1 산화막, 질화막 및 제 2 산화막을 하드 마스크로 하여 소자 분리막을 형성하는 과정을 나타내는 공정 순서도로서, 이들 도면을 참조하여 본 발명의 일 실시 예에 따른 소자 분리막 제조 방법을 설명한다.2A to 2E are process flowcharts illustrating a process of forming a device isolation film using a first oxide film, a nitride film, and a second oxide film as hard masks according to an embodiment of the present invention. The device isolation film manufacturing method according to the example will be described.

도 2a를 참조하면, 실리콘 기판(200) 상부에 제 1 산화막(202), 질화막(204) 및 제 2 산화막(206)을 순차 증착한 후에, 그 상부에 제 1 산화막(202), 질화막(204) 및 제 2 산화막(206)을 패터닝하기 위한 포토 레지스트 패턴(208)을 형성한다. 여기에서, 포토레지스트 패턴(208)은 예를 들면, ArF, KrF를 이용하여 형성할 수 있다.Referring to FIG. 2A, after the first oxide film 202, the nitride film 204, and the second oxide film 206 are sequentially deposited on the silicon substrate 200, the first oxide film 202 and the nitride film 204 are deposited thereon. ) And a photoresist pattern 208 for patterning the second oxide film 206. Here, the photoresist pattern 208 may be formed using, for example, ArF and KrF.

그리고, 도 2b에 도시한 바와 같이 형성된 포토 레지스트 패턴(208)에 따라 제 2 산화막(206) 및 질화막(204)까지 CCP(Capacitive Coupled Plasma) 방식으로 건식 식각한다. 이 후, 포토 레지스트 패턴(208)을 소정의 애싱 공정을 통해 제거한다. 여기에서, 건식 식각은, C4F6, N2, Ar, O2 가스 분위기에서 수행되며, 40 mT - 80 mT의 압력 조건으로 수행되고, 300 W - 500 W의 전력 조건으로 수행되며, 4 sccm - 10 sccm의 C4F6, 100 sccm - 200 sccm의 N2, 50 sccm - 150 sccm의 Ar 및 2 sccm - 5 sccm의 O2를 이용하여 수행되고, 20 초 - 50 초의 시간 조건으로 수행된다. 이 때, 질화막(204)을 식각할 때에는 C4F6 및 O2 가스량의 비율을 조절하여 식각면이 슬로프(slope)를 형성하도록 식각(즉, 식각면이 경사지도록 식각)한다.Then, the second oxide film 206 and the nitride film 204 are dry etched in a capacitive coupled plasma (CCP) method according to the photoresist pattern 208 formed as shown in FIG. 2B. Thereafter, the photoresist pattern 208 is removed through a predetermined ashing process. Here, dry etching is carried out in a gas atmosphere of C4F6, N2, Ar, O2, is carried out under a pressure condition of 40 mT-80 mT, a power condition of 300 W-500 W, 4 sccm-10 sccm C4F6, 100 sccm-200 sccm N2, 50 sccm-150 sccm Ar and 2 sccm-5 sccm O2, are carried out with a time condition of 20 seconds-50 seconds. At this time, when the nitride film 204 is etched, the etched surface is etched (that is, etched so that the etched surface is inclined) by adjusting the ratio of the amount of C4F6 and O2 gas.

다음에, 제 2 산화막(206) 및 경사면이 경사진 질화막(204)을 하드 마스크로 하여 제 1 산화막(202)을 실리콘 기판(200)이 드러나도록 식각하여 도 2c에 도시한 바와 같이 소자 분리막이 형성될 영역(B)을 정의한다.Next, the first oxide film 202 is etched to expose the silicon substrate 200 by using the second oxide film 206 and the nitride film 204 inclined inclined surface as a hard mask, thereby forming the device isolation film as shown in FIG. 2C. The region B to be formed is defined.

또한, 제 1 산화막(202), 질화막(204) 및 제 2 산화막(206)을 포함하는 구조물을 하드 마스크로 하여 소자 분리막이 형성될 영역의 실리콘 기판(200)을 식각하여 도 2d에 도시한 바와 같이 트렌치(210)를 형성한다.In addition, the silicon substrate 200 in the region where the device isolation layer is to be formed is etched using the structure including the first oxide film 202, the nitride film 204, and the second oxide film 206 as a hard mask, as shown in FIG. 2D. The trench 210 is formed together.

이어서, 실리콘 기판(200)에 형성된 트렌치(210)에 절연 물질을 매립하여 도 2e에 도시한 바와 같이 섀로우 트렌치 분리 방식의 소자 분리막(212)을 형성한다. 이 때, 제 1 산화막(202), 질화막(204) 및 제 2 산화막(206)을 포함하는 구조물은 소정의 식각 과정을 통해 제거된다.Subsequently, an insulating material is embedded in the trench 210 formed on the silicon substrate 200 to form a device isolation film 212 having a shallow trench isolation method as illustrated in FIG. 2E. At this time, the structure including the first oxide film 202, the nitride film 204 and the second oxide film 206 is removed through a predetermined etching process.

따라서, 질화막 식각 시 슬로프를 형성하도록 식각하여 그 산화막들 및 질화 막을 하드 마스크로 하여 트렌치를 형성하고, 이를 매립하여 소자 분리막을 형성할 수 있다.Accordingly, the trench may be etched to form a slope during etching of the nitride film to form a trench using the oxide films and the nitride film as hard masks, and the device isolation layer may be formed by filling the trench.

이상의 설명에서는 본 발명의 바람직한 실시 예들을 제시하여 설명하였으나 본 발명이 반드시 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함을 쉽게 알 수 있을 것이다.In the foregoing description, the present invention has been described with reference to preferred embodiments, but the present invention is not necessarily limited thereto. Those skilled in the art will appreciate that the present invention may be modified without departing from the spirit of the present invention. It will be readily appreciated that branch substitutions, modifications and variations are possible.

이상 설명한 바와 같이 본 발명은, 실리콘 기판 상에 패터닝된 제 1 산화막, 질화막, 제 2 산화막 및 측벽의 스페이서 산화막을 이용하여 소자 분리 영역을 정의하고, 이러한 소자 분리 영역에 소자 분리막을 형성하는 종래 방법과는 달리, 실리콘 기판 상부에 제 1 산화막, 질화막 및 제 2 산화막을 순차 증착하고, 제 2 산화막을 포토 레지스트 패턴에 따라 건식 식각한 후 질화막을 식각면이 경사지도록 건식 식각하며, 제 2 산화막 및 경사진 질화막을 마스크로 하여 제 1 산화막을 식각하여 소자 분리 영역을 정의하고, 제 1 산화막, 질화막 및 제 2 산화막을 마스크로 하여 상기 소자 분리 영역에 트렌치를 형성하며, 형성된 트렌치에 절연 물질을 매립하여 소자 분리막을 형성함으로써, 측벽의 스페이서 산화막을 형성하지 않고 소자 분리 영역을 정의하여 소자 분리막을 효과적으로 형성할 수 있다.As described above, the present invention uses a first oxide film, a nitride film, a second oxide film, and a spacer oxide film of sidewalls patterned on a silicon substrate to define a device isolation region, and to form a device isolation film in the device isolation region. Unlike, the first oxide film, the nitride film and the second oxide film are sequentially deposited on the silicon substrate, the second oxide film is dry etched according to the photoresist pattern, and the nitride film is dry etched so that the etching surface is inclined, the second oxide film and A first oxide film is etched using the inclined nitride film as a mask to define an isolation region, a trench is formed in the device isolation region using the first oxide film, the nitride film, and the second oxide film as a mask, and an insulating material is embedded in the formed trench. By forming the device isolation film, the device isolation region is defined without forming the spacer oxide film on the sidewalls. It can form an effective separator character.

따라서, 반도체 소자의 소자 분리막 제조 과정에서 공정 횟수를 감소시킴으로써, 공정 상 오류 발생을 미연에 방지하여 제조 수율을 향상시킬 수 있다.Therefore, by reducing the number of steps in the device isolation film manufacturing process of the semiconductor device, it is possible to prevent the occurrence of an error in the process to improve the manufacturing yield.

Claims (5)

삭제delete 반도체 소자에서 소자간 전기적 절연을 위한 소자 분리막을 제조하는 방법으로서,A method of manufacturing a device isolation film for electrical insulation between devices in a semiconductor device, 실리콘 기판 상부에 제 1 산화막, 질화막 및 제 2 산화막을 순차 증착하는 단계와,Sequentially depositing a first oxide film, a nitride film, and a second oxide film on the silicon substrate; 상기 제 2 산화막과 상기 질화막을 포토 레지스트 패턴에 따라 CCP(Capacitive Coupled Plasma) 방식으로 C4F6, N2, Ar, O2 가스 분위기에서 건식 식각하되, 상기 질화막의 식각면이 경사지도록 식각하는 단계와,Etching the second oxide film and the nitride film in a C4F6, N2, Ar, O2 gas atmosphere by a capacitive coupled plasma (CCP) method according to a photoresist pattern, but etching the etching surface of the nitride film to be inclined; 상기 포토 레지스트 패턴을 제거한 후 상기 제 2 산화막 및 경사진 질화막을 마스크로 하여 상기 실리콘 기판이 노출되도록 상기 제 1 산화막을 식각하여 소자 분리 영역을 정의하는 단계와,Removing the photoresist pattern and etching the first oxide film to expose the silicon substrate using the second oxide film and the inclined nitride film as a mask to define a device isolation region; 상기 제 1 산화막, 질화막 및 제 2 산화막을 마스크로 하여 상기 소자 분리 영역에 트렌치를 형성하는 단계와,Forming a trench in the device isolation region using the first oxide film, the nitride film, and the second oxide film as a mask; 상기 형성된 트렌치에 절연 물질을 매립하여 상기 소자 분리막을 형성하는 단계Embedding an insulating material in the formed trench to form the device isolation layer 를 포함하는 반도체 소자의 소자 분리막 제조 방법.Device isolation film manufacturing method of a semiconductor device comprising a. 제 2 항에 있어서,The method of claim 2, 상기 건식 식각은, 4 sccm - 10 sccm의 C4F6, 100 sccm - 200 sccm의 N2, 50 sccm - 150 sccm의 Ar 및 2 sccm - 5 sccm의 O2를 이용하여 수행되는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.The dry etching is performed by using 4 sccm-10 sccm of C4F6, 100 sccm-200 sccm of N2, 50 sccm-150 sccm of Ar, and 2 sccm-5 sccm of O2. Manufacturing method. 제 2 항에 있어서,The method of claim 2, 상기 건식 식각은, 40 mT - 80 mT의 압력 조건, 300 W - 500 W의 전력 조건 및 20 초 - 50 초의 시간 조건으로 수행되는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.The dry etching may be performed under a pressure condition of 40 mT-80 mT, a power condition of 300 W-500 W, and a time condition of 20 seconds-50 seconds. 제 2 항에 있어서,The method of claim 2, 상기 건식 식각은, 상기 질화막 식각 시 상기 C4F6 및 O2의 가스량 비율을 조절하여 그 식각면이 경사지도록 하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.The dry etching method of manufacturing a device isolation film of a semiconductor device, characterized in that the etching surface is inclined by adjusting the gas amount ratio of the C4F6 and O2 during the etching of the nitride film.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347227A (en) * 2010-07-30 2012-02-08 中芯国际集成电路制造(上海)有限公司 Metal gate formation method
CN103117213A (en) * 2011-11-16 2013-05-22 中芯国际集成电路制造(上海)有限公司 Metallic grid electrode forming method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970030627A (en) * 1995-11-03 1997-06-26 김주용 Device Separation Method of Semiconductor Devices
KR20050072586A (en) * 2004-01-07 2005-07-12 세메스 주식회사 Apparatus for etching wafer edge using icp-rie
KR20060077018A (en) * 2004-12-29 2006-07-05 동부일렉트로닉스 주식회사 Method for forming trench in a active area of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970030627A (en) * 1995-11-03 1997-06-26 김주용 Device Separation Method of Semiconductor Devices
KR20050072586A (en) * 2004-01-07 2005-07-12 세메스 주식회사 Apparatus for etching wafer edge using icp-rie
KR20060077018A (en) * 2004-12-29 2006-07-05 동부일렉트로닉스 주식회사 Method for forming trench in a active area of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347227A (en) * 2010-07-30 2012-02-08 中芯国际集成电路制造(上海)有限公司 Metal gate formation method
CN103117213A (en) * 2011-11-16 2013-05-22 中芯国际集成电路制造(上海)有限公司 Metallic grid electrode forming method

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