KR100835682B1 - Analog digital converter with variable sampling period according to noise level, Audio recorder and Pacemaker therewith - Google Patents

Abstract

Disclosed are an analog to digital converter for controlling a sampling period according to noise, an audio recording device, and a pacemaker using the same.

The present invention relates to an analog-to-digital converter including a delta sigma analog-to-digital converter, comprising: an analog-to-digital converter for converting an analog input signal into a digital signal, a noise detector for detecting a noise component of the digital signal, and a plurality of noise components according to the noise component And a clock selector configured to select one of different clock signals and apply it to the clock input of the analog-digital converter.

In addition, the present invention provides an analog-to-digital converter comprising a delta sigma analog-to-digital converter, comprising: a clock generator for generating a clock signal of a predetermined period; an analog-to-digital converter for converting an analog input signal into a digital signal; And a noise multiplier for detecting a noise component, and a frequency multiplier for multiplying the clock signal by a multiple proportional to the noise component and applying the multiplied clock signal to a clock input of the analog-digital converter.

In addition, the present invention provides an analog-to-digital converter comprising a delta sigma analog-to-digital converter, comprising: a first clock generator for generating a clock signal of a first period, and a clock signal for generating a clock signal of a second period greater than the first period; 2, a clock generator, an analog-digital converter for converting an analog input signal into a digital signal, a noise detector for detecting a noise component of the digital signal, and if the noise component is greater than or equal to a threshold value, a clock of the analog-digital converter. And a switching unit for connecting an input and connecting the second clock generator with a clock input of the analog-digital converter if the noise component is less than a threshold.

According to the present invention, by lowering the sampling period in a low noise environment and increasing the sampling period in a noisy environment, a constant SNR can be maintained and power consumption can be minimized.

Description

Analog-to-digital converters that control sampling periods based on noise, audio recorders and pacemakers using them {Analog digital converter with variable sampling period according to noise level, Audio recorder and Pacemaker therewith}

1 is a block diagram of an analog-to-digital converter for controlling a sampling period according to noise according to an embodiment of the present invention.

2 illustrates an example of the noise detector of FIG. 1.

3 is a block diagram of an analog-to-digital converter for controlling a sampling period according to noise according to another embodiment of the present invention.

4 is a block diagram of an analog-to-digital converter for controlling a sampling period according to noise according to another embodiment of the present invention.

5 is a block diagram of an audio device using the analog-to-digital converter of FIG. 1.

6 is a block diagram of a pacemaker using the analog-to-digital converter of FIG. 1.

FIG. 7 is a graph illustrating a relationship between a sampling rate and an SNR in FIG. 1.

The present invention relates to a delta sigma analog-to-digital converter (Δ-Σ analog-to-digital converter (ADC)), and in particular, an analog-to-digital converter for controlling the sampling period according to noise, an audio recording device and a pacemaker It is about.

In general, a delta sigma analog-to-digital converter (Δ-Σ analog-to-digital converter (ADC)) consists of an analog sigma delta modulator, a decimator, a lowpass filter, and an accumulate and dump circuit.

The sigma delta modulator inputs and modulates an analog signal. The sigma delta modulator uses secondary, tertiary and quaternary sigma delta modulators depending on the purpose of the A / D converter. The output data of the sigma delta modulator consists of 1 bit. The output data is input to a Finite Impulse Response comb filter. The decimator, low pass filter, accumulation and dump circuit are implemented by FIR comb filter to remove high frequency noise. In this case, a plurality of comb filters are used to increase the signal-to-noise ratio to increase the dynamic range of the A / D conversion, that is, the bit resolution, and the decimator uses an operating frequency to reduce the high frequency noise. Lower it to reduce noise in the band as it passes through multiple stages of the comb filter. The transfer function H (Z) of the decimator using the comb filter is expressed by Equation 1 below when the decimation ratio is D.

Since the decimator using the comb filter having the transfer function as shown in Equation 1 does not have a linear characteristic for phase and uses multiple stages of the comb filter, the bit resolution must be increased and decimated whenever passing through the preceding comb filter. Therefore, a typical decimator uses a comb filter of about four stages. With this characteristic, the FIR comb filter is decimated at D: 1 and output. At this time, the output data bit is output as a specific bit. The output of the FIR comb filter is combined and output by the FIR combination filter. At this time, the output signal is a digital signal converted into digital.

In general, the sampling period of the delta sigma analog-to-digital converter is determined according to the signal-to-noise ratio (SNR) of the input signal.

However, an input signal, such as an ECG signal, does not always have a constant signal-to-noise ratio, but has a non-uniform signal-to-noise ratio depending on the subject's physical state (eg, sleeping and immediately after exercise) or environmental conditions.

Therefore, in designing an analog-to-digital converter (particularly a delta sigma analog-to-digital converter (ADC)) to convert an input signal having a non-uniform SNR characteristic into a digital signal, the sampling period of the input signal is SNR. This should be decided considering the worst case. That is, a fast sampling period is required assuming when the SNR is not the best.

Therefore, the conventional delta sigma analog-to-digital converter operates with a fast sampling period considering the lowest SNR of the allowed range, even though the input signal exhibits high SNR characteristics, which means frequent circuit operation. Therefore, the faster the sampling period, the more the power consumption per hour of the analog-to-digital converter (ADC) becomes unnecessary.

Accordingly, the first technical problem to be achieved by the present invention is to reduce the sampling period in a low noise environment and to increase the sampling period in a noisy environment, thereby maintaining a constant SNR, and sampling period according to noise that can minimize power consumption. To provide an analog-to-digital converter for controlling the.

The second technical problem to be achieved by the present invention is to provide an audio recording apparatus using an analog-to-digital converter for controlling the sampling period according to the noise.

The third technical problem to be achieved by the present invention is to provide a cardiac pacemaker using an analog-to-digital converter that controls the sampling period according to the noise.

In order to solve the above first technical problem, the present invention provides an analog-to-digital converter comprising a delta sigma analog-to-digital converter, the analog-to-digital converter for converting an analog input signal into a digital signal, detecting the noise component of the digital signal It provides an analog-to-digital converter for controlling the sampling period according to the noise including a noise detector and a clock selector for selecting any one of a plurality of different clock signals according to the noise component to apply to the clock input of the analog-to-digital converter. do.

In addition, in order to solve the first technical problem described above, the present invention is a analog-to-digital converter comprising a delta sigma analog-to-digital converter, the clock generator for generating a clock signal of a predetermined period, converting the analog input signal to a digital signal An analog-to-digital converter, a noise detector for detecting a noise component of the digital signal, a frequency multiplier for multiplying the clock signal by a multiple proportional to the noise component and applying the multiplied clock signal to a clock input of the analog-digital converter It provides an analog to digital converter for controlling the sampling period according to the noise, including.

In addition, in order to solve the first technical problem described above, the present invention is an analog-to-digital converter including a delta sigma analog-to-digital converter, the first clock generating unit for generating a clock signal of the first period, greater than the first period A second clock generator for generating a clock signal of a second period, an analog-digital converter for converting an analog input signal to a digital signal, a noise detector for detecting a noise component of the digital signal, and if the noise component is equal to or greater than a threshold value, A sampling period connected to a clock input of the analog digital converter, and a switching unit configured to connect the second clock generator to a clock input of the analog digital converter if the noise component is less than a threshold; It provides an analog to digital converter.

Meanwhile, in order to solve the second technical problem, the present invention provides an audio device including a delta sigma analog-to-digital converter, comprising: an analog-to-digital converter for converting an analog input signal into a digital signal and detecting a noise component of the digital signal Sampling according to noise, including a noise detector configured to select one of a plurality of different clock signals according to the noise component, a clock selector configured to apply the clock signal to the analog-digital converter, and an audio recorder configured to store the digital signal. An audio recording apparatus using an analog-to-digital converter for controlling periods is provided.

On the other hand, in order to solve the third technical problem, the present invention is a cardiac pacemaker comprising a delta sigma analog-to-digital converter, the sensor unit for converting the heart rate to an analog input signal, converting the analog input signal into a digital signal An analog-to-digital converter, a noise detector for detecting a noise component of the digital signal, a clock selector for selecting any one of a plurality of different clock signals according to the noise component, and applying it to a clock input of the analog-digital converter; The present invention provides a pacemaker using an analog-to-digital converter for controlling a sampling period according to noise including a stopwatch generating a reference clock at a period of time and an electric shock unit for outputting an electrical stimulus according to the digital signal and the reference clock.

The present invention proposes a method for adjusting an optimal sampling period for minimizing power consumption for an input having a variable SNR. To this end, the noise level of the input signal is detected and fed back to adjust the sampling period.

The present invention relates to an analog-to-digital converter device having an optimal sampling period for implementing low power and its operation.

1 is a block diagram of an analog-to-digital converter for controlling a sampling period according to noise according to an embodiment of the present invention.

The analog to digital converter of FIG. 1 includes a delta sigma analog to digital converter.

The analog to digital converter 110 converts an analog input signal into a digital signal. The output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 110 may be composed of a plurality of bits and transmitted in parallel.

The noise detector 120 detects a noise component of the digital signal. Preferably, the noise detector 120 measures a differentiator that differentiates the digital signal and a number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined section, and performs noise quantification to detect a noise component. It may include.

The output signal ND_out of the noise detector 120 is a digital signal representing the degree of noise included in the output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 110 in units of bits or an analog-digital converter. It may be an analog signal representing a noise level included in the output signal (analog-to-digital converter (ADC) _out) of 110 at a voltage level.

At this time, the noise counter is assumed that the output of the analog-to-digital converter 110 is x (n), and the output of the differentiator is d (n) = x (n) -x (n-1). Noise quantization may be performed by measuring the number of times a sign of) changes from negative to positive or positive to negative within a predetermined interval.

The clock selector 130 selects one of a plurality of different clock signals according to the noise component detected by the noise detector 120 and applies it to the clock input of the analog-to-digital converter 110.

In the present invention, the analog input signal In is converted into a plurality of digital output signals ADC_out through the delta sigma analog-to-digital conversion unit ADC 110. The digital output signal is input to the noise detector 120 again, and the noise detector 120 determines the current noise state of the input signal and sends the output signal ND_out. The output signal ND_out is fed back to the clock CLK signal input unit which determines the operation speed of the analog-to-digital conversion unit ADC 110 to adjust the period of the clock CLK signal. In this way, the operating speed of the analog-to-digital converter (ADC) 110 can be determined according to the noise state of the current input signal.

FIG. 2 illustrates an example of the noise detector 120 of FIG. 1.

Noise quantification to determine the noise level of the input signal is possible by measuring the analog-to-digital converter (ADC) output signal through a differentiator and then measuring the number of intersections with zero of this signal. That is, when the output signal x (n) of the analog-to-digital converter (ADC) is input to the differentiator, the signal becomes d (n) = x (n)-x (n-1) and the sign of d (n). Is the same as Equation 2 below.

sgn {d (n)} = +1, d (n)> = 0

sgn {d (n)} = -1, d (n) <0

At this time, the noise signal can be quantified by finding the number of intersection points of the above signal d (n) with 0.

3 is a block diagram of an analog-to-digital converter for controlling a sampling period according to noise according to another embodiment of the present invention.

The clock generator (not shown) generates a clock signal f of a predetermined period.

The analog to digital converter 310 converts an analog input signal into a digital signal. The output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 310 may be composed of a plurality of bits and transmitted in parallel.

The noise detector 320 detects a noise component of the digital signal. Preferably, the noise detector 320 measures a differentiator that differentiates the digital signal and a number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined section to perform noise quantification to detect a noise component. It may include.

The output signal ND_out of the noise detector 320 is a digital signal representing the degree of noise included in the output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 310 in units of bits or an analog-digital converter. The signal may be an analog signal indicating a noise level included in the output signal of the 310 (analog-to-digital converter (ADC) _out).

The frequency multiplier 330 multiplies the clock signal f of a predetermined period by a multiple proportional to the noise component detected by the noise detector 320, and multiplies the multiplied clock signal fx N by the analog-digital converter. Applies to the clock input of (310).

4 is a block diagram of an analog-to-digital converter for controlling a sampling period according to noise according to another embodiment of the present invention.

The first clock generator 431 generates a clock signal of a first period.

The second clock generator 432 generates a clock signal having a second period greater than the first period.

Preferably, the first period may be a clock signal for the normal operation of the analog-to-digital converter 410, and the second period may be a preliminary clock signal for lowering the sampling rate of the analog-to-digital converter 410.

The analog to digital converter 410 converts an analog input signal into a digital signal. The output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 410 may be composed of a plurality of bits and transmitted in parallel.

The noise detector 420 detects noise components of the digital signal. Preferably, the noise detector 420 measures a differentiator for differentiating the digital signal and a number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined section to perform noise quantification to detect a noise component. It may include.

The output signal ND_out of the noise detector 420 is a digital signal representing the noise level included in the output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 410 in bits, or an analog-digital converter. It may be an analog signal representing a noise level included in the output signal (analog-to-digital converter (ADC) _out) of 410 at a voltage level.

The switching unit 440 connects the first clock generator 431 to the clock input of the analog-to-digital converter 410 when the noise component detected by the noise detector 420 is greater than or equal to the threshold value, and the noise component is the threshold value. If less, the second clock generator 410 is connected to the clock input of the analog-to-digital converter 410. Preferably, the switching unit 440 includes logic gates, and applies the noise component, which is a digital signal, to the logic of the logic gate to turn the switches on or off, thereby providing the first clock generator 431 or the second clock. One of the generators 432 may be connected to the clock input of the analog-to-digital converter 410. In this case, the logic gate may include at least one of an AND gate and an OR gate.

5 is a block diagram of an audio device using the analog-to-digital converter of FIG. 1.

The analog to digital converter 510 converts an analog input signal into a digital signal. The output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 510 may be composed of a plurality of bits and transmitted in parallel.

Preferably, the analog input terminal of the analog-to-digital converter 510 may include a voice sensor such as a microphone. Preferably, the analog input terminal of the analog-to-digital converter 510 may be connected to an audio output of an MP3 player, a CD player, or other sound equipment.

The noise detector 520 detects noise components of the digital signal. Preferably, the noise detector 520 measures a differentiator that differentiates the digital signal and a number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined section, and performs noise quantification to detect a noise component. It may include.

The output signal ND_out of the noise detector 520 is a digital signal representing the degree of noise included in the output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 510 in bits, or an analog-digital converter. The noise level included in the output signal (analog-to-digital converter (ADC) _out) of 510 may be an analog signal representing a voltage level.

The clock selector 530 selects one of a plurality of different clock signals according to the noise component detected by the noise detector 520 and applies it to the clock input of the analog-to-digital converter 510.

The audio recorder 540 stores a digital signal. Preferably, the audio recording unit 540 may include a volatile memory device or a nonvolatile memory device as a storage space. Preferably, the audio recording unit 540 may include an optical recording medium such as a CD-ROM, a DVD + ROM, and a DVD-ROM as a storage space. Preferably, the audio recording unit 540 may include a writer for storing the digital signal in the containing storage space.

6 is a block diagram of a pacemaker using the analog-to-digital converter of FIG. 1.

The analog to digital converter 610 converts an analog input signal into a digital signal. The output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 610 may consist of a plurality of bits and may be transmitted in parallel. Preferably, the analog input terminal of the analog to digital converter 610 may be connected to a sensor device that detects a heartbeat.

The noise detector 620 detects noise components of the digital signal. Preferably, the noise detector 620 measures a differentiator for differentiating the digital signal and a number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined section to perform noise quantification to detect a noise component. It may include.

The output signal ND_out of the noise detector 620 is a digital signal representing a noise level included in the output signal (analog-to-digital converter (ADC) _out) of the analog-to-digital converter 610 in units of bits, or an analog-digital converter. It may be an analog signal representing a noise level included in the output signal (analog-to-digital converter (ADC) _out) of 610 at a voltage level.

The clock selector 630 selects one of a plurality of different clock signals according to the noise component detected by the noise detector 620 and applies it to the clock input of the analog-to-digital converter 610.

The stop watch 640 generates a reference clock at predetermined periods. The reference clock is a clock to provide a reference for the human heartbeat cycle.

The electric shock unit 650 outputs an electrical stimulus according to the digital signal of the analog-digital converter 610 and the reference clock of the stopwatch 640. At this time, the electrical stimulation is an electrical signal for pacing, has a small voltage and a small current of harmless levels to the human body.

Preferably, the electric shock unit 650 includes a means for comparing the digital signal of the analog-digital converter 610 and the reference clock of the stopwatch 640, and the period of the digital signal of the analog-digital converter 610. May be configured to output an electrical stimulus when the signal becomes slower than the reference clock of the stop watch 640.

FIG. 7 is a graph illustrating a relationship between a sampling rate and an SNR in FIG. 1.

7 shows ideal values of SNR according to the order and oversampling rate (OSR) of the delta sigma analog-to-digital converter. As shown in FIG. 76, it can be seen that as the loop order inside the analog-to-digital converter increases, that is, as the oversampling ratio increases, the SNR increases.

That is, when the SNR of the input signal is low, the SNR can be increased by increasing the oversampling ratio or increasing the analog-to-digital converter loop order.

An analog-to-digital converter comprising a delta sigma analog-to-digital converter according to the present invention comprises means for detecting the degree of noise component of the signal output through the delta-sigma analog-to-digital converter according to the analog input signal, Adjust the sampling rate of the delta sigma analog-to-digital converter according to the degree.

In this case, the means for detecting the degree of the noise component may detect the output of the delta sigma analog-to-digital converter for a predetermined time to detect the degree of the noise component. That is, the output of the means for detecting the degree of noise component changes the operating period of the delta analog to digital converter.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary and will be understood by those of ordinary skill in the art that various modifications and variations can be made therefrom. However, such modifications should be considered to be within the technical protection scope of the present invention. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, by lowering the sampling period in a low noise environment and increasing the sampling period in a noisy environment, a constant SNR can be maintained and power consumption can be minimized.

Claims (11)

delete An analog-to-digital converter comprising a delta sigma analog-to-digital converter, An analog-digital converter for converting an analog input signal into a digital signal; A noise detector for detecting a noise component of the digital signal; And A clock selector configured to select one of a plurality of different clock signals according to the noise component and apply the selected clock signal to a clock input of the analog-digital converter; The noise detector, A differentiator for differentiating the digital signal; And And a noise counter for detecting noise components by measuring the number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined period and detecting noise components. Device. The method of claim 2, The noise counter is When the output of the analog-to-digital converter is called x (n) and the output of the differentiator is called d (n) = x (n) -x (n-1), the sign of d (n) is within a predetermined section. An analog to digital converter for controlling the sampling period according to the noise, characterized in that for measuring the number of changes from negative to positive or from positive to negative. An analog-to-digital converter comprising a delta sigma analog-to-digital converter, A clock generator generating a clock signal of a predetermined period; An analog-digital converter for converting an analog input signal into a digital signal; A noise detector for detecting a noise component of the digital signal; And A frequency multiplier configured to multiply the clock signal by a multiple proportional to the noise component to apply the multiplied clock signal to a clock input of the analog-digital converter; The noise detector, A differentiator for differentiating the digital signal; And And a noise counter for detecting noise components by measuring the number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined period and detecting noise components. Device. An analog-to-digital converter comprising a delta sigma analog-to-digital converter, A first clock generator which generates a clock signal of a first period; A second clock generator configured to generate a clock signal having a second period greater than the first period; An analog-digital converter for converting an analog input signal into a digital signal; A noise detector for detecting a noise component of the digital signal; And A switching unit connecting the first clock generator to the clock input of the analog-digital converter if the noise component is greater than or equal to a threshold value; and connecting the second clock generator to the clock input of the analog-digital converter of the analog clock converter if the noise component is less than a threshold. Including, The noise detector, A differentiator for differentiating the digital signal; And And a noise counter for detecting noise components by measuring the number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined period and detecting noise components. Device. delete An audio device comprising a delta sigma analog-to-digital converter, An analog-digital converter for converting an analog input signal into a digital signal; A noise detector for detecting a noise component of the digital signal; A clock selector which selects one of a plurality of different clock signals according to the noise component and applies it to a clock input of the analog-digital converter; And An audio recorder for storing the digital signal, The noise detector, A differentiator for differentiating the digital signal; And And a noise counter for detecting noise components by measuring the number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined period and detecting noise components. Audio recording device using the device. The method of claim 7, wherein The noise counter is When the output of the analog-to-digital converter is called x (n) and the output of the differentiator is called d (n) = x (n) -x (n-1), the sign of d (n) is within a predetermined section. An audio recording apparatus using an analog-to-digital converter for controlling the sampling period according to the noise, characterized in that for measuring the number of times from negative to positive or from positive to negative at. delete A pacemaker comprising a delta sigma analog-to-digital converter, A sensor unit for converting a heartbeat into an analog input signal; An analog-digital converter for converting the analog input signal into a digital signal; A noise detector for detecting a noise component of the digital signal; A clock selector which selects one of a plurality of different clock signals according to the noise component and applies it to a clock input of the analog-digital converter; A stop watch generating a reference clock at a predetermined period; And An electric shock unit configured to output an electrical stimulus according to the digital signal and the reference clock, The noise detector, A differentiator for differentiating the digital signal; And And a noise counter for detecting noise components by measuring the number of times that the magnitude of the differentiated digital signal becomes zero within a predetermined section and detecting noise components. Pacemaker using the device. The method of claim 10, The noise counter is When the output of the analog-to-digital converter is called x (n) and the output of the differentiator is called d (n) = x (n) -x (n-1), the sign of d (n) is within a predetermined section. A pacemaker using an analog-to-digital converter for controlling the sampling period according to noise, characterized in that it measures the number of times from negative to positive or from positive to negative at.

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