KR100716644B1 - Method for manufacturing mim capacitor in semiconductor device - Google Patents

Abstract

The present invention provides a method of manufacturing a MIM capacitor which can increase the capacitance of the capacitor to increase the capacitance of the capacitor while minimizing the leakage current characteristics. Forming a pattern hole by etching the sacrificial insulating layer, forming a sacrificial pattern layer having a hemispherical structure in the inner wall of the pattern hole, and depositing a material for the lower electrode to fill the pattern hole; Removing the sacrificial insulating layer and the sacrificial pattern layer to form a lower electrode having a hemispherical surface, forming a dielectric film along the surface of the lower electrode, and forming an upper electrode to cover the dielectric layer; It provides a method of manufacturing a MIM capacitor of a semiconductor device comprising the step.

MIM capacitors, hemispherical, MPS

Description

METHODS FOR MANUFACTURING MIM CAPACITOR IN SEMICONDUCTOR DEVICE

1 to 8 are cross-sectional views illustrating a method of manufacturing a MIM capacitor of a semiconductor device according to a preferred embodiment of the present invention.

         <Explanation of symbols for the main parts of the drawings>

10: interlayer insulation film

12: Storage Node Contact Plug

14: etching barrier layer

16: sacrificial insulating film

20: pattern hole

22: sacrificial pattern layer

22a: hemispherical

28: material for the lower electrode

28a: lower electrode

30: dielectric film

32: upper electrode

34: capacitor

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a metal-insulator-metal (MIM) capacitor of a semiconductor device.

In general, analog capacitors applied to CMOS IC logic devices that require high precision are advanced analog MOS technology, especially A / D converters (Analog / Digital converter). Or switching capacitor filters. As such capacitors, various structures such as polysilicon-insulator-polysilicon (PIP), polysilicon-insulator-metal (PIM), metal-insulator-polysilicon (MIP), and metal-insulator-metal (MIM) have been proposed.

Among them, the capacitor having the MIM structure is used as a representative structure of the analog capacitor because of the advantages of low series resistance, low thermal budget and low power supply voltage. Such MIM capacitors have been widely used in semiconductor companies in radio frequency (RF) / mixed signal (MS) devices and DRAM cells.

In general, SiO _2, Si ₃ N ₄ , and the like, which have a relatively simple manufacturing process and are inexpensive, are used as the dielectric film of the MIM capacitor. However, since SiO ₂ or Si ₃ N ₄ has a low dielectric constant and a low capacitance value, it is necessary to increase the area of the capacitor in order to obtain a desired capacitance. In other words, in order to cope with high integration of semiconductor devices, a material having a high dielectric constant is used as the capacitor dielectric film to reduce the area of the capacitor, or instead of using a material having a relatively low permittivity as the dielectric film of the capacitor, the area of the capacitor is increased. Capacitance must be secured.

Recently, as a part of increasing the area of the capacitor of the DRAM device, a concave structure and a cylinder structure have been proposed. However, the cylinder structure is complicated and difficult to manufacture compared to the concave structure. In addition, in order to increase the capacitance within the same area, an electrode must use a material having a high barrier height or a dielectric film having a high dielectric constant to reduce the thickness of the oxide film. Because of this, there is a burden to develop new new materials, and the development is also very difficult. Moreover, even if a new material is developed and applied to the device, the cost of the product is higher than the cost of product development in the device that uses the existing material, thereby lowering the competitiveness.

Capacitors with a concave structure are hole type so that the bottom electrode, the dielectric film and the top electrode are coated even if they are deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) with good step coverage. There is a limit to increasing the properties, and the thickness of each material must be reduced to obtain the desired capacitance.

In addition, since both the concave structure and the cylinder structure have a very small thickness of the storage node which is the lower electrode, when the lower electrode is formed of metal, the solution for wet etching during the subsequent wet etching process is lowered through the lower electrode. The storage node contact plug penetrates the storage node contact plug, which causes the loss of the storage node contact plug. Furthermore, the etch solution penetrated below etches the interlayer insulating film surrounding the storage node contact plug to cause a bridge between the bit line and the capacitor upper electrode or the upper electrode and the contact plug M1C for the first metal wiring M1. Problem occurs.

Accordingly, the present invention has been made to solve the above problems, has the following objects.

First, it is a first object of the present invention to provide a method of manufacturing a MIM capacitor capable of increasing the area of the capacitor to increase the capacitance of the capacitor while minimizing the leakage current characteristics.

In addition, a second object of the present invention is to provide a method of manufacturing a MIM capacitor that can improve the coverage of the lower electrode, the dielectric film and the upper electrode.

In addition, a third object of the present invention is to manufacture a MIM capacitor capable of preventing damage of an interlayer insulating layer, which is a lower layer, by preventing penetration of an etching solution into the lower layer during a wet etching process for removing an oxide layer for a storage node pattern, which is a lower electrode. To provide a method.

In addition, a fourth object of the present invention is to provide a method of manufacturing a MIM capacitor, which can prevent an increase in contact resistance between a storage node and a storage node contact plug by preventing a loss of a storage node contact plug, which is a lower layer of a lower electrode of the capacitor. It is.

According to an aspect of the present invention, there is provided a method of forming an interlayer insulating film having a storage node contact plug interposed on a substrate, forming an etch barrier layer on the interlayer insulating film, and forming an etch barrier. Forming a sacrificial insulating film on the layer, etching the sacrificial insulating film to form a pattern hole in a portion corresponding to the storage node contact plug, and sacrificial along a step of an upper surface of the entire structure including the pattern hole Forming a silicon layer for a pattern layer, etching the silicon layer and the etch barrier layer through an etch back process to expose an upper portion of the storage node contact plug, and performing a metastable polisilicon (MPS) process By growing MPS grain on the surface of the silicon film to form a sacrificial pattern layer for the lower electrode pattern having a hemispherical structure Forming a lower electrode material on the sacrificial pattern layer to fill the pattern hole, removing the sacrificial insulating layer and the sacrificial pattern layer to form a lower electrode having a hemispherical surface; It provides a method of manufacturing a MIM capacitor of a semiconductor device comprising forming a dielectric film along the surface of the lower electrode, and forming an upper electrode to cover the dielectric film.

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DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

1 to 8 are cross-sectional views illustrating a method of manufacturing a MIM capacitor according to a preferred embodiment of the present invention.

First, as shown in FIG. 1, a semiconductor substrate (not shown) having a base layer formed through a series of semiconductor manufacturing processes is prepared. In this case, the underlying layer may include a word line, a junction region, a bit line, a transistor, a landing plug, a storage node contact plug 12, and a plurality of layers. Insulating film 10 and the like.

Subsequently, an etch barrier layer 14 is deposited on the underlayer. In this case, the etching barrier layer 14 is formed using a nitride film-based material. For example, the etching barrier layer 14 is formed of a Si ₃ N ₄ film.

Subsequently, a sacrificial insulating layer 16 for forming a storage node pattern is deposited on the etch barrier layer 14. In this case, the sacrificial insulating layer 16 is formed of an oxide-based material. For example, HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate Glass) film, FSG (FSG) film It is formed from a single layer film made of any one of a fluorinated Silicate glass (CDO) film, a carbon doped oxide (CDO) film, and an organosilicate glass (OSG) film, or they are formed as a laminated film in which at least two or more layers are laminated.

On the other hand, the sacrificial insulating film 16 is deposited to a thickness of 15000 ~ 40000Å.

Subsequently, as shown in FIG. 2, an photoresist film (not shown) is coated on the sacrificial insulating layer 16, followed by exposure and development processes using a photo mask to form an etching mask (not shown).

Subsequently, the etching process 18 using the etching mask is performed to etch the sacrificial insulating layer 16 to form the pattern hole 20 for the storage node pattern. In this case, during the etching process 18, only the sacrificial insulating layer 16 is selectively etched using the etch barrier layer 14 as an etch stop layer.

Subsequently, as shown in FIG. 3, the sacrificial pattern layer 22 for the storage node pattern is formed along the step formed by the pattern hole 20. In this case, the sacrificial pattern layer 22 is formed in a stacked structure of a doped silicon film and an undoped silicon film. The sacrificial pattern layer 22 is formed by a low pressure chemical vapor deposition (LPCVD) method by forming a doped silicon film using SiH ₄ gas and injecting PH ₃ gas therein in-situ thereon. do. At this time, the doped silicon film is formed at 550 ° C. or less, preferably in the range of 300 to 500 ° C., with an amorphous film having a thickness of 30 to 100 kPa, and the undoped silicon film is formed with a thickness of 30 to 200 kPa. Thereby, the total thickness of the whole sacrificial pattern layer 22 is controlled to 60-300 micrometers.

Subsequently, as illustrated in FIG. 4, an etch back process is performed to etch the sacrificial pattern layer 22 and the etch barrier layer 14. As a result, the upper portion of the storage node contact plug 12 is exposed. That is, the sacrificial pattern layer 22 remains only on the inner wall of the pattern hole 20 and all are removed.

Subsequently, as illustrated in FIG. 5, a metastable polisilicon (MPS) process 26 is performed to grow MPS grains on the sacrificial pattern layer 22 remaining on the inner wall of the pattern hole 20 to form a hemispherical shape ( Hemispherical grain (HSG) 22a is formed. At this time, the growth degree of the MPS grain may be appropriately adjusted within a range capable of securing the capacitance according to the purpose of the semiconductor device.

Meanwhile, the MPS process 26 proceeds to a stabilization process, a seed process, and an annealing process.

The stabilization process is a process for stabilizing the inside of the chamber before the seed process, and is separated into a heat-up step and a vent step. First, the heat-up step is a process for gradually increasing the temperature inside the chamber within the temperature range of 550 ~ 700 ℃ 45 to 55 seconds, preferably 50 seconds. The vent step is a process of injecting an inert gas into the chamber after the heat-up is completed for 9 to 11 seconds, preferably 10 seconds.

The seeding process is performed by injecting Si ₂ H ₆ gas at 2 to 20 sccm into the chamber where the stabilization process is completed for 50 to 300 seconds.

The annealing process is carried out for 50 to 400 seconds within the temperature range of 600 ~ 650 ℃ after the seeding process is completed.

Subsequently, as shown in FIG. 6, the lower electrode material 28 is deposited to fill the pattern hole 20. In this case, the lower electrode material 28 is formed of any one metal material selected from a group of metal materials such as TiN, TaN, HfN, ZrN, Ru, RuO ₂ , Pt, Ir, and IrO ₂ .

Subsequently, a chemical mechanical polishing (CMP) process is performed to isolate the lower electrode material 28 in the pattern hole 20.

Subsequently, as shown in FIG. 7, DHF (Diluted HF; HF solution diluted with H ₂ O ₂ at a ratio of 50: 1 or 100: 1) or BOE (Buffered Oxide Etchant; HF and NH ₄ F is 100: The sacrificial insulating film 16 is removed by a cleaning process using 1 or 300: 1 solution.

Subsequently, the sacrificial insulating layer 16 is removed to remove the exposed sacrificial pattern layer 22. In this case, an etching process for removing the sacrificial pattern layer 22 is performed using NH ₄ OH: H ₂ 0 or HF: HNO ₃ , but the mixing ratio of NH ₄ OH: H ₂ 0 is 1: 2 to 1:20. The mixing ratio of HF: HNO ₃ is 1:20. As a result, a lower electrode 28a is formed, which is a storage node of a capacitor having a hemispherical surface.

On the other hand, since the etch barrier layer 14 exists under the sacrificial insulating layer 16 during the cleaning process for removing the sacrificial insulating layer 16, the damage to the storage node contact plug 12 does not occur.

Subsequently, as shown in FIG. 8, the dielectric film 30 is formed along the surface of the lower electrode 28a. At this time, the dielectric film 30 is formed by an ALD (Atomic Layer Deposition) method having good coverage. As the material, Al ₂ O ₃ , ZrO ₂ , HfO ₂ , Ta ₂ O ₅ , and SrTiO ₃ may be formed of any one of dielectric films selected from dielectric films having a dielectric constant of 9 or more, or mixed films thereof. In addition, the dielectric film 30 is deposited to a thickness of 30 to 100 Å.

For example, the case in which the dielectric film 30 is formed by using an Al ₂ O ₃ film by the ALD method will be described below. The deposition process using the ALD method is carried out until the Al ₂ O ₃ film has a thickness of 30 to 100 kPa while maintaining the pressure inside the chamber at 0.1 to 10 Torr and maintaining the temperature at 25 to 500 ° C. Specifically, TMA (Tri Methyl Aluminum, Al (CH ₃ ) ₃ ), which is an aluminum source, is introduced into the chamber for 0.1 to 10 seconds. Then, N ₂ gas, which is an inert gas, is introduced into the chamber for 0.1 to 10 seconds to remove unreacted source gas other than the source gas that forms the atomic layer. Then, the O ₃ gas is introduced into the chamber for 0.1 to 10 seconds to oxidize the atomic layer deposited on the surface of the lower electrode 28a. Then, N ₂ gas is introduced into the chamber for 0.1 to 10 seconds to discharge unreacted O ₃ gas into the chamber.

In order to form an Al ₂ O ₃ film with a desired thickness, the above-described operation, that is, Al deposition-N ₂ purge-O ₃ oxide-N ₂ purge process, is repeated one cycle, and the cycle is repeatedly performed a plurality of times. .

Next, the upper electrode 32 of the capacitor is formed to cover the upper portion of the dielectric film 30. At this time, the upper electrode 32 is the same material as the lower electrode 28a, for example, any one metal material selected from the group of metal materials such as TiN, TaN, HfN, ZrN, Ru, RuO ₂ , Pt, Ir and IrO ₂ To form. Thereby, the capacitor 34 which consists of the lower electrode 28a, the dielectric film 30, and the upper electrode 32 is completed.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, according to the present invention, the lower electrode of the MIM capacitor having a hemispherical shape is formed on the surface to increase the surface area of the lower electrode, thereby increasing the capacitance of the capacitor.

In addition, according to the present invention, as shown in Figure 7, after filling the pattern hole with the lower electrode material to form a lower electrode having a columnar shape by removing the sacrificial insulating film, and then forming the dielectric film and the upper electrode sequentially By doing so, it is possible to solve the coating deterioration problem generated during the manufacturing process of the MIM capacitor having a cylinder and a convex structure of the prior art.

In addition, according to the present invention, the leakage current characteristic can be improved by solving the problem of coating deterioration.

In addition, according to the present invention, as shown in Figure 7, by performing the sacrificial insulating film removal process in the state where the etching barrier layer is located under the sacrificial insulating film, the storage node formed by the etching solution used in the sacrificial insulating film removal process Damage to the contact plug and the interlayer insulating film can be prevented.

In addition, according to the present invention, by minimizing damage to the storage node contact plug, it is possible to prevent a single bit failure due to an increase in contact resistance between the storage node and the storage node contact plug.

In addition, according to the present invention, it is possible to prevent the bridge between the bit line and the capacitor upper electrode or the bridge between the upper electrode and the first metal wiring by minimizing damage to the interlayer insulating film.

Claims (21)

Forming an interlayer insulating film having a storage node contact plug interposed thereon on the substrate; Forming an etch barrier layer on the interlayer insulating film; Forming a sacrificial insulating film on the etch barrier layer; Etching the sacrificial insulating layer to form a pattern hole in a portion corresponding to the storage node contact plug; Forming a silicon film for a sacrificial pattern layer along a step of an upper surface of the entire structure including the pattern hole; The storage node contact plug is etched by etching the silicon layer and the etch barrier layer through an etch back process so that the sacrificial pattern layer for the lower electrode pattern to be formed through a subsequent process does not directly contact the storage node contact plug. Exposure Forming a sacrificial pattern layer for the lower electrode pattern having a hemispherical structure by growing MPS grains on a surface of the silicon film by performing a metastable polisilicon (MPS) process; Forming a material for a lower electrode on the sacrificial pattern layer to fill the pattern hole; Removing the sacrificial insulating layer and the sacrificial pattern layer to form a lower electrode having a hemispherical surface; Forming a dielectric film along the surface of the lower electrode; And Forming an upper electrode to cover the dielectric layer MIM capacitor manufacturing method of a semiconductor device comprising a. delete The method of claim 1, The sacrificial pattern layer is a semiconductor device MIM capacitor manufacturing method of forming a laminated structure of a undoped silicon film. The method of claim 3, wherein The doped silicon film is a MIM capacitor manufacturing method of a semiconductor device to form an amorphous film with a thickness of 30 ~ 100 ~ within a range of 300 ~ 500 ℃. The method of claim 4, wherein The undoped silicon film is a MIM capacitor manufacturing method of a semiconductor device to form a thickness of 30 ~ 200 ~ by performing the deposition process in-situ and the doped silicon film deposition process. delete The method of claim 1, The MPS process is a method of manufacturing a MIM capacitor of a semiconductor device comprising the step of performing a seed process using a Si ₂ H ₆ gas. The method of claim 7, wherein The seed step is a MIM capacitor manufacturing method of a semiconductor device performed at a temperature of 550 ~ 700 ℃. The method of claim 8, The seed process is a method of manufacturing a MIM capacitor of a semiconductor device is carried out for 50 to 300 seconds by injecting the Si ₂ H ₆ gas at 2 ~ 20sccm. The method according to any one of claims 7 to 9, The MPS process further comprises the step of performing an annealing process for 50 to 400 seconds within a temperature range of 600 ~ 650 ℃. The method of claim 10, The MPS process further comprises the step of performing a stabilization process to stabilize the inside of the chamber before the seed process. The method of claim 11, wherein the stabilization process, Gradually increasing the temperature inside the chamber within a temperature range of 550 to 700 ° C. for 45 to 55 seconds; And Injecting an inert gas into the chamber to maintain for 9 ~ 11 seconds MIM capacitor manufacturing method of a semiconductor device comprising a. delete The method of claim 1, The sacrificial insulating layer is formed of an oxide film-based material, the etching barrier layer is formed of a nitride film-based material MIM capacitor manufacturing method of a semiconductor device. The method of claim 1, The cleaning process for removing the sacrificial insulating film is a method of manufacturing a MIM capacitor of a semiconductor device by selectively etching only the sacrificial insulating film using the etch barrier layer as an etch stop layer. The method of claim 15, The cleaning step is a method of forming a MIM capacitor of a semiconductor device performed using a DHF solution or a BOE solution. The method of claim 1, The etching process for removing the sacrificial pattern layer is a method of manufacturing a MIM capacitor of a semiconductor device performed using NH ₄ OH: H ₂ 0 or HF: HNO ₃ . The method of claim 17, The mixing ratio of the NH ₄ OH: H ₂ 0 is 1: 2 to 1:20, and the mixing ratio of the HF: HNO ₃ is 1:20 method of manufacturing a MIM capacitor of a semiconductor device. The method of claim 1, The lower electrode material and the upper electrode are MIM capacitors of a semiconductor device formed of any one metal material selected from a group of metal materials such as TiN, TaN, HfN, ZrN, Ru, RuO ₂ , Pt, Ir, and IrO _2. Manufacturing method. The method of claim 1, MIM capacitor of a semiconductor device formed in the dielectric film _{Al 2 O 3, ZrO 2,} HfO 2 and Ta ₂ O _5, either one of the dielectric film or a mixed film mixing these selected ones of the dielectric film has a dielectric constant 9 or more, such as SrTiO ₃ Preparation Way. The method of claim 20, The dielectric film is a method of manufacturing a MIM capacitor of a semiconductor device formed by the ALD method.

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