KR100701768B1 - Cmos image sensor - Google Patents

Abstract

A CMOS image sensor is provided to enhance considerably a fill-factor, to restrain the generation of failures, and to reduce the area of a unit pixel. A CMOS image sensor comprises a plurality of unit pixels and a drive transistor. The plurality of unit pixels include a photodiode, a select transistor for transferring the electric charge stored in the photodiode, and a reset transistor for resetting the photodiode via the select transistor, respectively. The drive transistor is connected with the plurality of unit pixels, so that the electric charge transferred from the select transistor of each unit pixel is applied to a gate of the drive transistor.

Description

CMOS image sensor {CMOS IMAGE SENSOR}

1 is a configuration diagram showing the configuration of a general CMOS image sensor.

Fig. 2 is a circuit diagram showing the configuration of unit pixels having a 3-T structure of a general CMOS image sensor.

3 is a circuit diagram illustrating a pixel array in which a plurality of unit pixels illustrated in FIG. 2 is formed.

4 is a circuit diagram showing the configuration of unit pixels having a 4-T structure of a general CMOS image sensor.

FIG. 5 is a circuit diagram illustrating a pixel array including a plurality of unit pixels illustrated in FIG. 4.

6 is a waveform diagram illustrating the operation characteristics of the drive transistor Dx shown in FIGS. 2 and 4.

FIG. 7 is a circuit diagram showing the configuration of a unit pixel having a 2-T structure according to Embodiment 1 of the present invention; FIG.

8 is a plan view of a unit pixel shown in FIG. 7;

FIG. 9 is a circuit diagram illustrating a pixel array including a plurality of unit pixels illustrated in FIG. 7. FIG.

FIG. 10 is a circuit diagram showing a configuration of unit pixels having a 3-T structure according to Embodiment 2 of the present invention. FIG.

11 is a plan view of a unit pixel illustrated in FIG. 10;

FIG. 12 is a circuit diagram illustrating a pixel array including a plurality of unit pixels illustrated in FIG. 10. FIG.

FIG. 13 is a plan view illustrating another structure of the unit pixel illustrated in FIG. 10.

<Explanation of symbols for the main parts of the drawings>

10: pixel array

20: to decoder

30: column decoder

TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a Complementary Metal Oxide Semiconductor (CMOS) image sensor.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

The camera module basically includes an image sensor. In general, an image sensor refers to a device that converts an optical image into an electrical signal. As such an image sensor, a charge coupled device (hereinafter referred to as a CCD) and a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor are widely used.

CCD has a complicated driving method, high power consumption, complicated process due to the large number of mask processes in the manufacturing process, and it is difficult to realize a signal processing circuit in a chip, making it difficult to make one chip. There are disadvantages. In contrast, CMOS image sensors are receiving more attention recently because of the monolithic integration of control, drive, and signal processing circuitry on a single chip. In addition, CMOS image sensors offer potentially lower cost than conventional CCDs due to low voltage operation and low power consumption, compatibility with peripherals, and the availability of standard CMOS fabrication processes.

However, analog signals generated by light receiving elements, such as photo diodes, in CMOS image sensors have various parasitic effects caused by parasitic capacitance, resistance, dark current leakage, or mismatch of semiconductor device characteristics. Such a parasitic effect is essentially generated in a semiconductor device, resulting in a decrease in the signal to noise ratio of the image data. Therefore, noise is an important factor limiting the performance of the CMOS image sensor.

Noise in the CMOS image sensor is caused by kT / C noise related to the sampling of the image data, 1 / f noise associated with the circuit used to amplify the image signal, and fixed by the mismatch of the signal processing circuit of the sensor. Patterned Pattern Noise (hereinafter referred to as FPN). Dual FPNs are not very good visually because they appear as vertical lines or strips in the image and are easily found in the human eye.

1 is a diagram illustrating a CMOS image sensor having a unit pixel having a square shape.

As shown in FIG. 1, when a row address is designated around the pixel array 10, a row decoder 20 is disposed in one direction of the pixel array 10, and is positioned at a right angle thereof. The data output of the pixel is connected to, and a column decoder 30 for designating a column address of the pixels is disposed.

A process of reading data from a CMOS image sensor having such a configuration will be described below.

First, the first column is selected by the row decoder 20, and then data of each pixel of the first column selected by the column decoder 30 is read, and then the data of each pixel is amplified. Next, the second column is selected by the row decoder 20, and then data for each pixel of the second column selected by the column decoder 30 is read and then amplified. In this manner, data of all pixels is read.

There are many types of unit pixels used in CMOS image sensor, but among them, the typical commercially available pixel type is 3-T (3-transistor) composed of three basic transistors and one photodiode. There is a 4-T (4-transistor) structure pixel composed of a pixel of the structure, four basic transistors, and a photodiode.

FIG. 2 is a circuit diagram illustrating a general 3-T structure among the CMOS image sensor unit pixels.

Referring to FIG. 2, a 3-T pixel includes one photodiode PD for converting and storing photon into electrons and three NMOS transistors. The three NMOS transistors are configured as a source follower by operating the reset transistor Rx for resetting one end of the photodiode PD to the power supply voltage VDD and the charge accumulated in the photodiode PD. The drive transistor Dx serves as a buffer amplifier, and the select transistor Sx allows addressing by switching.

4 is a circuit diagram illustrating a general 4-T structure among the CMOS image sensor unit pixels.

Referring to FIG. 4, a 4-T pixel includes one photodiode PD and four NMOS transistors. The four NMOS transistors have a transfer transistor Tx for transporting the photo-generated charges concentrated in the photodiode PD to the floating diffusion region FD, and the floating diffusion region FD to a desired value. A reset transistor Rx for setting the potential and discharging the charge to reset the floating diffusion region FD, and a drive transistor acting as a buffer amplifier in a source follower configuration by operating according to the accumulated charge in the floating diffusion region FD. (Dx), it consists of a select transistor (Sx) which enables addressing by switching.

As described above, the greatest difference in the circuit configuration between the pixels of the 3-T structure and the pixels of the 4-T structure is the presence or absence of the transfer transistor Tx and the floating diffusion region. The pixel of the 3-T structure first detects the signal level and then turns on the reset transistor Rx to detect the reset level. On the other hand, the pixel of the 4-T structure turns on the reset transistor Rx to detect the reset level first, and then turns on the transfer transistor Tx to detect the signal level.

3 is a circuit diagram illustrating a pixel array in which pixels of the 3-T structure shown in FIG. 2 share one column line. As illustrated in FIG. 3, each unit pixel UP1 to UPn is connected to one column line in common and is connected to one load transistor Load.

FIG. 5 is a circuit diagram illustrating a pixel array in which pixels of the 4-T structure illustrated in FIG. 4 share one column line. As shown in FIG. 5, each unit pixel UP1 to UPn is connected to one column line in common and is connected to one load transistor Load.

As shown in FIGS. 3 and 5, the pixels of the 3-T structure and the 4-T structure are configured such that a plurality of pixels share one column line and are connected to one load transistor through the column line. As shown in FIG. 1, a signal is read and output for each column line.

On the other hand, each pixel independently configures the drive transistor Dx, and the drive transistor Dx has the characteristics as shown in FIG. Referring to FIG. 6, the drive transistor Dx increases the overall voltage swing by changing the output voltage flowing from the photodiode PD to the gate input.

However, in the CMOS image sensor according to the related art, since the drive transistor Dx is independently configured for each unit pixel, there is a limit in improving the fill factor. In addition, a failure due to an internal interconnection process for forming a separate contact for connecting the gate electrode of the drive transistor Dx occurs. In addition, by increasing the area of the entire pixel it acts as a factor to inhibit high integration.

Accordingly, the present invention has been made to solve the above problems of the prior art, has the following objects.

First, an object of the present invention is to provide a CMOS image sensor that can greatly improve the fill factor.

In addition, another object of the present invention is to provide a CMOS image sensor capable of minimizing the number of drive transistors of pixels connected per column line to minimize defects that may occur during a drive transistor forming process.

Another object of the present invention is to provide a CMOS image sensor capable of minimizing a defect due to an internal connection process for forming a separate contact for connecting a gate electrode of a drive transistor.

In addition, another object of the present invention is to provide a CMOS image sensor capable of highly integrated a device by minimizing an area of a unit pixel.

According to an aspect of the present invention, there is provided a photodiode, a select transistor configured to transport charges selected during a signal readout period and accumulated in the photodiode, and the photodiode via the select transistor. A plurality of unit pixels each composed of reset transistors for resetting; And a drive transistor connected to the plurality of unit pixels in common, and having a charge transferred by a select transistor of each unit pixel applied to a gate thereof.

According to another aspect of the present invention, there is provided a photodiode, a transfer transistor for transferring charges accumulated in the photodiode to a floating diffusion region, and a photodiode and the transfer transistor. A plurality of unit pixels each comprising a reset transistor for resetting the floating diffusion region together and a select transistor for carrying charges accumulated in the floating diffusion region; And a drive transistor connected to the plurality of unit pixels in common, and having a charge transferred by a select transistor of each unit pixel applied to a gate thereof.

According to still another aspect of the present invention, there is provided a pixel array configured to share a plurality of pixels in common with one column line, and data of the plurality of pixels output through the column line. And a drive transistor for amplifying and outputting the pixel, wherein the pixel comprises a photodiode, a select transistor for carrying charges accumulated in the photodiode, and a reset transistor for resetting the photodiode via the select transistor. Provide an image sensor.

According to still another aspect of the present invention, there is provided a pixel array configured to share a plurality of pixels in common with one column line, and data of the plurality of pixels output through the column line. And a drive transistor for amplifying and outputting the pixel, wherein the pixel includes a photodiode, a transfer transistor for transporting charges accumulated in the photodiode to a floating diffusion region, the photodiode, and the floating transistor via the transfer transistor. A CMOS image sensor comprising a reset transistor for resetting the diffusion region together and a select transistor for carrying charge accumulated in the floating diffusion region.

According to still another aspect of the present invention, there is provided a pixel array configured to share a plurality of pixels in common with one column line, and data of the plurality of pixels output through the column line. And a drive transistor for amplifying and outputting the pixel, wherein the pixel includes a photodiode having a rectangular structure, an active region protruding from an upper right side of the photodiode, and a region crossing the region where the active region and the photodiode contact each other. The present invention provides a CMOS image sensor including a gate electrode of a select transistor formed to overlap and a gate electrode of a reset transistor formed to overlap the active region at a predetermined interval from the gate electrode of the select transistor.

According to still another aspect of the present invention, there is provided a pixel array configured to share a plurality of pixels in common with one column line, and data of the plurality of pixels output through the column line. And a drive transistor for amplifying and outputting the pixel, wherein the pixel includes a photodiode having a rectangular structure, a first active region protruding to the lower right side of the photodiode, and a photodiode formed on the photodiode. A second active region, a gate electrode of a transfer transistor formed at a center portion of the photodiode, a floating diffusion region formed inside the gate electrode of the transfer transistor so as to be separated from the photodiode by a gate electrode of the transfer transistor; Formed under the photodiode A gate electrode of a reset transistor formed to overlap a region crossing the first active region and the photodiode, and a gate electrode of the select transistor formed to cross the second active region formed on the photodiode And a metal wiring connecting the second active region and the floating diffusion region.

According to still another aspect of the present invention, there is provided a pixel array configured to share a plurality of pixels in common with one column line, and data of the plurality of pixels output through the column line. And a drive transistor for amplifying and outputting the pixel, wherein the pixel includes a photodiode having a rectangular structure, a first active region protruding to the lower right side of the photodiode, and a photodiode formed on the photodiode. A second active region, a gate electrode of a transfer transistor formed in an inverted 'c' or 'c' shape at a central portion of the photodiode, and a field region formed to cover an opening of a gate electrode of the transfer transistor in the photodiode And between the gate electrode and the field region of the transfer transistor. A floating diffusion region formed therein, a gate electrode of a reset transistor formed to overlap a region crossing the first active region formed in the lower portion of the photodiode and a region in which the photodiode is in contact with the photodiode; A CMOS image sensor includes a gate electrode of a select transistor formed to cross an active region, and a metal wiring connecting the second active region and the floating diffusion region.

According to still another aspect of the present invention, there is provided a pixel array configured to share a plurality of pixels in common with one column line, and data of the plurality of pixels output through the column line. And a drive transistor for amplifying and outputting the pixel, wherein the pixel includes a photodiode having a rectangular structure, a first active region protruding to the lower right side of the photodiode, and a photodiode separated from an upper portion of the photodiode. A second active region formed at the upper portion of the photodiode, a gate electrode of a transfer transistor formed in an inverted 'a' or 'a' shape at a central portion of the photodiode, and an opening of the gate electrode of the transfer transistor within the photodiode; Formed in an inverted 'L' or 'L' shape that is symmetrical with the gate electrode of the transfer transistor A field region, a floating diffusion region formed between the gate electrode of the transfer transistor and the field region, and a region overlapping the first active region formed below the photodiode and a region where the photodiode is in contact with each other; A gate electrode of a reset transistor, a gate electrode of a select transistor formed to cross the second active region formed on the photodiode, and a metal wiring connecting the second active region and the floating diffusion region; Provides CMOS image sensor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals throughout the specification represent the same elements performing the same function.

Example 1

7 and 8 are circuit diagrams and plan views illustrating a unit pixel having a 2-T structure in order to explain a configuration of a unit pixel of a CMOS image sensor according to Embodiment 1 of the present invention.

7 and 8, the unit pixel UP of the CMOS image sensor according to the first exemplary embodiment of the present invention includes one photodiode PD for converting light into electrons and two NMOS transistors. have. The two NMOS transistors include a reset transistor Rx for resetting one end of the photodiode PD to the power supply voltage VDD, and a select transistor Sx for transferring charge accumulated in the photodiode PD to the addressing switching element. . Although not shown, a pixel array including a plurality of unit pixels U P shares one column line, which is connected to one drive transistor Dx and one load transistor Load. Therefore, the plurality of unit pixels UP are commonly connected to one drive transistor Dx.

First, during the reset readout period, the reset transistor Rx and the select transistor Sx are simultaneously turned on to reset one end of the photodiode PD to the power supply voltage VDD. In this case, the select transistor Sx may be designed as a native transistor in order to minimize the influence on the reset operation through the reset transistor Rx. Thereafter, during the signal readout period, the charge accumulated in the photodiode PD is selected through the select transistor Sx through the select transistor Sx by selecting the select transistor Sx while the reset transistor Rx is turned off. Output to the gate of). Therefore, the select transistor Sx transfers the charge accumulated in the photodiode PD while addressing at the time of selection.

As shown in FIG. 9, the drive transistor Dx serving as a buffer amplifier in the source follower configuration is not configured for each unit pixel, but is configured for each column line connected to a plurality of unit pixels to form the corresponding column line. All shared pixels are shared in common. In this case, even when one drive transistor Dx is allocated to each column line, row selection is possible through the select transistor Sx, and thus data reading may be performed in the same manner as in the prior art illustrated in FIG. 3. .

The CMOS image sensor according to the first exemplary embodiment of the present invention having the above configuration includes three NMOS transistors Rx, Dx, and Sx shown in FIG. 3 as the unit pixel is implemented by only two NMOS transistors Rx and Sx. Compared to the CMOS image sensor according to the prior art made can significantly improve the fill factor, thereby improving the dynamic range (Signal / Noise Ratio, SNR). In addition, as shown in FIG. 8, since the drive transistor Dx is not configured in the pixel, the number of contacts CT formed in the unit pixel is also four (two active region contacts and one for the gate electrode of the reset transistor). Can be reduced to a single gate electrode contact of a select transistor), thereby reducing the bad pixel fail ratio due to a defect that may occur during an interconnection process for forming a contact CT. Can be reduced. In addition, the size of the pixel array may be reduced over the entire surface, thereby reducing the overall chip size. In addition, a contact for connecting the gate electrode of the photodiode PD and the drive transistor Dx is conventionally present in the photodiode PD, so that the photodiode PD is formed during an etching process (plasma etching process) for forming a contact. Has been damaged to reduce the dark current characteristics, but this cause can be completely isolated.

Meanwhile, the structure of the pixel illustrated in FIG. 8 will be described in a direction viewed from above.

The pixel structure shown in FIG. 8 has an active region protruding from the upper right side of the rectangular photodiode PD, and the active region is formed in a '-' ring shape. In the active region, the gate electrode Sx Gate of the select transistor Sx is overlapped in the crossing direction. In addition, the gate electrode Rx Gate of the reset transistor Rx is formed in a direction parallel to the gate electrode Sx Gate so as to be spaced apart from the gate electrode Sx Gate at a predetermined interval and overlap in a direction crossing the active region. A contact CT is formed at an end of the active region to be connected to the power supply voltage source VDD, and a contact is connected to the gate electrode of the drive transistor Dx at an active region between the gate electrodes Sx Gate and Rx Gate. CT (Sx out) is formed.

Example 2

10 and 11 are circuit diagrams and plan views illustrating a unit pixel having a 4-T structure in order to explain a configuration of a unit pixel of a CMOS image sensor according to Embodiment 2 of the present invention.

10 and 11, the unit pixel UP of the CMOS image sensor according to the second exemplary embodiment of the present invention does not include the drive transistor Dx in the pixel, as in the technical spirit of the first exemplary embodiment of the present invention. Rather, one for each column line connected to a plurality of pixels.

That is, the unit pixel of the CMOS image sensor according to the second embodiment of the present invention includes one photodiode PD for converting light into electrons and three NMOS transistors for controlling the transport of electric charges of the photodiode PD. Consists of. The three NMOS transistors have a transfer transistor Tx for transporting the concentrated photocharges from the photodiode PD to the floating diffusion region FD, and sets the potential of the floating diffusion region FD to a desired value and charges them. And a reset transistor Rx for resetting the floating diffusion region FD and a select transistor Sx for addressing by switching.

First, during the reset readout period, the reset transistor Rx and the transfer transistor Tx are simultaneously turned on to reset one end of the photodiode PD and the floating diffusion region FD to the power supply voltage VDD. Subsequently, only the reset transistor Rx is turned off during the signal read period to transfer charges generated in the photodiode PD to the floating diffusion region FD through the transfer transistor Tx. Then, the select transistor Sx is turned on to output charges accumulated in the floating diffusion region FD to the gate of the drive transistor Dx.

As shown in FIG. 12, the drive transistor Dx serving as a buffer amplifier in the source follower configuration is not configured for each unit pixel, but is configured for each column line connected to a plurality of unit pixels to form the corresponding column line. All shared pixels are shared in common. As such, even when one drive transistor Dx is assigned to each column line, row selection is possible through the select transistor Sx, and thus data reading is possible as in the prior art illustrated in FIG. 5. Do.

The CMOS image sensor according to the second exemplary embodiment of the present invention having such a configuration implements a unit pixel using only three NMOS transistors Rx, Tx, and Sx, and thus four NMOS transistors Rx and Tx as shown in FIG. 5. , Dx, Sx) can significantly improve the fill factor compared to the CMOS image sensor according to the prior art, through which the dynamic range and the signal-to-noise ratio can be improved. In addition, the chip size may be reduced as the pixel size is reduced. In addition, as illustrated in FIG. 11, since the layout of adjacent pixels is completely symmetrical (or isotropic), crosstalk degradation by colors may be improved. In addition, since the photoelectrons are introduced into the center floating diffusion region FD in the 4-direction (east-south, north-south) of the photodiode PD when the transfer transistor Tx is turned on, transport characteristics may be improved. In addition, the capacitance of the floating diffusion region FD can be adjusted only by changing a mask for forming the gate electrode Tx gate of the transistor Tx, thereby allowing charge sharing. It is easy to solve the phenomenon.

Meanwhile, the structure of the pixel illustrated in FIG. 11 will be described in the direction viewed from above.

The pixel structure shown in FIG. 11 has a first active region protruding from the lower left side of the rectangular photodiode PD, and the first active region is formed in a ring shape bent at right angles, such as 'b'. In addition, a second active region is formed on the photodiode PD so as to be separated from the photodiode PD. In addition, a region where the photodiode PD and the first active region are in contact with each other is overlapped in a direction crossing the gate electrode Rx of the reset transistor Rx, and a gate electrode of the select transistor Sx is disposed in the second active region. Sx Gate) overlap in the direction crossing. In addition, the gate electrode Tx Gate of the transfer transistor Tx overlaps the center portion of the photodiode PD, and the floating diffusion region FD is formed in the center portion of the gate electrode Tx Gate. In addition, a contact CT is formed at one side of each of the floating diffusion region FD and the second active region to be connected to the metal wiring M1, and a power supply voltage source VDD and a termination portion of the first active region are formed. A contact CT for connecting is formed, and a contact CT for inputting a bias is formed at an end of the gate electrode Rx Gate of the reset transistor Rx. Although not shown, a contact is formed in the gate electrode Tx Gate of the transfer transistor Tx to receive a bias for controlling the operation.

Hereinafter, another example of the unit pixel structure of the CMOS image sensor according to the second embodiment of the present invention described above will be described with reference to FIG. 13. Here, only the photodiode (PD) region is shown for convenience of description. The other structure is the same as that of FIG.

First, as shown in FIG. 13A, the gate electrode Tx Gate of the transfer transistor Tx is formed in an inverted 'c' shape, and a portion of the inverted 'c' that is open is a field region ( It is closed by a field oxide film of a field) or an element isolation film of a shallow trench isolation (STI) structure. A floating diffusion region FD is formed between the field region and the gate electrode Tx gate. Of course, in addition to the inverted 'c' shape, 'c' shaped gate electrode (Tx Gate) is also possible.

In addition, as shown in FIG. 13B, the field region has a 'c' shape, and an open portion has a structure of closing with a gate electrode Tx gate of the transfer transistor Tx. In addition, a floating diffusion region FD is formed between the gate electrode Tx Gate and the field region.

In addition, as shown in FIG. 13C, the field region has a shape in which the field region is bent at right angles such as 'b', and the gate electrode Tx Gate of the transfer transistor Tx is 'a'. Like the ruler, the ends are bent at right angles, and end portions thereof overlap each other to be symmetrical to each other. A floating diffusion region FD is formed therein. Of course, the reverse structure is also possible. That is, the field area (Field) has a shape bent at right angles, such as the letter 'b', the gate electrode (Tx Gate) has a shape bent at a right angle, such as the letter 'b' and the ends overlap each other so as to be symmetrical to each other It may be formed.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, the present invention can greatly improve the fill factor to improve the dynamic range and the signal-to-noise ratio.

In addition, the present invention can reduce the bad pixel fail ratio due to a defect that may occur during the internal connection process for forming a contact by reducing the number of contacts per unit pixel of the 3-T structure.

In addition, the present invention can reduce the size of the pixel array to reduce the overall chip size.

In addition, in the case of the 3-T structure, the present invention does not need to form a contact in the photodiode region, thereby preventing damage to the photodiode region, thereby improving dark current characteristics.

In addition, in the case of the 4-T structure, when the transfer transistor is turned on, photoelectrons may be introduced into the floating diffusion region in the 4-direction of the photodiode to improve electron transport characteristics.

In addition, the present invention can control the capacitance of the floating diffusion region, it is easy to solve the charge distribution phenomenon.

Claims (35)

A plurality of unit pixels each consisting of a photodiode, a select transistor selected during a signal readout period to carry charge accumulated in the photodiode, and a reset transistor for resetting the photodiode via the select transistor; And A drive transistor connected in common with the plurality of unit pixels so that charges transferred by the select transistors of the respective unit pixels are applied to a gate; CMOS image sensor comprising a. The method of claim 1, And the select transistor is turned on together with the reset transistor during the period of resetting the photodiode to connect the reset transistor and the photodiode. The method according to claim 1 or 2, And the select transistor is operated during a period in which the reset transistor is turned off to transport charge accumulated in the photodiode to transport charge accumulated in the photodiode. delete delete delete A pixel array configured to allow a plurality of pixels to share one column line in common; And A drive transistor for amplifying and outputting data of the plurality of pixels output through the column line, The pixel, Photo diodes; A select transistor for transporting charges accumulated in the photodiode; And A reset transistor for resetting the photodiode via the select transistor CMOS image sensor comprising a. The method of claim 7, wherein And the select transistor is turned on together with the reset transistor during the period of resetting the photodiode to connect the reset transistor and the photodiode. The method of claim 8, And the select transistor is operated during a period in which the reset transistor is turned off to transport charge accumulated in the photodiode to transport charge accumulated in the photodiode. A pixel array configured to allow a plurality of pixels to share one column line in common; And A drive transistor for amplifying and outputting data of the plurality of pixels output through the column line, The pixel, Photo diodes; A transfer transistor for transferring charge accumulated in the photodiode to a floating diffusion region; A reset transistor for resetting together the photodiode and the floating diffusion region via the transfer transistor; And Select transistors that carry charges accumulated in the floating diffusion region CMOS image sensor comprising a. The method of claim 10, And the transfer transistor is turned on together with the reset transistor during the period of resetting the photodiode to connect the reset transistor and the floating diffusion region. The method of claim 11, The transfer transistor is operated during a period in which the reset transistor is turned off to transport charge accumulated in the photodiode to the floating diffusion region, thereby transferring a charge accumulated in the photodiode to the floating diffusion region. sensor. A pixel array configured to allow a plurality of pixels to share one column line in common; And A drive transistor for amplifying and outputting data of the plurality of pixels output through the column line, The pixel, Photodiodes having a rectangular structure; An active region protruding from one corner of the photodiode; A gate electrode of the select transistor formed to overlap the region where the active region and the photodiode are in contact with each other; And A gate electrode of the reset transistor spaced apart from the gate electrode of the select transistor at a predetermined interval so as to overlap the active region CMOS image sensor comprising a. The method of claim 13, The active area is a CMOS image sensor formed in a shape bent at a right angle, such as 'ㄱ'. The method of claim 14, And a gate contact of the reset transistor and a gate electrode of the select transistor each having a first contact for connecting a wiring to which a bias is input. The method of claim 15, A second image sensor is formed at an end of the active region, and a second contact is formed to be connected to a power supply voltage source, and a third contact is formed between the gate electrode of the reset transistor and the gate electrode of the select transistor. . A pixel array configured to allow a plurality of pixels to share one column line in common; And A drive transistor for amplifying and outputting data of the plurality of pixels output through the column line, The pixel, A photodiode having a rectangular ring structure except for a center portion; A first active region formed to protrude toward one side of the photodiode; A second active region separated from the photodiode and formed on the other side corresponding to one side of the photodiode; A gate electrode of a transfer transistor formed to overlap a central portion between the photodiodes; A floating diffusion region formed in the center portion to be separated from the photodiode by a gate electrode of the transfer transistor; A gate electrode of a reset transistor formed to overlap a direction crossing the region where the first active region and the photodiode are in contact with each other; A gate electrode of the select transistor formed to cross the second active region; And A metal wiring connecting the second active region and the floating diffusion region CMOS image sensor comprising a. The method of claim 17, The first active area is a CMOS image sensor formed in a shape bent at a right angle, such as 'L'. The method of claim 18, And a gate electrode of the reset transistor having a first contact formed therein for connecting with a wire to which a bias is input. The method of claim 19, The gate electrode of the select transistor is integrally formed with the same material as the bias input wiring CMOS sensor. The method of claim 20, And a second contact formed at an end of the first active region to be connected to a power supply voltage source. The method of claim 21, And a third contact formed at one end of the second active area to be connected to the metal wire, and a fourth contact formed at the other end of the second active area to be connected to the output terminal. The method of claim 22, And a fifth contact formed in the floating diffusion region, the fifth contact being connected to the third contact through the metallization. A pixel array configured to allow a plurality of pixels to share one column line in common; And A drive transistor for amplifying and outputting data of the plurality of pixels output through the column line, The pixel, A photodiode having a rectangular ring structure except for a center portion; A first active region protruding to one side of the photodiode; A second active region separated from the photodiode and formed on the other side corresponding to one side of the photodiode; A gate electrode of a transfer transistor formed in a single open shape having an inverse 'c' or 'c' rule and a planar opening in a central portion of the photodiode; A field region formed in the photodiode to block an opening of a gate electrode of the transfer transistor; A floating diffusion region formed between the gate electrode and the field region of the transfer transistor; A gate electrode of a reset transistor formed to overlap a direction crossing the region where the first active region and the photodiode are in contact with each other; A gate electrode of the select transistor formed to cross the second active region; And A metal wiring connecting the second active region and the floating diffusion region CMOS image sensor comprising a. The method of claim 24, And a gate electrode of the reset transistor having a first contact formed therein for connecting with a wire to which a bias is input. The method of claim 25, The gate electrode of the select transistor is integrally formed with the same material as the bias input wiring CMOS sensor. The method of claim 26, And a second contact formed at an end of the first active region to be connected to a power supply voltage source. The method of claim 27, And a third contact formed at one end of the second active area to be connected to the metal wire, and a fourth contact formed at the other end of the second active area to be connected to the output terminal. The method of claim 28, And a fifth contact formed in the floating diffusion region, the fifth contact being connected to the third contact through the metallization. A pixel array configured to allow a plurality of pixels to share one column line in common; And A drive transistor for amplifying and outputting data of the plurality of pixels output through the column line, The pixel, A photodiode having a rectangular ring structure except for a center portion; A first active region protruding to one side of the photodiode; A second active region separated from the photodiode and formed on the other side corresponding to one side of the photodiode; A gate electrode of the transfer transistor formed in a center shape between the photodiodes and bent at right angles, such as an inverted 'a' or 'a'; A field region formed at a right angle, such as an inverted 'L' or 'L', which is symmetrical with the gate electrode of the transfer transistor so as to cover an opening of the gate electrode of the transfer transistor in a center portion between the photodiodes; A floating diffusion region formed between a gate electrode of the transfer transistor and the field region at a center portion between the photodiodes; A floating diffusion region formed between the gate electrode and the field region of the transfer transistor in the central portion; A gate electrode of a reset transistor formed to overlap a direction crossing the region where the first active region and the photodiode are in contact with each other; A gate electrode of the select transistor formed to cross the second active region; And A metal wiring connecting the second active region and the floating diffusion region CMOS image sensor comprising a. The method of claim 30, And a gate electrode of the reset transistor having a first contact formed therein for connecting with a wire to which a bias is input. The method of claim 31, wherein The gate electrode of the select transistor is integrally formed with the same material as the bias input wiring CMOS sensor. The method of claim 32, And a second contact formed at an end of the first active region to be connected to a power supply voltage source. The method of claim 33, wherein And a third contact formed at one end of the second active area to be connected to the metal wire, and a fourth contact formed at the other end of the second active area to be connected to the output terminal. The method of claim 34, wherein And a fifth contact formed in the floating diffusion region, the fifth contact being connected to the third contact through the metallization.

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