KR100699057B1 - Light emitting device and method therefor - Google Patents

Abstract

A light emitting diode and a method for manufacturing the same are provided to reduce the density of crystal defects of a semiconductor layer by using a potential diffusion protection layer. A buffer layer(120) is formed on a substrate(110). A first semiconductor layer(130) is formed on the buffer layer. An active layer(150) is formed on the first semiconductor layer. A second semiconductor layer(160) is formed on the active layer. A potential diffusion protection layer(140) is formed to contain the first semiconductor layer or the second semiconductor layer. The potential diffusion protection layer is stacked sequentially and repeatedly in an AlxGaPN layer and a GaPN layer.

Description

Light emitting device and manufacturing method thereof {LIGHT EMITTING DEVICE AND METHOD THEREFOR}

1 is a view showing a part of a light emitting device according to the present invention;

2 is a view showing a potential diffusion prevention layer according to the present invention;

3 is a view showing an embodiment of a light emitting device according to the present invention;

4 is a view showing a method of manufacturing a light emitting device according to the present invention.

<Brief Description of Major Codes in Drawings>

100: light emitting cell 110: substrate

120: buffer layer 130: first semiconductor layer

140: potential diffusion prevention layer 150: active layer

160: second semiconductor layer

The present invention relates to a light emitting device, and more particularly, to a light emitting device having a structure capable of improving the luminous efficiency and a manufacturing method thereof.

 In general, nitrides of Group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition energy band structure. As a lot of attention. In particular, blue and green light emitting devices using gallium nitride (GaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

The nitride semiconductor layer of the group III element is a metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE) on a heterogeneous substrate such as sapphire or silicon carbide (SiC) having a hexagonal structure Grown through the process. However, when a nitride semiconductor layer of a group III element is formed on a dissimilar substrate, cracks or warpage occur in the semiconductor layer due to a difference in lattice constant and thermal expansion coefficient between the semiconductor layer and the substrate, Dislocations are created. Cracks, distortions and dislocations in the semiconductor layer deteriorate the characteristics of the light emitting element.

In order to solve this problem, conventionally, a technique of Lateral Epitaxial Overgrowth (LEO), in which a semiconductor layer is grown in a lateral direction, has been used. In this method, gallium nitride is grown on a substrate by MOCVD (organic metal chemical vapor deposition) or the like, and then the growth inhibition layer is formed into a stripe through a photo process. Then, when gallium nitride is grown again, gallium nitride grows vertically from the substrate opened by the photo process and also grows laterally. However, there is a problem that the dislocation density decreases only in the portion where the growth inhibition layer of the stripe type is formed.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a light emitting device having a dislocation diffusion prevention layer in order to reduce the crystal defect density of a semiconductor layer.

Another object of the present invention is to provide a method of manufacturing a light emitting device having a dislocation diffusion prevention layer in order to reduce the crystal defect density of a semiconductor layer.

In order to achieve the above technical problem, the present invention is a buffer layer formed on a substrate, a first semiconductor layer formed on the buffer layer, and an active layer formed on the first semiconductor layer;

And a potential diffusion prevention layer formed to be part of any one of the semiconductor layers and the second semiconductor layer formed on the active layer, wherein the potential diffusion prevention layer is formed with the potential diffusion prevention layer interposed therebetween. Provided is a light emitting element having a first layer formed under the prevention layer and a second layer formed over the potential diffusion prevention layer.

The dislocation diffusion prevention layer is preferably formed to form a partial layer of the first semiconductor layer.

The dislocation diffusion prevention layer is Al _X Ga _Y P _(1-XY) N ( However, 0≤X, Y≤1) and Ga _X P _Y N ( However, it is preferable that it consists of a mixed layer of 0 <= X, Y <= 1).

The dislocation diffusion prevention layer is Al _X Ga _Y As _(1-XY) N ( However, 0≤X, Y≤1) and Ga _X As _Y N ( However, it is preferable that it consists of a mixed layer of 0 <= X, Y <= 1).

The buffer layer is preferably made of a mixture of SiN _X and GaN, or made of an AlN layer.

The sub-mount substrate is flip-bonded to the first and second semiconductor layers through a transparent electrode formed on the second semiconductor layer, a connecting electrode electrically connecting the first semiconductor layer and the transparent electrode, and metal bumps. It is preferable to include.

The present invention also provides a buffer layer on a substrate, a portion of a first semiconductor layer formed on the buffer layer, a potential diffusion prevention layer formed on a portion of the first semiconductor layer, and on the potential diffusion prevention layer It provides a method of manufacturing a light emitting device comprising forming a remainder of the first semiconductor layer, forming an active layer on the first semiconductor layer, and forming a second semiconductor layer on the active layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, widths, lengths, thicknesses, and the like of components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a view showing a part of the light emitting device according to the present invention, Figure 2 is a view showing a potential diffusion preventing layer according to the present invention.

3 is a view showing an embodiment of a light emitting device according to the present invention, Figure 4 is a view showing a manufacturing method of a light emitting device according to the present invention.

As shown in these drawings, the light emitting device according to the present invention is for flip chip. Referring to FIG. 1, the light emitting cell 100 is formed on the buffer layer 120 and the buffer layer 120 formed on the substrate 110. The first semiconductor layer 130 is formed, an active layer 150 formed on a portion of the first semiconductor layer 130, and a second semiconductor layer 160 formed on the active layer 150. Here, it is preferable that the first semiconductor layer 130 is an N-type semiconductor layer, and the second semiconductor layer 160 is a P-type semiconductor layer. Such light emitting cells 100 are arranged on the substrate 110.

The substrate 110 is a conventional wafer for fabricating a light emitting diode, and the substrate 110 may use at least one of Al 2 O 3, SiC, ZnO, Si, GaAs, GaP, LiAl 2 O 3, BN, AlN, and GaN. The substrate 110 is selected in consideration of the lattice constant of the semiconductor layer to be formed thereon. For example, when a GaN-based semiconductor layer is formed on the substrate 110, the substrate 110 may be made of sapphire.

On the substrate 110, a buffer layer 120 that serves as a buffer when the N-type semiconductor layer 130 is formed is formed. The buffer layer 120 is to reduce lattice mismatch between the substrate 110 and subsequent layers during crystal growth, and may be made of a mixed layer in which SiN _X and GaN are mixed or an AlN layer. In addition, the buffer layers 120 may be spaced apart from each other in units of cells, but the present invention is not limited thereto. When the buffer layers 120 are formed of an insulating material or a semi-insulating material, the buffer layers 120 may be continuous with each other. However, since the buffer layer 120 may not be formed, the present invention is not limited thereto.

The first semiconductor layer 130 (hereinafter referred to as an 'N-type semiconductor layer') is a layer in which electrons are generated. The N-type semiconductor layer 130 is formed of an N-type compound semiconductor layer and an N-type cladding layer. In this case, it is preferable that the N-type semiconductor layer 130 use a GaN film into which N-type impurities are injected. However, the present invention is not limited thereto, and material layers having various semiconductor properties are possible. In the present embodiment, an N-type semiconductor layer 130 including an N-type In _x Ga _y Al _{1- xy} N (0 ≦ x, y ≦ 1) film is formed.

The N-type semiconductor layer 130 includes a potential diffusion preventing layer 140.

Hereinafter, the potential diffusion prevention layer will be described in detail with reference to FIG. 2.

The potential diffusion preventing layer 140 is a crystal lattice in which each component is arranged regularly so as to reduce lattice mismatch of subsequent layers, such as the buffer layer 120, and further expands the potential defect extending from the lower buffer layer 120. It serves to prevent. Dislocation diffusion prevention layer 140 is Al _X Ga _Y P _(1-XY) N ( However, 0≤X, Y≤1) and Ga _X P _Y N ( However, each layer is composed of 0 ≦ X, Y ≦ 1). At this time, each layer is made of a plurality of layers repeatedly. In addition, the potential diffusion prevention layer 140 is made of Al _X Ga _Y As _(1-XY) N ( However, 0 ≦ _X , _Y ≦ 1) and Ga _X As _Y N ( However, each layer may be formed of 0 ≦ X, Y ≦ 1). Therefore, the second semiconductor layer 160, which will be described later, may selectively accept P atoms by the N-type semiconductor layer 130 to form a regular crystal lattice.

The second semiconductor layer 160 (hereinafter referred to as a 'P-type semiconductor layer') is a layer in which holes are generated. The P-type semiconductor layer 160 is formed of a P-type cladding layer and a P-type compound semiconductor layer. At this time, the P-type semiconductor layer 160 uses AlGaN implanted with P-type impurities. In this embodiment, a P-type semiconductor layer 160 including a P-type Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1) film is formed. In addition, an InGaN film may be used as the P-type semiconductor layer film.

The active layer 150 is a region where electrons and holes are recombined, and a multilayer film in which a quantum well layer and a barrier layer are repeatedly formed on the N-type semiconductor layer 130 may be used. As the barrier layer and the well layer, binary compounds GaN, InN, Al, etc. may be used, and ternary compounds In _x Ga _{1- x} N (0 ≦ _x ≦ 1) and Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1), and the like, can be used 4 won compound _{Al x In y Ga 1 -x- y} N (0≤x, y, x + y≤1). Of course, the N-type semiconductor layer 130 and the P-type semiconductor layer 160 may be formed by implanting predetermined impurities into the two- to four-membered compounds. Herein, the emission wavelength generated by the combination of electrons and holes in the active layer 150 is changed according to the type of material forming the active layer 150. Therefore, it is preferable that the active layer 150 adjusts a material included according to a target wavelength.

The active layer 150 is located on a portion of the N-type semiconductor layer 130, and the P-type semiconductor layer 160 is located on the active layer 150. Accordingly, a portion of the N-type semiconductor layer 130 is covered by the top surface of the active layer 150 and the P-type semiconductor layer 160, the remaining portion is exposed.

Referring to FIG. 3, as an embodiment of the light emitting device according to the present invention, an additional transparent electrode 161 is further formed on the P-type semiconductor layer 160 to reduce the resistance of the P-type semiconductor layer 160. The transparent electrode 161 may be indium tin oxide (ITO) or an ITO oxide as a transparent conductor.

In addition, the electrode 131 may be further included on the N-type semiconductor layer 130. In addition, an additional ohmic metal layer may be further formed on the N-type semiconductor layer 130 and the P-type semiconductor layer 160 to reduce the bonding resistance and facilitate the supply of current.

Hereinafter, a method of manufacturing a light emitting device according to the present invention having the above-described structure will be described with reference to FIG. 4.

The substrate 110 is prepared. (S200)

The buffer layer 120 is formed on the substrate 110. The buffer layer 120 may be formed using a MOCVD or MBE process. That is, the buffer layer 120 may be formed by supplying TMA, TMI, TMG, TEA and / or TEG as a source gas in the chamber, and supplying ammonia or the like as the reaction gas. When the buffer layer 120 is formed of AlN, TMA or TEA may be used as the source gas, and when the buffer layer 120 is formed of a mixture of SiN _X and GaN-based, TMG or TEG may be used as the source gas. (S210)

Next, the N-type semiconductor layer 130 is formed on the buffer layer 120. In this case, the N-type semiconductor layer 130 is formed by separating the first and second N-type semiconductor layers 131 and 133. First, the first N-type semiconductor layer 131 is formed on the buffer layer 120. (S220)

The potential diffusion prevention layer 140 is formed on the first N-type semiconductor layer 131. For example, on the first N-type semiconductor layer 131, Al _X Ga _Y P _(1-XY) N ( However, after forming layers of 0≤X, Y≤1), Ga _X P _Y N ( However, layers of 0 ≦ X, Y ≦ 1) may be laminated. At this time, the two layers are formed to be repeatedly stacked. Of course, Al _X Ga _Y As _(1-XY) N ( However, 0≤X, Y≤1) and Ga _X As _Y N ( However, 0? X, Y? 1) may be formed by stacking a plurality of layers as described above. Since the dislocation diffusion prevention layer 140 has a surface having few crystal defects, the dislocation diffusion prevention layer 140 affects the crystal structure crystal quality of the semiconductor layer to be formed thereon and the size distribution of the column, thereby reducing the crystal defect density.

Next, a second N-type semiconductor layer 133, like the first N-type semiconductor layer 131, is formed on the potential diffusion preventing layer 140. Here, since the second N-type semiconductor layer 133 is formed on the potential diffusion preventing layer 140, the density of crystal defects is reduced than that of the first N-type semiconductor layer 131.

The active layer 150 is formed on the second N-type semiconductor layer 133. (S250)

The P-type semiconductor layer 160 is formed on the active layer 150. (S260)

Next, the substrate 110 in which the above-described ones are stacked may be formed by etching the substrate 110 using photo and etching processes. In other words, a portion of the N-type semiconductor layer 130, the potential diffusion prevention layer 140, the active layer 150, the P-type semiconductor layer 160, and the buffer layer 120 are removed to separate the light emitting cells 100. . To this end, after forming a mask pattern (not shown) on the P-type semiconductor layer 160, the N-type semiconductor layer 130, the active layer 150, the P-type semiconductor layer 160 and the area exposed by the mask pattern and The buffer layer 120 is etched to electrically separate the plurality of light emitting cells 100. As a result, the light emitting cell 100 having a plurality of patterns is formed on the substrate 110. When the buffer layer 120 is formed of an insulating or semi-insulating material, etching of the buffer layer 120 may be omitted.

Next, a portion of the N-type semiconductor layer 130 is exposed by removing a portion of the P-type semiconductor layer 160, a portion of the N-type semiconductor layer 130, and an active layer 150 through an etching process. In other words, after forming an etch mask pattern on the P-type semiconductor layer 160, a dry / wet etching process is performed to remove the N-type semiconductor by removing the P-type semiconductor layer 160 and the active layer 150 in the exposed region. Expose layer 130. Thereafter, the electrode 131 and the transparent electrode 161 are formed on the N-type semiconductor layer 130 and the P-type semiconductor layer 160 of the light emitting cell 100. The electrode 131 and the transparent electrode 161 may be formed using a lift-off process. Here, since the electrode 131 on the N-type semiconductor layer 130 may be formed to be transparent, it may be simultaneously formed when the transparent electrode 161 is formed, thereby reducing the process.

The transparent electrode 161 is formed by applying a photoresist film over the entire structure and then performing a photolithography process using a mask to form a first photoresist pattern (not shown) to expose the P-type semiconductor layer 160. Thereafter, the transparent electrode 161 is formed on the entire structure, and the first photosensitive film pattern is removed and formed. The electrode 131 may also be formed in this manner.

Next, the light emitting cell 100 as described above is electrically connected to the electrode 131 and the transparent electrode 161 by a connection electrode (not shown), and is flip-bonded to the sub-mount substrate through metal bumps to be completed.

Here, as the potential diffusion preventing layer 140 repeats the stacked structure, defects of the uppermost layer, for example, the second N-type semiconductor layer 133 are reduced, and thus the crystal defect density of the P-type semiconductor layer 160 to be formed thereon. Can be further reduced.

According to embodiments of the present invention, the present invention can form a semiconductor layer with fewer crystal defects than the prior art, thereby reducing the density of crystal defects of the semiconductor layer to be formed thereon. Therefore, the light emitting device can increase the light efficiency.

Claims (13)

A buffer layer formed on the substrate; A first semiconductor layer formed on the buffer layer; An active layer formed on the first semiconductor layer; A second semiconductor layer formed on the active layer; And It includes a potential diffusion prevention layer formed to be part of any one of the semiconductor layers, The layer having the potential diffusion preventing layer formed thereon has a first layer formed below the potential diffusion prevention layer with the potential diffusion prevention layer interposed therebetween, and a second layer formed on the potential diffusion prevention layer. The method according to claim 1, The potential diffusion preventing layer is formed to form a partial layer of the first semiconductor layer. The method according to claim 1, The dislocation diffusion prevention layer is Al _X Ga _Y P _(1-XY) N ( However, 0≤X, Y≤1) and Ga _X P A light emitting device comprising: a plurality of layers each consisting of _Y N (where 0 ≦ _{X and Y} ≦ 1) are stacked. The method according to claim 1, The dislocation diffusion prevention layer is formed of Al _X Ga _Y As _(1-XY) N (where 0 ≦ _X , _Y ≦ 1) and Ga _X As _Y N (where 0 ≦ _X , _Y ≦ 1). A light emitting device characterized in that a plurality of stacked. The method according to claim 1, The buffer layer is a light emitting device, characterized in that made of a mixture of SiN _X and GaN-based. The method according to claim 1, The buffer layer is a light emitting device, characterized in that the AlN layer. The method according to claim 1, A transparent electrode formed on the second semiconductor layer; A connection electrode electrically connecting the first semiconductor layer and the transparent electrode; And And a submount substrate flip-bonded to the first and second semiconductor layers via metal bumps. Forming a buffer layer on the substrate, Forming a part of the first semiconductor layer on the buffer layer, Forming a potential diffusion prevention layer on a portion of the first semiconductor layer, Forming a remainder of the first semiconductor layer on the dislocation diffusion prevention layer; An active layer is formed on the first semiconductor layer, A method of manufacturing a light emitting device comprising forming a second semiconductor layer on the active layer. The method according to claim 8, The dislocation diffusion prevention layer is Al _X Ga _Y P _(1-XY) ( However, 0≤X, Y≤1) and Ga _X P _Y N ( However, the manufacturing method of the light emitting element characterized by consisting of a mixed layer of 0≤X, Y≤1). The method according to claim 8, The dislocation diffusion prevention layer is made of Al _X Ga _Y As _(1-XY) N (where 0 ≦ _X , _Y ≦ 1) and Ga _X As _Y N ( However, the manufacturing method of the light emitting element characterized by consisting of a mixed layer of 0≤X, Y≤1). The method according to claim 8, The buffer layer is a method of manufacturing a light emitting device, characterized in that consisting of a mixture of SiN _X and GaN-based. The method according to claim 8, The buffer layer is a method of manufacturing a light emitting device, characterized in that the AlN layer. The method according to claim 8, Forming a transparent electrode on the second semiconductor layer, Electrically connecting the transparent electrode and the first semiconductor layer, A method of manufacturing a light emitting device further comprising flip-bonding a submount substrate to the first and second semiconductor layers via metal bumps.

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