KR100695301B1 - manufacturing method of thin film transistor array panel for liquid crystal display - Google Patents

Abstract

A gate wiring including a gate line, a gate electrode, and a gate pad is formed on the insulating substrate, and a gate insulating film is formed. Next, an amorphous silicon layer, a doped amorphous silicon layer, a MoW film, and an Al-Nd film were deposited in sequence, and a data line, a source electrode, a drain electrode, and a data pad made of a double film were formed by using a mask including a slit pattern or a semi-transmissive film. An included data line and an ohmic contact layer and a semiconductor layer thereunder are formed. Next, after forming a protective film having a contact hole exposing the drain electrode, the gate pad and the data pad, heat treatment is performed. Next, a pixel electrode, an auxiliary gate pad, and an auxiliary data pad made of IZO are formed. As described above, in the present invention, the data wiring, the ohmic contact layer, and the semiconductor layer are formed in one photo process, and at this time, the MoW film and the Al-Nd film can be etched by one wet etching, thereby simplifying the process and the data wiring by MoW. The contact resistance with the IZO film formed thereon can be reduced through the heat treatment performed after forming the double film of the film and the Al-Nd film and forming the protective film.

MoW, Al-Nd, Heat Treatment, Slit Pattern, Transflective, IZO, Contact Resistance

Description

Manufacturing method of thin film transistor substrate for liquid crystal display device

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1;

3A is a layout view illustrating a thin film transistor substrate for a liquid crystal display device in a first step of manufacturing according to an embodiment of the present invention;

FIG. 3B is a cross-sectional view taken along line IIIb-IIIb in FIG. 3A;

4 is a cross-sectional view in the next step of FIG.

5A to 5D are cross-sectional views sequentially showing the process sequence in the next step of FIG. 4,

FIG. 6A is a layout view illustrating a thin film transistor substrate for a liquid crystal display device in a next step of FIG. 5D.

FIG. 6B is a cross-sectional view taken along the VIb-VIb line in FIG. 6A;

FIG. 7a is a layout view in the next step of FIG.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb of FIG. 7A.

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor substrate for a liquid crystal display device which reduces contact resistance.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal layer between the two substrates and the two substrates on which the plurality of electrodes are formed to generate an electric field is attached to the outer surface of each substrate to polarize light. It consists of two polarizing plates, and is a display device for controlling the amount of light transmitted by rearranging the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode.

A thin film transistor is formed on one substrate of the liquid crystal display, which serves to switch a voltage applied to the electrode. On the substrate on which the thin film transistor is formed, a plurality of wirings, that is, a plurality of gate lines and data lines, are formed in row and column directions, respectively. A pixel electrode is formed in the pixel region defined by the intersection of the gate line and the data line, and the thin film transistor controls the image signal transmitted through the data line according to the scan signal transmitted through the gate line and sends it out to the pixel electrode.

In recent years, as the size of the liquid crystal display increases, the length of the wiring increases and signal delay occurs. Therefore, a low-resistance metal should be used as the material of the wiring, for example, aluminum or an aluminum alloy. In this case, Al-Nd (aluminum-neodymium) may be used as an example of the aluminum alloy. In particular, in the case of forming the data wiring as an Al-Nd single layer, the silicon of the lower ohmic contact layer and the aluminum of the Al-Nd layer may be used. Since the resistance increases at the contact portion due to the reaction, the data wiring must be formed as a double layer of Cr / Al-Nd by using a buffer film such as chromium (Cr) between the data wiring and the ohmic contact layer below it.

However, in the case of using a double layer of Cr / Al-Nd, the number of etching processes is increased because the etching process of the two films is different, and thus, the photoresist pattern may be exposed to the etching solution, and thus the photoresist pattern may be easily peeled off. It is difficult to form the wiring and the semiconductor layer in one photo process.

The technical problem to be achieved by the present invention is to simplify the process.

In order to achieve such a problem, in the present invention, the data line is formed of a double film including a lower MoW film and an upper Al-Nd film.

According to the present invention, a gate wiring including a gate line and a gate electrode is formed on an insulating substrate, and a gate insulating film is formed. Next, a data line including a semiconductor layer, an ohmic contact layer, and a data line, a source electrode, and a drain electrode is formed. Next, a protective film having a first contact hole exposing the drain electrode is formed and then heat treated. next. A pixel electrode connected to the drain electrode is formed. In this case, the data line is formed of a double layer etched under the same etching conditions.

Here, it is preferable that the lower film is formed of molybdenum alloy and the upper film is formed of aluminum alloy film.

On the other hand, the etching conditions are wet etching and the etching solution preferably comprises H ₃ PO _4, HNO ₃ and CH ₃ COOH.

Further, the gate wirings may be formed of Al-Nd films, and the pixel electrodes are preferably formed of IZO.

Here, the gate line further includes a gate pad connected to the gate line, the data line further includes a data pad connected to the data line, and the passivation layer includes second and third contact holes exposing the gate pad and the data pad, respectively. And an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad, respectively, on the same layer as the pixel electrode.

Here, the semiconductor layer, the ohmic contact layer, and the data wiring may be formed in one photolithography process. In this case, the mask used in the photographing process varies in transmittance according to the position, and the mask preferably includes a semi-transmissive film or a slit pattern.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily practice the present invention. .

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

As shown in FIGS. 1 and 2, gate wirings 21, 22, and 23 made of aluminum or an aluminum alloy are formed on the insulating substrate 10. The gate wiring is connected to the gate line 21 extending in the horizontal direction, the gate electrode 22 that is part of the gate line 21, and the end of the gate line 21, and receives a scan signal from the outside to the gate line 21. A gate pad 23.

Here, although the gate wirings 21, 22, 23 are formed in a single layer, they may be formed in a double layer or triple layer or more. In the case of two or more layers, it is preferable that one layer is formed of a material having a low resistance, and the other layer is formed of a material having good contact properties with other materials, for example, Cr / Al or Al / Mo.

The gate wirings 21, 22, and 23 are covered with a gate insulating film 30 made of silicon nitride (SiN _X ).

A semiconductor layer 41 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30, and a resistivity made of a semiconductor such as amorphous silicon doped with n-type impurities such as phosphorus (P) is formed on the semiconductor layer 41. The contact layers 52 and 53 are formed separated from both sides with respect to the gate electrode 22.

On the ohmic contact layers 52 and 53, a data line 61, 62, 63, 64 including a lower layer 68 made of molybdenum alloy and an upper layer 69 made of aluminum and etched under the same etching conditions. ) Is formed. The data line includes a data line 61 extending in the vertical direction, a source electrode 62 that is part of the data line 61, a drain electrode 63 facing the source electrode 62 around the gate electrode 22, and data. And a data pad 64 connected to the line 61 to receive an image signal from the outside and transmit the image signal to the data line 61. In this case, it is preferable that the data wires 61, 62, 63, and 64 have a taper structure under the same etching conditions.

Here, the data lines 61, 62, 63, and 64 are double layers 68 and 69, but may be formed of a single layer or a triple layer similarly to the gate lines 21, 22, and 23.

Meanwhile, the ohmic contacts 52 and 53 have the same shape as the data wires 61, 62, 63, and 64, and lower the contact resistance between the semiconductor layer 41 and the data wires 61, 62, 63, and 64. Role. The semiconductor layer 41 has the same shape as that of the data lines 61, 62, 63, and 64 and the ohmic contacts 52 and 53 except between the source electrode 62 and the drain electrode 63.

A protective film 70 made of silicon nitride or an organic insulating film is formed on the data wirings 61, 62, 63, and 64 and the gate insulating film 30. The passivation layer 70 has not only a contact hole 73 exposing the gate pad 23 with the gate insulating film 30, but also a contact hole 74 and a drain electrode 63 exposing the data pad 64. It has a contact hole 72.

The pixel electrode 80, the auxiliary gate pad 83, and the auxiliary data pad 84 made of a transparent conductive material such as indium zinc oxide (IZO) are formed on the passivation layer 70.                     

The pixel electrode 80 is connected to the drain electrode 63 through the contact hole 72 to receive an image signal. The auxiliary gate pad 83 and the auxiliary data pad 84 are connected to the gate pad 23 and the data pad 64 through the contact holes 73 and 74, respectively, which are the pads 23 and 64 and the external circuit. It serves to complement the adhesion with the device and to protect the pads 23 and 64.

In the thin film transistor substrate for a liquid crystal display device having such a structure, the gate wirings 21, 22, 23 formed of Al-Nd films in the contact holes 72, 73, 74 through heat treatment performed after the protective film 70 is formed. ) And the contact resistance of the pixel electrodes 80, the auxiliary gate pads 83, and the auxiliary data pads 84 formed of the data lines 61, 62, 63, and 64 and the IZO can be reduced.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display device will be described with reference to FIGS. 3A to 7B and FIGS. 1 and 2.

First, as shown in FIGS. 3A and 3B, a conductive layer for a gate wiring, such as Al-Nd, is deposited on the insulating substrate 10 to a thickness of 1,000 Å to 3,000 Å by sputtering, such as Al-Nd, and is photographed using a mask. Patterned by an etching process to form the gate wiring (21, 22, 23).

Next, as shown in FIG. 4, the gate insulating film 30, the amorphous silicon layer 40, and the amorphous silicon layer 50 doped with n-type impurities are respectively 1,500 kV to 5,000 kPa and 500 kPa to 1,500 using chemical vapor deposition. And a thickness of 300 kPa to 600 kPa in order, and a lower film 68 of MoW and an upper film 69 of Al-Nd are deposited in order of 500 kPa and 2,000 kPa to 2,500 kPa, respectively, by sputtering or the like. Next, the photoresist film 110 is coated, exposed to a mask 100, and developed to form photoresist patterns 112 and 114 as shown in FIG. 5A. In this case, the mask 100 to be used includes a slit pattern smaller than the resolution of the transflective film or the exposure machine in the C part, the opaque part in the A part, and the transparent part in the B part as shown in FIG. 4. Therefore, it is an optical mask having a different transmittance of light. Among the photoresist patterns 112 and 114, the photoresist pattern 114 positioned between the source electrode 62 and the drain electrode 63 (C) is formed at a portion A on which the data lines 61, 62, 63, and 64 are to be formed. It is thinner than the photoresist pattern 112 located, and the photoresist of the other part B is not thick or thinner than other parts.

Next, as shown in FIG. 5B, the resistive contact layer 50 is exposed by patterning the upper layer 69 and the lower layer 68 of the other portion B under the same etching conditions using the photoresist patterns 112 and 114 as masks. . In this case, the etching conditions are wet etching, and when the aluminum etchant used to etch the metal layer including aluminum may be used, the lower layer 68 of the MoW may be etched together with the upper layer 69. In this case, it is preferable to use a solution obtained by mixing deionized water with a mixture of H ₃ PO ₄ , HNO _3, and CH ₃ COOH, and diluting the etching solution. It is preferable to have a tapered structure having an angle of about 20-70 ° under the conditions.

Next, as shown in FIG. 5C, the photoresist pattern 114, the exposed ohmic contact layer 50, and the lower semiconductor layer 40 are etched together to etch the gate insulating layer 30 of the other portion B and the upper layer of the C portion. Expose (69).

Next, as shown in FIG. 5D, the upper layer 69 exposed at the portion C and the lower layer 68 below are etched at once using the aluminum etching solution, and the exposed ohmic contact layer 50 is removed. Separate into two parts 52 and 53.

Next, the remaining photoresist layer pattern 112 is removed to form the data wires 61, 62, 63, and 64, the ohmic contact layers 52, 53, and the semiconductor layer 41 below the data lines 61, 6, and 6B. Complete

Next, as shown in FIGS. 7A and 7B, silicon nitride is deposited by chemical vapor deposition or spin-coated an organic insulating material to form a protective film 70 having a thickness of 3,000 Å or more, followed by heat treatment, and then patterned by a photolithography process. (72, 73, 74).

Next, as shown in FIGS. 1 and 2, a transparent conductive material such as IZO is deposited to a thickness of 400 kV to 500 kV by a sputtering method and patterned by a photolithography process to form the pixel electrode 80, the auxiliary gate pad 83, and the auxiliary. The data pad 84 is formed.

As described above, in the present invention, the data wires 61, 62, 63, and 64, the ohmic contacts 52, 53, and the semiconductor layer 41 are formed in one photo process, and the upper layer 68 and the lower layer 69 are formed at this time. ) Can be etched under the same etching conditions, so that the process can be simplified, and the data wirings 61, 62, 63, and 64 are formed as a double layer, and a protective film 70 is formed thereon, followed by heat treatment. It is possible to reduce the contact resistance with the IZO film.

 As described above, the present invention can simplify the process by patterning the double layer at the same time using the same etching conditions when forming the data wiring.The contact resistance between the aluminum-based metal film and the IZO film is formed by heat treatment after forming the protective film. Can be reduced.

Claims (19)

Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, Forming a gate insulating film on the gate wiring; Forming a silicon layer, a doped silicon layer and a metal layer on the gate insulating film, Patterning the metal layer, the doped silicon layer and the silicon layer in a single photolithography process to form a data line, an ohmic contact layer, and a semiconductor layer including a data line, a source electrode, and a drain electrode; Forming a passivation layer on the data line; Heat-treating the protective film; Forming a first contact hole in the protective film, Forming a pixel electrode connected to the drain electrode through the first contact hole on the passivation layer Including; And the data wiring is formed of a double film of a molybdenum alloy film and an aluminum alloy film formed on the molybdenum alloy film. delete delete In claim 1, The double layer is a method of manufacturing a thin film transistor substrate for a liquid crystal display device patterned by wet etching. In claim 4, The wet etching etchant includes H ₃ PO ₄ , HNO ₃ and CH ₃ COOH manufacturing method of a thin film transistor substrate for a liquid crystal display device. delete delete delete delete In claim 1, The manufacturing method of the thin-film transistor board | substrate for liquid crystal display devices whose mask used for the said photo process differs in a transmittance according to a position. In claim 10, The mask is a method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a semi-transmissive film or a slit pattern. Insulation board, A gate wiring formed on the substrate, the gate wiring including a gate line and a gate electrode; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer; A data line formed on the ohmic contact layer and comprising a double layer of a molybdenum alloy film and an aluminum alloy film formed on the molybdenum alloy film; A protective film covering the semiconductor layer and exposing the drain electrode, A pixel electrode connected to the drain electrode Including; The semiconductor layer except for the source electrode and the drain electrode is formed in the same planar pattern as the ohmic contact layer and the data line. delete delete In claim 12, The double layer is a thin film transistor substrate for a liquid crystal display device having a tapered structure having a 20-70 ° angle. delete delete delete delete

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