KR100680954B1 - Stacked chip package - Google Patents

Abstract

The present invention discloses a stack chip package, and the disclosed stack chip package includes a substrate having a plurality of bonding pads, a first semiconductor chip attached to the substrate and having a plurality of first bonding pads; A second semiconductor chip stacked on the first bonding pad surface of the first semiconductor chip and having the same size as the first semiconductor chip and having a plurality of second bonding pads, the first semiconductor chip and the second semiconductor chip; A first semiconductor interposed between the chips and formed in a space between the spacer having a smaller size than the first and second semiconductor chips and the first bonding pads on the first semiconductor chip, without forming an electrical connection. When the dummy pad made of a non-conductive tape supporting the chip and the second semiconductor chip, the bonding pad of the substrate and the first bonding pad of the first semiconductor chip are electrically connected. The key includes a first bonding wire, a second bonding wire electrically connecting a bonding pad of the substrate and a second bonding pad of the second semiconductor chip, first and second semiconductor chips on the substrate, first and And a molding covering the second bonding wire.

Description

Stacked Chip Packages {STACKED CHIP PACKAGE}

1 is a view for explaining a problem according to the prior art.

2 and 3 are plan and partial cross-sectional views illustrating a stack chip package according to an embodiment of the present invention.

4 and 5 are a plan view and a partial cross-sectional view for explaining a stack chip package according to another embodiment of the present invention.

The present invention relates to a semiconductor package, and more particularly, to a stack chip package having an overhang die structure.

Recently, according to the development of the semiconductor industry and the needs of users, electronic devices are becoming smaller and lighter, and packages, which are core components of electronic devices, are also becoming smaller and lighter. As a package type developed according to such a trend, a stack chip package implemented as a single unit semiconductor chip package by vertically stacking a plurality of semiconductor chips is known. Such a stack chip package is advantageous in size and weight in terms of size, weight, and mounting area, rather than using a plurality of unit semiconductor chip packages containing one semiconductor chip.

In addition, in order to stack semiconductor chips of the same size or different from each other, tape spacers have been used to protect the bonding wires of the semiconductor chips. Here, as a material of the spacer, a wafer backside lamination (WBL) or an epoxy, which is a non-conductive gluing material, may be used instead of the tape. The spacers are formed smaller than the sizes of the semiconductor chips to have an overhang structure, thereby securing a space occupied by the bonding wires on the semiconductor chips.

1 is a view illustrating a problem according to the prior art, reference numeral 1 denotes a substrate, reference numerals 3 and 5 denote semiconductor chips, reference numerals 3a and 5a denote bonding pads, reference numeral 7 denotes a spacer, and Reference numeral 9 denotes balls for forming bonding wires, respectively.

However, when manufacturing a stack chip package having such an overhang structure, since the upper semiconductor chip is in a relatively floating state, the most important rubbing and pressing forces are not transmitted during the wire bonding process. Therefore, in order to solve this problem, the wire bonding speed should be as slow as possible, the rubbing force is strong, and the pressing force is weakened to reduce the semiconductor chip elasticity as much as possible. In particular, in the case of stacking a plurality of semiconductor chips, the thickness of the semiconductor chips is getting thinner and stacking devices having different functions, the overhang is not keeping up with the trend. In general, wire bonding is possible under the chip thickness of 125㎛ and overhang length of 1mm.

However, in the prior art, in the wire bonding process, in order to transmit a rubbing force and a pressing force, by reducing the wire bonding speed, the movable force of the equipment is lowered. In addition, by applying a strong rubbing force and a pressing force weakly, the ball for forming the bonding wire is agglomerated, the BST (Ball Shear Test) value is not constant. In particular, the wire bonding process itself is difficult in a stack chip package structure in which the overhang length is outside the range of 1 mm in a 125 μm thick semiconductor chip.

In order to solve the above problems, an object of the present invention is to apply a dummy pad between the semiconductor chip of the overhang structure, the stack chip package capable of stably fixing the relatively floating semiconductor chip state to perform the wire bonding process stably Is to provide.

In order to achieve the above object, the present invention is a substrate having a plurality of bonding pads; A first semiconductor chip attached to the substrate and having a plurality of first bonding pads; A second semiconductor chip stacked on the first bonding pad surface of the first semiconductor chip, having a same size as the first semiconductor chip, and having a plurality of second bonding pads; A spacer interposed between the first semiconductor chip and the second semiconductor chip, the spacer having a smaller size than the first and second semiconductor chips; A dummy pad formed in a space between the first bonding pads on the first semiconductor chip and formed of a non-conductive tape supporting the first semiconductor chip and the second semiconductor chip without making an electrical connection; A first bonding wire electrically connecting the bonding pad of the substrate and the first bonding pad of the first semiconductor chip; A second bonding wire electrically connecting the bonding pad of the substrate and the second bonding pad of the second semiconductor chip; And a molding body covering the first and second semiconductor chips and the first and second bonding wires on the substrate.

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In addition, the present invention, a substrate having a plurality of bonding pads; A first semiconductor chip attached to the substrate and having a plurality of first bonding pads; A second semiconductor chip stacked on the first bonding pad surface of the first semiconductor chip, having a size larger than that of the first semiconductor chip, and having a plurality of second bonding pads; A spacer interposed between the first semiconductor chip and the second semiconductor chip, the spacer having a smaller size than the first semiconductor chip; A dummy pad formed in a space between the second bonding pads of the second semiconductor chip, the dummy pad being made of a non-conductive tape supporting the second semiconductor chip and the substrate without making an electrical connection; A first bonding wire electrically connecting the bonding pad of the substrate and the first bonding pad of the first semiconductor chip; A second bonding wire electrically connecting the bonding pad of the substrate and the second bonding pad of the second semiconductor chip; And a molding body covering the first and second semiconductor chips on the substrate and the first and second bonding wires.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 and 3 are plan and partial cross-sectional views illustrating a stack chip package according to an exemplary embodiment of the present invention, and correspond to a case in which the size of the first semiconductor chip and the second semiconductor chip is the same.

Stack chip package according to an embodiment of the present invention, as shown in Figures 2 and 3, the substrate 11 is provided with a plurality of bonding pads (11a), a plurality of attached to the substrate 11 The first semiconductor chip 21 having the first bonding pad 23 and the first bonding pad 23 stacked on the surface of the first semiconductor chip 21 are provided with a plurality of second bonding pads 33. A spacer 43 interposed between the second semiconductor chip 31, the first semiconductor chip 21 and the second semiconductor chip 31, and having a smaller size than the first and second semiconductor chips, and the first semiconductor chip. And a dummy pad 71 formed in the space between the first bonding pads 21a on the 21 to support the first semiconductor chip 21 and the second semiconductor chip 31. Here, as described above, the first and second semiconductor chips 11 and 31 have the same size.

In addition, the dummy pads 71 are not electrically connected to each other, and are formed by the size of the space between the first semiconductor chip 11 and the second semiconductor chip 21, and thus wire bonding in the second semiconductor chip 33. In the process, it serves to stably support the second semiconductor chip 33. Here, the dummy pad 71 may be manufactured in a bump ball shape according to a gap between the first semiconductor chip and the second semiconductor chip, or may use a non-conductive tape.

Meanwhile, a first bonding wire 51 is formed between the substrate 11 and the first semiconductor chip 11 to electrically connect the bonding pad 11a of the substrate 11 and the first bonding pad 13 to each other. A second bonding wire 53 is formed between the substrate 11 and the second semiconductor chip 33 to electrically connect the bonding pad 11a of the substrate 11 and the second bonding pad 33 to each other.

A molding member 61 is formed on the substrate 11 to cover the first semiconductor chip 11, the second semiconductor chip 31, and the first and second bonding wires 51 and 53.

Meanwhile, reference numeral 41, which is not described, indicates an adhesive interposed between the substrate and the first semiconductor chip to improve the adhesive force therebetween.

4 and 5 are a plan view and a partial cross-sectional view for explaining a stack chip package according to another embodiment of the present invention, which corresponds to the case where the sizes of the first semiconductor chip and the second semiconductor chip are different from each other.

Stack chip package according to another embodiment of the present invention, as shown in Figures 4 and 5, the substrate 101 is provided with a plurality of bonding pads (101a), a plurality of attached to the substrate 101 The first semiconductor chip 121 having the first bonding pad 123 and the first bonding pad 123 of the first semiconductor chip 121 are stacked on the surface of the first semiconductor chip 121 and are larger in size than the first semiconductor chip 121. The second semiconductor chip 131 provided with two second bonding pads 133 and the first semiconductor chip 121 and the second semiconductor chip 131 are interposed between the first semiconductor chip 121 and have a smaller size. A dummy pad 171 formed in a space between the excitation spacer 143 and the second bonding pads 131a of the second semiconductor chip 131 to support the second semiconductor chip 131 and the substrate 101. It includes.

In addition, an adhesive 141 is provided between the substrate 101 and the first semiconductor chip 121 to improve the adhesive force therebetween.

Here, the dummy pad 171 is not electrically connected to each other, and is formed to have a size of a space between the second semiconductor chip 131 in the substrate 101, and thus a wire bonding process in the second semiconductor chip 131. City, the second semiconductor chip 131 serves to stably fix and support so as not to float. The dummy pad 171 may be manufactured in a bump ball shape, and a plurality of bump balls may be stacked according to a gap between the second semiconductor chip and the substrate, or a non-conductive tape may be used. It is formed by stacking a plurality of bump balls in accordance with the distance between the substrate.

In addition, a first bonding wire 151 is formed between the substrate 101 and the first semiconductor chip 121 to electrically connect the bonding pad 101a of the substrate 101 and the first bonding pad 123. A second bonding wire 153 is formed between the substrate 101 and the second semiconductor chip 131 to electrically connect the bonding pad 101a of the substrate 101 and the second bonding pad 133.

On the other hand, a molding member 161 is formed on the substrate 101 to cover the first semiconductor chip 121, the second semiconductor chip 131, and the first and second bonding wires 151 and 153.

According to the present invention, a dummy pad is applied to a semiconductor chip having an overhang structure to stably fix the semiconductor chip so as not to float during the bonding wire process. Therefore, the wire bonding process can be performed stably.

As described above, the present invention stacks the semiconductor chip of the overhang structure and applies a dummy pad to the semiconductor chip of the overhang structure during package fabrication, thereby stably fixing the semiconductor chip so as not to float during the bonding wire process. . Therefore, the wire bonding process can be performed stably.

In addition, in the present invention, since the wire bonding speed does not need to be reduced during the wire bonding process, not only the moving force of the equipment can be improved, but also the ball for forming the bonding wire can be prevented to obtain a constant BST value.

In particular, the present invention is applicable when stacking semiconductor chips having different functions and when stacking semiconductor packages having a thickness of 125 μm has difficulty in manufacturing a stack chip package having an overhang length of 1 mm.

Claims (6)

A substrate having a plurality of bonding pads; A first semiconductor chip attached to the substrate and having a plurality of first bonding pads; A second semiconductor chip stacked on the first bonding pad surface of the first semiconductor chip, having a same size as the first semiconductor chip, and having a plurality of second bonding pads; A spacer interposed between the first semiconductor chip and the second semiconductor chip, the spacer having a smaller size than the first and second semiconductor chips; A dummy pad formed in a space between the first bonding pads on the first semiconductor chip and formed of a non-conductive tape supporting the first semiconductor chip and the second semiconductor chip without making an electrical connection; A first bonding wire electrically connecting the bonding pad of the substrate and the first bonding pad of the first semiconductor chip; A second bonding wire electrically connecting the bonding pad of the substrate and the second bonding pad of the second semiconductor chip; And A molding member covering first and second semiconductor chips and first and second bonding wires on the substrate; Stack chip package, characterized in that consisting of. delete delete A substrate having a plurality of bonding pads; A first semiconductor chip attached to the substrate and having a plurality of first bonding pads; A second semiconductor chip stacked on the first bonding pad surface of the first semiconductor chip, having a size larger than that of the first semiconductor chip, and having a plurality of second bonding pads; A spacer interposed between the first semiconductor chip and the second semiconductor chip, the spacer having a smaller size than the first semiconductor chip; A dummy pad formed in a space between the second bonding pads of the second semiconductor chip, the dummy pad being made of a non-conductive tape supporting the second semiconductor chip and the substrate without making an electrical connection; A first bonding wire electrically connecting the bonding pad of the substrate and the first bonding pad of the first semiconductor chip; A second bonding wire electrically connecting the bonding pad of the substrate and the second bonding pad of the second semiconductor chip; And A molding member covering first and second semiconductor chips and the first and second bonding wires on the substrate; Stack chip package, characterized in that consisting of. delete delete

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