KR100670183B1 - Plasma display device and driving method thereof - Google Patents

Abstract

In the plasma display device, the power recovery circuit is divided into two, and in the sustain period, the Vs voltage and the -Vs voltage are alternately applied to the scan electrodes by using resonance. At this time, after changing the voltage of the scan electrode by using resonance in the sustain period according to the load ratio of the plasma display panel, it is determined whether to apply the ground voltage to the scan electrode based on the magnitude of the load ratio of the plasma display panel. This can cause stable sustain discharge.

PDP, Electrode, Power Recovery, Capacitor, Duration, Separation, Resonance, Load Factor

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 illustrates a driving waveform of a plasma display device according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a sustain discharge driving circuit of a scan electrode driver according to a first exemplary embodiment of the present invention.

4 is a diagram illustrating a driving timing of the driving circuit illustrated in FIG. 3.

5A and 5B are diagrams showing current paths in respective modes of the driving circuit shown in FIG. 3, respectively.

6 is a diagram illustrating a sustain discharge driving circuit of a scan electrode driver according to a second exemplary embodiment of the present invention.

The present invention relates to a plasma display device and a driving method thereof.

The plasma display device is a display device using a plasma display panel that displays text or an image by using plasma generated by gas discharge. In the plasma display panel, dozens to millions or more pixels (discharge cells) are arranged in a matrix form according to their size.

The display panel of the plasma display device is driven by dividing one frame into a plurality of subfields having respective weights. Each subfield includes a reset period, an address period, and a sustain period. The reset period is a period of initializing discharge cells in order to stably perform the next address discharge. The address period is a period for selecting cells that are turned on and cells that are not turned on in the display panel. The sustain period is a period in which sustain discharge for actually displaying an image is performed for the cells to be turned on.

To perform this operation, sustain discharge pulses having a high level voltage (Vs voltage) and a low level voltage (0 V) are applied to the scan electrode and the sustain electrode in an opposite phase in the sustain period, and the scan electrode in the reset period and the address period. The reset waveform and the scan waveform are applied. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

In order to solve this problem, Korean Patent Laid-Open Publication No. 2003-90370 discloses a technique of applying a sustain discharge pulse having alternating Vs voltages and -Vs voltages to only the scan electrodes in the sustain period and biasing the sustain electrodes to the ground voltage. It is.

However, since the capacitive component Cp is formed by the scan electrode and the sustain electrode, when the voltage of the scan electrode is changed from -Vs (or Vs) voltage to Vs (or -Vs) voltage, it is (1/2) Cp (2Vs). ² ) power loss occurs. On the other hand, the power loss when the Vs voltage is alternately applied to the sustain electrode and the scan electrode is {(1/2) Cp (Vs) ² + (1/2) Cp (Vs) ² }. Therefore, when the Vs voltage and the -Vs voltage are alternately applied to the scan electrodes in the sustain period, the power loss increases twice as compared with the case where the Vs voltage is alternately applied to the sustain electrodes and the scan electrodes.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device and a driving method thereof capable of reducing power loss in a sustain period.

According to an aspect of the present invention, a controller is configured to divide a plurality of first electrodes, a plurality of second electrodes, and a frame into a plurality of subfields, calculate a screen load ratio from an input image signal, and the first period in a sustain period. There is provided a plasma display device including a driving circuit configured to alternately apply a second voltage higher than the first voltage and a third voltage lower than the first voltage to the second electrode while the first voltage is applied to the electrode. do.

In this case, the driving circuit may include a first switch connected between the first power supply for supplying the second voltage and the second electrode, and a second power supply connected between the second power supply for supplying the third voltage and the second electrode. A second switch connected between the second electrode and a third power supply for supplying a fourth voltage between the second voltage and the third voltage, and a first inductor having a first end connected to the second electrode And a first power recovery unit for changing a voltage of the second electrode through the first inductor, and a second inductor having a first end connected to the second electrode, and through the second inductor. A second power recovery unit for changing the voltage of the second electrode,

The controller may further increase the voltage of the second electrode through the first power recovery during a second period after increasing the voltage of the second electrode from the third voltage through the second power recovery unit during the first period. Increasing the voltage of the second electrode through the first power recovery unit at the second voltage during the third period, and then further decreasing the voltage of the second electrode through the second power recovery unit during the fourth period. The turn-on / turn-off of the third switch is determined between the first and second periods and between the third and fourth periods according to the screen load ratio of the plasma display panel.

According to another feature of the present invention, a first voltage is applied to the first electrode of the plasma display panel including a plurality of first electrodes and a plurality of second electrodes, and the first electrode is applied to the second electrode. In the plasma display device which alternately applies a high second voltage and a third voltage lower than the first voltage, a method of driving one frame into a plurality of subfields is provided. The driving method includes (a) reducing the voltage of the second electrode from the second voltage using a first inductor connected to the second electrode, and (b) using a second inductor connected to the second electrode. Further reducing the voltage of the second electrode, (c) applying the third voltage to the second electrode, and (d) using the second inductor to adjust the voltage of the second electrode. Increasing at three voltages, (e) further increasing the voltage of the second electrode using the first inductor, and (f) applying the second voltage to the second electrode; According to the screen load ratio of the plasma display panel, the second voltage and the second electrode to the second electrode in at least one of the steps (a) and (b) and between the steps (d) and (e). A fourth voltage between the third voltages is applied.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also an electrically connected part with another element in between.

In the present invention, the wall charge refers to a charge formed close to each electrode on the cell wall (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as “formed”, “accumulated” or “stacked” on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A plasma display device and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, the plasma display panel 100 includes a plasma display panel 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500.

The plasma display panel 100 includes a plurality of address electrodes (hereinafter referred to as “A electrodes”) A1 to Am extending in the column direction, and a plurality of sustain electrodes extending in pairs to each other in the row direction (hereinafter, “ X electrode ”(X1 to Xn) and scan electrode (hereinafter referred to as“ Y electrode ”) (Y1 to Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn. The Y electrodes Y1 to Yn and the X electrodes X1 to Xn are arranged to be orthogonal to the A electrodes A1 to Am. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms a cell. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an A electrode driving control signal, an X electrode driving control signal, and a Y electrode driving control signal, and divides and drives one frame into a plurality of subfields having respective luminance weights. do. Each subfield consists of a reset period, an address period, and a sustain period. According to an exemplary embodiment of the present disclosure, the control unit 200 changes the voltage on the Y electrode by using resonance in the sustain period as described later, and then ground voltage (0 V voltage) on the Y electrode according to the load ratio of the plasma display panel 100. Outputs the Y electrode driving control signal.

The address electrode driver 300 receives the A electrode driving control signal from the controller 200 and applies a driving voltage to the A electrode.

The scan electrode driver 400 receives a Y electrode driving control signal from the controller 200 and applies a driving voltage to the Y electrode.

The sustain electrode driver 500 receives the X electrode driving control signal from the controller 200 and applies a driving voltage to the X electrode.

Next, a driving waveform of the plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 2. In the following description, only driving waveforms applied to the Y electrode, the X electrode, and the A electrode forming one cell will be described.

2 illustrates a driving waveform of a plasma display device according to an exemplary embodiment of the present invention. 2 shows only drive waveforms in the sustain period.

As shown in Fig. 2, in the sustain period, a sustain discharge pulse having a Vs voltage and a -Vs voltage is alternately applied to the Y electrode while a 0V voltage is applied to the A electrode and the X electrode. In this case, since the pulse for sustain discharge is supplied only from the scan electrode driver 400, the impedance in the path to which the sustain discharge pulse is applied may be constant. The voltage of the Y electrode decreases from the Vs voltage to approximately 0V voltage and then decreases to the -Vs voltage, and the voltage of the Y electrode increases to the Vs voltage after increasing from the -Vs voltage to approximately 0V voltage. At this time, the voltage of the Y electrode may be maintained at a voltage of 0V for a predetermined period according to the screen load ratio.

In general, the wall voltage Vwxy is formed so that the potential of the Y electrode is higher than that of the X electrode in the cell selected as the cell turned on in the address period (not shown). Therefore, in the sustain period, a sustain discharge pulse having a voltage of Vs is first applied to the Y electrode while a 0 V voltage is applied to the A electrode and the X electrode to generate a sustain discharge between the Y electrode and the X electrode. At this time, the voltage Vs is set to be lower than the discharge start voltage between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is higher than the discharge start voltage. As a result of the sustain discharge, negative wall charges are formed on the Y electrode and positive wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vwyx is formed so that the potential of the X electrode is high with respect to the potential of the Y electrode. do.

Subsequently, a sustain discharge pulse having a voltage of -Vs is applied to the Y electrode to generate a sustain discharge between the Y electrode and the X electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can be generated when the Vs voltage is applied to the Y electrode. Thereafter, the process of alternately applying the sustain discharge pulse of the Vs voltage and the -Vs voltage to the scan electrode Y is repeated a number of times corresponding to the weight indicated by the corresponding subfield.

Next, with reference to FIG. 3, the drive circuit for applying a sustain discharge pulse in a sustain period is demonstrated in detail. The switches used below are shown as n-channel field effect transistors (FETs) with body diodes (not shown) and may be comprised of other switches having the same or similar function. The capacitive component formed by the X electrode and the Y electrode is shown as a panel capacitor Cp.

3 is a diagram illustrating a sustain discharge driving circuit of a scan electrode driver according to a first exemplary embodiment of the present invention.

As shown in FIG. 3, the sustain discharge driving circuit of the scan electrode driver 400 according to an exemplary embodiment of the present invention includes first and second power recovery units 410 and 420 and a voltage supply unit 430.

The first power recovery unit 410 includes transistors Yr1 and Yf1, an inductor L1, a diode Dr1 and Df1, and a capacitor Ce1, and the second power recovery unit 430 includes transistors Yr2 and Yf2. ), An inductor L2, diodes Dr2 and Df2, and a capacitor Ce2.

The power recovery capacitor Ce1 is connected to the drain of the transistor Yr1 and the source of the transistor Yf1, and the power recovery capacitor Ce2 is connected to the drain of the transistor Yr2 and the source of the transistor Yf2. . The second end of the inductor L1 having the first end connected to the Y electrode of the panel capacitor Cp is connected to the source of the transistor Yr1 and the drain of the transistor Yf1, and to the Y electrode of the panel capacitor Cp. The second end of the inductor L2 to which the first end is connected is connected to the source of the transistor Yr2 and the drain of the transistor Yf2. The diode Dr1 is connected between the source of the transistor Yr1 and the inductor L1, and the diode Df1 is connected between the source of the transistor Yf1 and the inductor L1. In addition, the diode Dr2 is connected between the source of the transistor Yr2 and the inductor L2, and the diode Df2 is connected between the source of the transistor Yf2 and the inductor L2. At this time, the voltage Vs / 2 is charged to the capacitor Ce1, and the voltage -Vs / 2 is charged to the capacitor Ce2.

The diodes Dr1 and Dr2 are for setting up a rising path for increasing the voltage of the panel capacitor Cp when the transistors Yr1 and Yr2 have a body diode, and the diodes Df1 and Df2 are transistors Yf1 and Yf2. Has a body diode to set the falling path for lowering the voltage of the Y electrode. In this case, if the transistors Yr1, Yr2, Yf1, and Yf2 do not have a body diode, the diodes Dr1, Df1, Dr2, and Df2 may be removed. The first power recovery unit 410 connected as described above increases or decreases the voltage of the Y electrode from 0V to Vs or from Vs to 0V by using resonance of the inductor L1 and the panel capacitor Cp. The second power recovery unit 420 increases the voltage of the Y electrode from the voltage of -Vs to 0V or from the voltage of 0V to -Vs by using the resonance of the inductor L2 and the panel capacitor Cp.

In the power recovery unit 410, the connection order between the inductor L1, the diode Df1, and the transistor Yf1 may be changed, and the connection order between the inductor L1, the diode Dr1, and the transistor Yr1 may also be changed. Can be. For example, the inductor L1 may be connected between the contacts of the transistors Yr1 and Yf1 and the power recovery capacitor Ce1. Similarly, the order of connection between the inductor L2, the diode Df2 and the transistor Yf2 in the power recovery unit 420 may be changed, and the connection order between the inductor L2, the diode Dr2 and the transistor Yr2 may be changed. Can be changed. In addition, although the inductor L1 is connected to the contacts of the transistors Yr1 and Yf1 in FIG. 5, the inductor may be connected to the rising path formed by the transistor Yr1 and the falling path formed by the transistor Yf1, respectively. have. This may also be applied to the second power recovery unit 420.

The voltage supply unit 430 includes transistors Ys1, Ys2, and Yg.

The transistor Ys1 is connected between the power supply Vs supplying the Vs voltage and the Y electrode of the panel capacitor Cp, and the transistor Ys2 is the power supply supplying the voltage -Vs and the panel capacitor Cp. Is connected between Y electrodes. The transistor Yg is connected between the Y electrode of the panel capacitor Cp and the power supply 0V supplying the 0V voltage, and is formed in a back-to-back form to block a current path through the body diode. have. At this time, if the body diode does not exist in the transistor Yg, the transistor Yg may not be formed back-to-back.

Next, with reference to FIGS. 4, 5A, and 5B, a time series operation change in the sustain period of the sustain discharge driving circuit according to an exemplary embodiment of the present invention will be described in detail. Here, the operation change is performed in eight modes (M1 to M8), and the mode change is caused by the operation of the transistor. The phenomenon referred to as LC resonance below is not a continuous oscillation, but a change in voltage and current caused by a combination of inductors L1 and L2 and panel capacitor Cp that occur when the transistors Yr1, Yr2, Yf1, and Yf2 are turned on. It is a phenomenon.

4 is a diagram illustrating a driving timing of the driving circuit illustrated in FIG. 3, and FIGS. 5A and 5B are diagrams illustrating current paths in respective modes of the driving circuit illustrated in FIG. 3.

It is assumed that before the mode 1 M1 starts, the transistor Yg is turned on so that a 0V voltage is applied to the Y electrode of the panel capacitor Cp.

In mode 1 M1, the transistor Yg is turned off and the transistor Yr1 is turned on. Then, as illustrated in FIG. 5A, a current path is formed by the Y electrodes of the capacitor Ce1, the transistor Yr1, the diode Dr1, the inductor L1, and the panel capacitor Cp (①). This path 1 causes LC resonance between the inductor L1 and the panel capacitor Cp. At this time, since the voltage Vs / 2 is charged to the capacitor Ce1, the voltage of the Y electrode of the panel capacitor Cp is Vs due to LC resonance. Increases to near voltage.

In mode 2 M2, transistor Ys1 is turned on and transistor Yr1 is turned off. Then, as illustrated in FIG. 5A, a current path ② is formed by the Y electrodes of the power supply Vs, the transistor Ys1, and the panel capacitor Cp (②), and the Vs voltage is applied to the Y electrode of the panel capacitor.

In mode 3 M3, transistor Yf1 is turned on and transistor Ys1 is turned off. Then, as shown in FIG. 5A, a current path is formed to the Y electrode, the inductor L1, the diode Df1, the transistor Yf1, and the capacitor Ce1 of the panel capacitor Cp (3). This path ③ causes LC resonance between the inductor L1 and the panel capacitor Cp. Due to this LC resonance, the voltage charged in the panel capacitor Cp is discharged, and the voltage of the Y electrode of the panel capacitor Cp decreases to near 0V voltage.

In mode 4 M4, the transistor Yg is turned on and the transistor Yf1 is turned off. Then, as shown in FIG. 5A, a current path ④ to the Y electrode of the panel capacitor Cp and the transistor Y1 is formed, and a 0V voltage is applied to the Y electrode of the panel capacitor Cp.

In mode 5 M5, transistor Yf2 is turned on and transistor Yg is turned off. Then, as shown in FIG. 5B, a current path is formed to the Y electrode, the inductor L2, the diode Df2, the transistor Yf2, and the capacitor Ce2 of the panel capacitor Cp (5). This path ⑤ generates an LC resonance between the inductor L2 and the panel capacitor Cp. Due to this LC resonance, the voltage charged in the panel capacitor Cp is discharged so that the voltage of the Y electrode of the panel capacitor Cp decreases to near the -Vs voltage.

In mode 6 M6, transistor Ys2 is turned on and transistor Yf2 is turned off. Then, as shown in FIG. 5B, a current path 6 is formed to the Y electrode, the transistor Ys2, and the power source (-Vs) of the panel capacitor Cp, and the -Vs voltage is applied to the Y electrode of the panel capacitor.

In mode 7 M7, transistor Yr2 is turned on and transistor Ys2 is turned off. Then, as shown in FIG. 5B, a current path is formed to the Y electrode of the capacitor Ce2, the transistor Yr2, the diode Dr2, the inductor L2, and the panel capacitor Cp (7). This path ⑦ generates an LC resonance between the inductor L2 and the panel capacitor Cp. At this time, since the capacitor Ce1 is charged with the voltage -Vs / 2, the voltage of the Y electrode of the panel capacitor Cp is 0V due to LC resonance. Increases to near voltage.

In mode 8 M8, transistor Yg is turned on and transistor Yr2 is turned off. Then, as shown in Fig. 5B, a current path (8) to the Y electrode of the transistor Yg and the panel capacitor is formed, and a 0V voltage is applied to the Y electrode of the panel capacitor Cp.

By repeating the above-described modes M1 to M8, the sustain discharge pulses having the Vs voltage and the -Vs voltage alternately may be applied to the Y electrode. In an embodiment of the present disclosure, mode 4 (M4) and / or mode 8 (M8) may not be performed according to the screen hatching rate. If the mode 4 (M4) is not performed, after the voltage of the Y electrode decreases to near the 0 V voltage in the mode 3 (M3), the voltage of the Y electrode is caused by the resonance of the mode 5 (M5) without the 0 V voltage being applied to the Y electrode. This decreases near the -Vs voltage. Similarly, if the mode 8 (M8) is not performed, the voltage of the Y electrode in the mode 7 (M7) increases to near the 0V voltage, and then the Y electrode is caused by the resonance of the mode 1 (M1) without the 0V voltage applied to the Y electrode. The voltage at increases until near the voltage Vs.

In this way, the power loss when the power recovery circuit is divided into two is {(1/2) Cp (Vs) ² + (1/2) Cp (Vs) ² }. Therefore, the power loss can be reduced compared to the power loss (1/2) Cp (2Vs) ² when the Vs voltage and the -Vs voltage are alternately applied to the conventional Y electrode.

However, if a 0 V voltage is applied to the Y electrode in every frame when the sustain discharge pulse is applied to the Y electrode in the sustain period, when there are many sustain discharge pulses, there is insufficient time to display an image, and the transistor Yg connected to the 0 V voltage is applied. Excessive on-off operation of) may stress transistor Yg.

In addition, when the sustain discharge pulse is applied to the Y electrode by using only resonance without applying the 0 V voltage to the Y electrode in every frame, distortion occurs in the waveform of the sustain discharge pulse. Specifically, when the voltage of the Y electrode is reduced from the Vs voltage to the 0V voltage by using resonance, the voltage of the Y electrode is reduced to near the 0V voltage without being reduced to the 0V voltage due to noise components on each path. Then, if the voltage of the Y electrode is reduced again to -Vs voltage by using resonance again, the voltage of the Y electrode does not decrease to -Vs voltage because the voltage of the Y electrode was not reduced to exactly 0V voltage before. . Therefore, if only the resonance is used in all the frames as described above, distortion may occur in the waveform of the sustain discharge pulse.

Therefore, when the sustain discharge pulse is applied to the Y electrode in the sustain period, the controller 200 determines whether to apply a 0 V voltage for each subfield according to the screen load ratio of the plasma display panel 100. That is, the controller 200 detects the screen load ratio of the plasma display panel 200, determines whether to turn on or off the transistor Yg according to the detected screen load ratio, and outputs a corresponding control signal to the scan electrode driver 400. Done.

The screen load ratio may be calculated as an average signal level ASL of an image signal input for one frame as shown in Equation 1. For example, when one pixel is formed of red (R), green (G), and blue (B) discharge cells, the image signal may be an R, G, B image signal.

,

,

은 각각 R, G, B 영상 신호의 레벨이며,

는 한 프레임이며,

은 한 프레임동안 입력된 R, G, B 영상 신호의 데이터 개수이다.here,

,

,

Are the levels of the R, G, and B video signals, respectively.

Is one frame,

Is the number of data of the R, G, and B image signals input during one frame.

In general, in the plasma display device, as the screen load ratio increases, the total number of sustain discharge pulses allocated to one frame decreases. That is, since the power consumption increases when the screen load ratio is large, the controller 200 reduces the number of sustain discharge pulses allocated to one frame. This reduces the number of sustain discharges so that power consumption does not exceed an appropriate threshold. Therefore, in the embodiment of the present invention, the controller 200 determines whether to apply a 0V voltage according to the screen load factor. That is, when the screen load ratio is smaller than the threshold value (for example, the screen load ratio when 1% of all cells are turned on), a large number of sustain discharge pulses are allocated to one frame, so that the control unit 200 may perform the maintenance period. Do not perform mode 4 (M4) and / or mode 8 (M8). When the screen load ratio is greater than the threshold value, since a small number of sustain discharge pulses are allocated to one frame, the controller 200 does not perform the mode 4 (M4) and the mode 8 (M8) in the sustain period.

However, as described above, when the voltage of the Y electrode is changed without passing through the 0V voltage in the sustain discharge pulse, distortion may occur in the sustain discharge pulse and thus the sustain discharge may be unstable. In particular, this phenomenon may occur in low weighted subfields where fewer sustain discharge pulses are assigned. Therefore, according to another embodiment of the present invention, when the screen load ratio is smaller than the threshold, the controller 200 performs mode 4 (M4) and mode 8 (M8) only during the sustain period of some subfields having a low weight.

In the exemplary embodiment of the present invention, the driving circuit of FIG. 3 is described as an example, but other driving circuits may be used. For example, as shown in FIG. 8, two transistors Yg1 and Yg2 may be used separately without forming the transistor Yg back-to-back. That is, the voltage supply unit 430 'includes transistors Ys1, Ys2, Yg1, and Yg2 and diodes Dg1 and Dg2. At this time, the transistor Yg1 having a drain connected to the first end of the inductor L1 is connected between the Y electrode of the panel capacitor Cp and a voltage of 0V, and the source is connected to the first end of the inductor L2. The transistor Yg2 is connected between the panel capacitor Cp and the 0V voltage of the Y electrode. The diode Dg1 is connected in the opposite direction to the body diode to block a current path through the body diode of the transistor Yg1. Similarly, the diode Dg2 is connected in the opposite direction to the body diode to block the current path through the body diode of the transistor Yg2. In this case, if the body diode does not exist in the transistors Yg1 and Yg2, the diodes Dg1 and Dg2 may be deleted. In such a driving circuit, the transistor Yg1 is turned on in the mode 4 (M8), and the transistor Yg2 is turned on in the mode 8 (M8) to apply a 0V voltage to the Y electrode of the panel capacitor Cp. .

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, in applying the Vs voltage and the -Vs voltage alternately by using resonance only for the scan electrodes in the sustain period, power loss can be reduced by separating the power recovery circuit into two. In addition, after the voltage of the scan electrode is changed by using resonance in the sustain period, the ground voltage (0 V voltage) is applied to the scan electrode according to the load ratio of the plasma display panel 100, thereby generating stable sustain discharge.

Claims (15)

First electrode, A second electrode extending in pairs with the first electrode, A control unit for dividing a frame into a plurality of subfields and calculating a screen load ratio from an input video signal; and And a driving circuit configured to alternately apply a second voltage higher than the first voltage and a third voltage lower than the first voltage to the second electrode while the first voltage is applied to the first electrode in the sustain period. , The drive circuit, A first switch connected between a first power supply for supplying the second voltage and the second electrode; A second switch connected between a second power supply for supplying the third voltage and the second electrode; A third switch connected between a third power supply for supplying a fourth voltage between the second voltage and the third voltage and the second electrode; A first power recovery unit including a first inductor having a first end connected to the second electrode, and changing a voltage of the second electrode through the first inductor; and A second inductor having a first end connected to the second electrode, a second power recovery unit configured to change a voltage of the second electrode through the second inductor, After the voltage of the second electrode is increased from the third voltage through the second power recovery unit during the first period, the voltage of the second electrode is further increased through the first power recovery unit during the second period. After the voltage of the second electrode is reduced from the second voltage through the first power recovery unit for three periods, the voltage of the second electrode is further reduced through the second power recovery unit during the fourth period, The control unit, And determining whether the third switch is turned on between the first and second periods and between the third and fourth periods based on the magnitude of the screen load ratio. The method of claim 1, The controller may turn on the third switch between the first and second periods and between the third and fourth periods in the sustain period of the plurality of subfields when the screen load rate is greater than a threshold load rate. . The method of claim 1, The controller may be configured to switch the third switch between the first and second periods and between the third and fourth periods only in a sustain period of some subfields of the plurality of subfields when the screen load rate is smaller than the threshold load rate. A plasma display device that turns on. The method of claim 3, And the partial subfields include a minimum weight subfield among the plurality of subfields. The method of claim 1, The controller may turn off the third switch between the first and second periods and between the third and fourth periods during the sustain period of the plurality of subfields when the screen load rate is less than the threshold load rate. Display device. The method according to any one of claims 1 to 5, And the fourth voltage is the same as the first voltage. The method according to any one of claims 1 to 5, The first power recovery unit, A fourth switch connected between the second end of the first inductor and a fourth power supply for supplying a fifth voltage between the fourth voltage and the second voltage, and A fifth switch connected between the second end of the first inductor and the fourth power source, The second power recovery unit, A sixth switch connected between a second end of the second inductor and a fifth power supply for supplying a sixth voltage between the fourth voltage and the third voltage, and And a seventh switch connected between the second end of the second inductor and the fifth power supply. The method according to any one of claims 1 to 5, And the difference between the second voltage and the first voltage is equal to the difference between the first voltage and the third voltage. The method of claim 8, And the first and fourth voltages are ground voltages. A second voltage higher than the first voltage and the first voltage to the second electrode in a state where a first voltage is applied to the first electrode of the plasma display panel including a plurality of first electrodes and a plurality of second electrodes. In the method of driving by dividing one frame into a plurality of subfields in the plasma display device to alternately apply a lower third voltage, (a) reducing the voltage of the second electrode from the second voltage using a first inductor connected to the second electrode, (b) further reducing the voltage of the second electrode using a second inductor connected to the second electrode, (c) applying the third voltage to the second electrode, (d) increasing the voltage of the second electrode at the third voltage using the second inductor, (e) further increasing the voltage of the second electrode using the first inductor, and (f) applying the second voltage to the second electrode, The second voltage at the second electrode in at least one of the steps (a) and (b) and between the steps (d) and (e) based on the magnitude of the screen load ratio of the plasma display panel. And determining whether to apply a fourth voltage between the third voltage and the third voltage. The method of claim 10, When the screen load ratio of the plasma display panel is greater than a threshold load ratio, the at least one of steps (a) and (b) and between (d) and (e) in the plurality of subfields is performed. A method of driving a plasma display device applying the fourth voltage to two electrodes. The method of claim 10, When the screen load ratio of the plasma display panel is smaller than a threshold load ratio, the operation may be performed between (a) and (b) and between (d) and (e) in some subfields of the plurality of subfields. And at least one of applying the fourth voltage to the second electrode. The method of claim 12, And the partial subfields include a minimum weight subfield among the plurality of subfields. The method according to any one of claims 10 to 13, And the fourth voltage and the first voltage are the same. The method of claim 14, And the fourth and first voltages are ground voltages.

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