KR100678730B1 - Method for obtaining margin of etching process - Google Patents

Abstract

The present invention relates to a method of securing an etching process margin in a liquid crystal display panel, comprising: forming and patterning a triple layer of cobalt / aluminum / cobalt on an upper surface of a glass substrate to form a gate electrode having a gate pad, wherein the gate electrode is covered Forming a gate insulator so as to form an active layer on a portion of the top surface of the gate insulator corresponding to the gate electrode and patterning the active layer to form an active layer; Forming and patterning a source electrode connected to one side of the active, a data line connected to the source electrode, and forming a drain electrode connected to the active and spaced apart from the source; forming a passivation layer to cover the data line and the drain electrode and corresponding to the drain electrode Corresponds to the part and gate pad Dry etching the portion with a Florin (F) -based gas, forming a pixel connected to the drain electrode, and annealing the data line to react the lower cobalt layer and the active layer of the data line to form cobalt silicide. It includes.

Description

METHODS FOR OBTAINING MARGIN OF ETCHING PROCESS}

1 is a side view for showing an etching process in a liquid crystal display panel according to an embodiment of the present invention;

2 is a side view illustrating a gate pad part in a liquid crystal display panel according to another exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

2: glass substrate, 4: gate metal,

6: gate insulator, 8: SiNx,

10: source / drain electrode, 12: ITO,

14: Passivation layer.

The present invention relates to a method for securing an etching process margin in a liquid crystal display panel, and more particularly, to a method for securing an etching process margin in a liquid crystal display panel laminated with a triple layer of Co / Al / Co with a gate electrode and data metal. will be.

By using a Co / Al / Co triple layer as a data line or gate line in the TFT via hole dry etching process, the selectivity for SF6 gas of SiNx (or SiON) and Co is obtained to obtain a process margin close to infinity. Can be improved.

In order to have n + a-Si and excellent ohmic contact resistance, Co / Al / Co triple layer data line is applied.

In the process of using SF6 as an etching gas in a semiconductor process, by using a Co / Al / Co triple layer thin film electrode, very good selectivity and electrical conductivity can be obtained.

It can be used to improve the interfacial properties of the Si / metal electrode in the semiconductor process and to implement a low-resistance electrode.

When using current Mo / Al / Mo data lines in the via-hole dry etching process, the upper Mo and passivation of SiNx, which is a passivation for SF6 gas, are poor, which can cause a large amount of defects in array and cell processes. . In addition, when SiNx and Al having excellent selectivity are used as a single layer, hillock, electromigration, and the like occur, thereby degrading device characteristics.

Conventional methods for producing Co-silicides with very low ohmic contact resistance on n + a-Si are deposited on n + a-Si and then heat-treated. Co-silicide was formed. However, this method has a lot of problems, such as the remaining amount of Co in the subsequent process to remove the remaining Co to proceed to the subsequent process.

The data lines (Mo / Al / Mo) in the current staggered TFT array process are in contact with n + a-Si at the bottom and ITO at the top, respectively. In this stack of data lines, n + a-Si makes contact with Mo, resulting in a relatively high ohmic contact resistance. In addition, the presence of fine defects at this interface has a higher ohmic contact resistance, causing pixel defects and the like, which may cause a decrease in yield.

When using a single layer of Co as a data line, there are many limitations due to the relatively high resistance of Co.

The present invention has been made to improve as described above, an object of the present invention is to cobalt / aluminum / cobalt (Co / Al / Co) triple the data line, gate line, source electrode and drain electrode included in the liquid crystal display panel When the insulating layer is formed on the triple layer and the via hole is formed by the layer, the etching margin and the etching yield may be improved during the etching process due to the high etching selectivity of the cobalt and the insulating layer to secure the etching process margin.

According to a preferred embodiment of the present invention for achieving the above object, a step of forming a gate electrode having a gate pad by forming and patterning a triple layer of cobalt / aluminum / cobalt on the upper surface of the glass substrate, the gate electrode Forming a gate insulator such that the gate insulator is covered; forming an active layer on a portion of the top surface of the gate insulator corresponding to the gate electrode to form an active layer; and forming cobalt / aluminum / cobalt on the top surface of the glass substrate to cover the active Forming and patterning a triple layer to form a source electrode connected to one side of the active, a data line connected to the source electrode, and a drain electrode connected to the active and spaced apart from the source, forming a passivation layer to cover the data line and the drain electrode, and forming a drain electrode Corresponding parts and gate pads Dry etching the portion with a Florin (F) -based gas, forming a pixel connected to the drain electrode, and annealing the data line to react the lower cobalt layer and the active layer of the data line to form cobalt silicide. It includes.

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Hereinafter, a method of securing an etching process margin in a liquid crystal display panel according to the present invention will be described in detail with reference to the accompanying drawings.

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1 is a cross-sectional view illustrating pixels of a liquid crystal display panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a gate pad part of a liquid crystal display panel according to another exemplary embodiment of the present invention.

First, a gate metal layer (not shown) is deposited on the glass substrate 2. In this embodiment, the gate metal layer may be an aluminum / cobalt (Al / Co) or cobalt / aluminum / cobalt (Co / Al / Co) triple layer. Subsequently, a photoresist pattern (not shown) is formed on the gate metal layer, which is an aluminum / cobalt (Al / Co) or cobalt / aluminum / cobalt (Co / Al / Co) triple layer, and the photoresist pattern is used as an etching mask. The gate metal layer is patterned by wet etching or dry etching, thereby forming a gate electrode 4 having a gate pad formed at an end thereof.
In the present embodiment, when a cobalt / aluminum / cobalt (Co / Al / Co) triple layer or an aluminum / cobalt (Al / Co) bilayer is used as the gate metal layer, a gate pad is applied to the gate insulating layer 6 covering the gate metal layer. When forming an exposed via hole (not shown), a gate insulating layer 6 made of SiNx (8) or SiON (6) and a cobalt / aluminum / cobalt (Co / Al / Co) triple layer or aluminum / cobalt (Al) / Co) high etching selectivity can be realized between the gate metal layer, which is a double layer.

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On the other hand, after the gate electrode 4 is formed by patterning the gate metal layer, the gate insulating layer 6 covering the gate electrode 4 is formed.
Subsequently, after the gate insulating layer 6 is formed, an active layer containing n + amorphous silicon (n + a-Si) is formed on the gate insulating layer 6, and a portion corresponding to the gate electrode 4 of the active layer is formed. A photoresist pattern covering the film is formed. Subsequently, the active layer is patterned using the photoresist pattern as an etch mask to form an active corresponding to the gate electrode 4 on the gate insulating layer 6.
Subsequently, a source / drain metal layer (not shown) covering the gate insulating layer 6 and the active is formed. At this time, the source / drain metal layer (not shown) is made of a cobalt / aluminum / cobalt (Co / Al / Co) triple layer. Subsequently, a photoresist pattern (not shown) is formed on the source / drain metal layer formed of the triple layer, and the photoresist pattern is etched by an etching process. In this case, the source / drain metal layer may be wet etched at room temperature to about 50 ° C. or may be dry etched using Cl-based gas. The source / drain metal layers are etched to form active and data lines connected to the source and drain electrodes 10 and the source electrodes, respectively. The source electrode and the drain electrode 10 are spaced apart from each other by a predetermined interval.
Subsequently, a passivation layer 14 covering the source electrode and the drain electrode 10 is formed, and the via layer 12 is formed on the passivation layer 14 by a dry etching process. In order to form the via holes 12 in the protective film 14, SF6 gas is used. The upper cobalt Co deposited as the upper layer of the drain electrode 10 is hardly etched by the activated SF6 because it has a large etching selectivity with respect to the SF6 gas.
Therefore, when the via hole 12 is formed in the passivation layer 14 covering the drain electrode 10 by using a cobalt layer as an upper layer of the drain electrode 10 and the data line, the passivation layer 14 and the drain electrode 10 are interposed therebetween. The high etch selectivity can provide sufficient process margin.

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In addition, since the gate pad connected to the gate electrode 4 also uses cobalt / aluminum / cobalt (Co / Al / Co) or aluminum / cobalt (Al / Co), the gate pad 18 may be formed to form a via hole in the gate pad part 18. When etching the insulating layer 6, a sufficient process margin can be obtained by the large etching selectivity of the gate insulating layer 6 and the gate pad portion 18.

Subsequently, a transparent and conductive pixel electrode layer (not shown) is formed on the upper surface of the passivation layer 14, and the pixel electrode layer is patterned and connected to the drain electrode 10 through the via hole 12. ) Is formed.
At this time, cobalt (Co), which is an upper layer of the drain electrode 10, has a large etching selectivity with respect to the pixel electrode etchant, and thus, defects such as opening of the drain electrode 10 by the etchant when etching the pixel electrode 20 are performed. Can be significantly lowered.

Thereafter, an annealing process is performed. By the annealing process, cobalt silicide 16 having excellent interfacial properties and very low ohmic contact resistance is formed at an active interface contacting cobalt (Co) and cobalt, which are lower layers of the data line and drain electrode 10. At this time, the annealing temperature in the annealing process is about 300 ℃.

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Summarizing the above, a protective film (co) may be applied to expose the drain electrode 10 by applying a cobalt / aluminum / cobalt (Co / Al / Co) triple layer to the gate line 4, the drain electrode 10, the data line, and the like. When dry etching the via hole in 14), when dry etching the gate insulating layer 6 covering the gate pad portion 18, the cobalt (Co) is not etched by the etching gas SF6, so the electrical characteristics of the device Can greatly improve.

On the other hand, the cobalt (Co) layer, which is the upper layer of the drain electrode, has excellent physical and chemical durability against the wet etchant that etches the pixel electrode 20 when the pixel electrode ITO 20 is etched. (20) It is possible to greatly reduce the line open generated during etching.

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According to the present invention, the cobalt / aluminum / cobalt (Co / Al / Co) triple layer is patterned to be a gate line, a data line, and a source electrode and a drain electrode, and then annealed to form cobalt silicide (Co-silicide), thereby remaining Co. The problem does not occur at all.
In addition, an optimal process method may be secured by using a high etching selectivity between the cobalt layer Co and the passivation layer, which are upper layers of the data line.
Meanwhile, the cobalt layer Co, which is an upper layer of the data line, the passivation layer, and the cobalt layer Co, which is a lower layer of the data line, are in contact with the active layer. Therefore, when the final annealing process is performed, cobalt silicide having very low ohmic contact resistance is formed between the active layer and the cobalt layer. On the other hand, since the protective layer does not thermally react with cobalt, no silicide is formed.
In addition, cobalt has excellent chemical resistance with respect to ITO etchant etching the ITO forming the current pixel electrode, so that the source electrode, the drain electrode and the data line are formed with a cobalt / aluminum / cobalt (Co / Al / Co) layer. If used, the line open caused by ITO etchant attack can be greatly reduced.
Therefore, according to the method of securing the etching process margin in the liquid crystal display panel according to the present invention, by securing the etching margin and the optimal etching recipe during the via hole dry etching process, it is possible to obtain various effects such as accumulation of process technology, improvement of yield, etc. In addition, it is possible to secure an excellent etching process margin in the four mask process.

Claims (5)

Forming and patterning a triple layer of cobalt / aluminum / cobalt on an upper surface of the glass substrate to form a gate electrode having a gate pad; Forming a gate insulator covering the entire glass substrate including the gate electrode and the gate pad; Forming an active layer on an upper surface of the gate insulator corresponding to the gate electrode to form an active layer; Forming and patterning the triple layer of cobalt / aluminum / cobalt on the upper surface of the glass substrate to cover the active, a source electrode connected to one side of the active, a data line connected to the source electrode, and connected to the active Forming a drain electrode spaced apart from the drain electrode; Forming a passivation layer to cover the data line and the drain electrode, and dry etching a portion corresponding to the drain electrode and a portion corresponding to the gate pad with a florin (F) -based gas; Forming a pixel electrode connected to the drain electrode; And Annealing the data line to react the lower cobalt layer and the active layer to form cobalt silicide, wherein the etching process margin is secured in the liquid crystal display panel. delete delete delete        The method of claim 1, wherein the forming of the cobalt silicide is performed by using an excimer laser.

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