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KR100650762B1 - Manufacture method of pad redistribution package - Google Patents

Manufacture method of pad redistribution package Download PDF

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Publication number
KR100650762B1
KR100650762B1 KR1020050100837A KR20050100837A KR100650762B1 KR 100650762 B1 KR100650762 B1 KR 100650762B1 KR 1020050100837 A KR1020050100837 A KR 1020050100837A KR 20050100837 A KR20050100837 A KR 20050100837A KR 100650762 B1 KR100650762 B1 KR 100650762B1
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South Korea
Prior art keywords
pad
metal layer
metal film
insulating layer
package
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KR1020050100837A
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Korean (ko)
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양승택
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemically Coating (AREA)

Abstract

A method for manufacturing a pad rerouting package is provided to economize the amount of a plating metal and to simplify manufacturing processes by performing a plating process on a rerouted pad portion alone. A first insulating layer is coated on a predetermined wafer(S1). A first metal film is formed on the first insulating layer by using an electroplating process(S2). A second insulating layer is coated on the first metal film. At this time, a predetermined portion of the first metal film is exposed to the outside(S3). A second metal film is formed on the exposed portion of the first metal film by using an electroless plating process(S4). The resultant structure is mounted on a substrate. The substrate and the second metal film are electrically connected with each other.

Description

패드 재배열 패키지 제조 방법{Manufacture method of pad redistribution package}Manufacture method of pad redistribution package

도 1은 본 발명의 일 실시예에 따른 패드 재배열 패키지 제조 방법을 순차적으로 나타낸 순서도,1 is a flowchart sequentially showing a method for manufacturing a pad rearrangement package according to an embodiment of the present invention;

도 2a 내지 도 2g는 도 1의 패드 재배열 패키지 제조 방법을 순차적으로 나타낸 단면도.2A through 2G are cross-sectional views sequentially illustrating a method of manufacturing a pad rearrangement package of FIG. 1.

본 발명은 패드 재배열 패키지 제조 방법에 관한 것으로서, 특히 패드 부분을 Au의 무전해 도금방식에 의하여 형성하는 패드 재배열 패키지 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a pad rearrangement package, and more particularly, to a method for manufacturing a pad rearrangement package in which a pad portion is formed by an electroless plating method of Au.

최근 전자 제품의 경박단소화 및 고성능화에 발맞추어, 전자 제품에 들어가는 반도체 패키지 역시 경박단소화 및 고성능화 되어가는 추세이다.In line with the recent miniaturization and high performance of electronic products, semiconductor packages for electronic products are also becoming thin and short and high performance.

따라서, 패키지에 실장되는 칩 역시 크기는 작아지고, 스피드는 빨라지며, 용량이 커짐에 따라 외부로 신호를 보내는 패드의 피치 또한 복잡한 위치를 나타내고 있다.Therefore, the chip mounted in the package also has a smaller size, faster speed, and as the capacity increases, the pitch of the pad that signals to the outside also shows a complicated position.

패드 사이의 피치와 패드의 크기가 작아짐에 따라 와이어 본딩을 이용한 패키지를 적용하기가 점차 어려워지고 있다.As the pitch between the pads and the size of the pads become smaller, it becomes increasingly difficult to apply a package using wire bonding.

이에 최근 패드 재배열 기술이 출현하였는데, 이 패드 재배열 기술은 와이어와 패드 간의 접합성을 향상시키기 위하여 스퍼터에 의하여 Cu 금속층을 형성한 후, 이 Cu 금속층에 위에 전해 도금 방식에 의하여 Au 금속층을 코팅 및 패턴 형성을 위해 에칭 등을 한다.Recently, a pad rearrangement technique has emerged. In this pad rearrangement technique, a Cu metal layer is formed by sputtering to improve adhesion between a wire and a pad, and then the Au metal layer is coated on the Cu metal layer by electroplating. Etching is performed for pattern formation.

그런데, 이와 같은 패드 재배열 기술은 가격이 비싼 Au를 전해 도금 방식에 의하여 Cu 금속층 전면에 도금을 하여 패드를 형성하므로 비경제적이며, 패턴을 형성하기 위하여 에칭 등을 하여야 하므로 공정이 복잡해 지는 등의 문제점이 있다.However, such a pad rearrangement technique is inexpensive because the pad is formed by plating the entire surface of the Cu metal layer by electroplating Au, which is expensive, and the process is complicated because etching is required to form a pattern. There is a problem.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 경제적이며, 제조 공정을 단순화시킬 수 있는 패드 재배열 패키지를 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a pad rearrangement package which is economical and can simplify the manufacturing process.

상기의 목적을 달성하기 위한 본 발명의 패드 재배열 패키지는, 팹 아웃 웨이퍼 상에 제1절연층을 코팅하는 단계; 상기 제1절연층 상에 제1금속층을 전해 도금하는 단계; 상기 제1금속층의 소정 부분이 노출되도록, 상기 제1금속층 상에 제2절연층을 코팅하는 단계; 상기 노출된 소정 부분에 제2금속층을 무전해 도금하는 단계; 및 상기 제2금속층이 도금된 팹 아웃 웨이퍼를 기판 상에 실장한 후, 상기 기판과 상기 제2금속층을 전기적으로 연결하고 밀봉하는 단계를 포함한 것이 바람 직하다.The pad rearrangement package of the present invention for achieving the above object, the step of coating a first insulating layer on the fab out wafer; Electroplating a first metal layer on the first insulating layer; Coating a second insulating layer on the first metal layer so that a predetermined portion of the first metal layer is exposed; Electroless plating a second metal layer on the exposed predetermined portion; And mounting the fab-out wafer on which the second metal layer is plated on the substrate, and electrically connecting and sealing the substrate and the second metal layer.

여기서, 상기 소정 부분은 상기 팹 아웃 웨이퍼의 센터 및 에지 부분 중 어느 한 부분인 것이 바람직하다.Here, the predetermined portion is preferably any one of the center and the edge portion of the fab out wafer.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 일 실시예에 따른 패드 재배열 패키지의 제조 방법을 순차적으로 나타낸 순서도이고, 도 2a 내지 도 2g는 도 1에 따라 패드 재배열 패키지의 제조 방법을 순차적으로 나타낸 단면도이다.1 is a flow chart sequentially showing a method of manufacturing a pad rearrangement package according to an embodiment of the present invention, Figures 2a to 2g is a cross-sectional view showing a method of manufacturing a pad rearrangement package in accordance with FIG.

도면을 참조하면, 패드 재배열 패키지 제조 방법은, 먼저 도 2a와 같이 팹 아웃 웨이퍼(10)를 준비한 후, 이 팹 아웃 웨이퍼(10) 상에 제1절연층(20)을 코팅한다.(S1) 이 제1절연층(20)은 팹 아웃 웨이퍼(10) 상에 마련된 퓨즈 박스(11) 등을 보호하기 위한 것이다. Referring to the drawing, in the method for manufacturing a pad rearrangement package, first, as shown in FIG. 2A, the fab-out wafer 10 is prepared, and then the first insulating layer 20 is coated on the fab-out wafer 10. The first insulating layer 20 is for protecting the fuse box 11 or the like provided on the fab-out wafer 10.

다음으로, 제1절연층(20) 상에 Cu나 Au와 같은 전기 전도성이 우수한 금속을 전해 도금하여 제1금속층(30)을 코팅한다.(S2)Next, the first metal layer 30 is coated by electroplating a metal having excellent electrical conductivity such as Cu or Au on the first insulating layer 20. (S2)

다음으로, 제1금속층(30) 상에 패드의 재배열될 위치만이 외부로 노출되도록 포토 공정에 의하여 제2절연층(40)을 코팅한다.(S3)Next, the second insulating layer 40 is coated by the photo process so that only the positions of the pads to be rearranged on the first metal layer 30 are exposed to the outside.

그리고 나서, 외부로 노출된 제1금속층(30) 상에 Au나 Cu로 무전해 도금을 하여 제2금속층(50)을 코팅한다.(S4)Then, the second metal layer 50 is coated by electroless plating with Au or Cu on the first metal layer 30 exposed to the outside.

이렇게 무전해 도금을 실시하면 패드가 재배열될 위치에만 도금이 되므로 Au 등을 소량만 사용할 수 있게 된다.When the electroless plating is performed, the plating is performed only at the position where the pad is to be rearranged, so that only a small amount of Au can be used.

다음으로 제2금속층(50)이 도금된 팹 아웃 웨이퍼(10)를 절단부재(80)로 잘라 개별화시키고, 이 개별화된 팹 아웃 웨이퍼(10), 즉 칩을 기판(60) 상에 적층 후, 제2금속층(50), 즉 재배열된 패드(50)와 기판(60) 사이를 와이어(70)에 의하여 전기적으로 연결 및 칩과 와이어 등을 외부로부터 보호하기 위하여 몰딩을 하면 패키지 제조가 완료된다.Next, the fab out wafer 10 plated with the second metal layer 50 is cut and individualized by the cutting member 80, and the individualized fab out wafer 10, that is, the chip is stacked on the substrate 60. Package is completed when the second metal layer 50, ie, the rearranged pad 50 and the substrate 60, is electrically connected by wires 70 and molded to protect chips and wires from the outside. .

이와 같은 패드 재배열 패키지 제조 방법에 의하면, 무전해 도금 방식에 의하여 재배열된 패드에만 선택적으로 Au 등의 도금을 실시함으로써, 종래 전면에 도금을 실시하였던 전해 도금 방식보다 도금을 위한 금속을 절약할 수 있고, 또한 전해 도금 방식에 의하여 패드 재배열 시, 필요하였던 에칭 등의 과정을 생략할 수 있어 공정을 단순화시킬 수 있게 된다.According to the method for manufacturing a pad rearrangement package, plating of Au and the like only on pads rearranged by an electroless plating method can save metal for plating than an electrolytic plating method which is conventionally plated on the entire surface. In addition, when the pad rearrangement is performed by the electroplating method, a process such as etching required may be omitted, thereby simplifying the process.

상술한 바와 같이 본 발명의 패드 재배열 패키지 제조방법에 의하면, 무전해 도금 방식에 의하여 재배열된 패드 부분에만 도금을 실시함으로써, 도금에 사용되는 도금 금속의 양을 절약할 수 있고, 또한 전해 도금 방식에서 필요하였던 에칭 등의 과정을 생략할 수 있어 공정을 단순화 시키는 효과를 제공한다.As described above, according to the method for manufacturing a pad rearrangement package of the present invention, plating is performed only on the pad portion rearranged by an electroless plating method, thereby saving the amount of plated metal used for plating, and electrolytic plating. Since the process such as etching required in the method can be omitted, the process is simplified.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (2)

팹 아웃 웨이퍼 상에 제1절연층을 코팅하는 단계; Coating a first insulating layer on the fab out wafer; 상기 제1절연층 상에 제1금속층을 전해 도금하는 단계; Electroplating a first metal layer on the first insulating layer; 상기 제1금속층의 소정 부분이 노출되도록, 상기 제1금속층 상에 제2절연층을 코팅하는 단계; Coating a second insulating layer on the first metal layer so that a predetermined portion of the first metal layer is exposed; 상기 노출된 소정 부분에 제2금속층을 무전해 도금하는 단계; 및 Electroless plating a second metal layer on the exposed predetermined portion; And 상기 제2금속층이 도금된 팹 아웃 웨이퍼를 기판 상에 실장한 후, 상기 기판과 상기 제2금속층을 전기적으로 연결하고 밀봉하는 단계를 포함한 것을 특징으로 하는 패드 재배열 패키지 제조 방법.And mounting the fab-out wafer on which the second metal layer is plated on a substrate, electrically connecting and sealing the substrate and the second metal layer. 제1항에 있어서,The method of claim 1, 상기 소정 부분은 상기 팹 아웃 웨이퍼의 센터 및 에지 부분 중 어느 한 부분인 것을 특징으로 하는 패드 재배열 패키지 제조 방법.Wherein the predetermined portion is any one of a center and an edge portion of the fab out wafer.
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
KR101237963B1 (en) 2008-04-15 2013-02-27 삼성테크윈 주식회사 Forming method of bump for semiconductor chip

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JPH08227656A (en) * 1995-02-20 1996-09-03 Merutetsukusu Kk Formation of conductive pattern for plasma display
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KR100451767B1 (en) 2001-12-22 2004-10-08 주식회사 하이닉스반도체 Method for forming interconnect structures of semiconductor device
KR20050033892A (en) * 2003-10-07 2005-04-14 주식회사 하이닉스반도체 Method of forming a metal wiring in a semiconductor device

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JPH08227656A (en) * 1995-02-20 1996-09-03 Merutetsukusu Kk Formation of conductive pattern for plasma display
KR20030038509A (en) * 2001-11-09 2003-05-16 신꼬오덴기 고교 가부시키가이샤 Semiconductor device manufacturing method and semiconductor device
KR100451767B1 (en) 2001-12-22 2004-10-08 주식회사 하이닉스반도체 Method for forming interconnect structures of semiconductor device
KR20050033892A (en) * 2003-10-07 2005-04-14 주식회사 하이닉스반도체 Method of forming a metal wiring in a semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101237963B1 (en) 2008-04-15 2013-02-27 삼성테크윈 주식회사 Forming method of bump for semiconductor chip

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