KR100642785B1 - Luminous chip - Google Patents

Abstract

The present invention relates to a light emitting device, comprising a plurality of circular shaped light emitting cells formed on a semiconductor substrate, a plurality of metal wires connecting the light emitting cells, and first and second electrode pads for applying power to the light emitting cells. A light emitting chip is provided. That is, by forming the shape of the light emitting cells in a circle and keeping the gap therebetween, the current density can be improved, and the light reflection emitted to the side can be reduced, and the N-type pad formed in the circular light emitting cells and By controlling the pattern of the P-type pad, it is possible to minimize the factors that hinder the radiation of the light emitted from the light emitting cells, to evenly transfer external power to the semiconductor layer, and to form a series of light emitting cells in series or parallel between the electrode pads. It can be connected and operated as flicker-free LED light source in home AC power supply without any separate circuit.

In addition, the light emitting cells may be accommodated in an LED package and coated with a phosphor to implement white light using an AC LED chip as an excitation light source.

Light emitting cell, circular shape, N type pad, P type pad, semiconductor layer, light emitting chip for AC

Description

Luminous chip

1 is a perspective view of a light emitting chip according to a first embodiment of the present invention;

2 is a plan view of a light emitting chip according to a first embodiment of the present invention;

3 is a cross-sectional view of a single cell in a light emitting chip according to a first embodiment of the present invention;

4 is a perspective view of a light emitting chip according to a second embodiment of the present invention;

5 is a cross-sectional view of a single cell in a light emitting chip according to a second embodiment of the present invention.

6 is a perspective view of a light emitting chip according to a third embodiment of the present invention;

7 is a cross-sectional view of a single cell in a light emitting chip according to a third embodiment of the present invention.

8 is a perspective view of a light emitting chip according to a fourth embodiment of the present invention;

9 is a cross-sectional view of a single cell in a light emitting chip according to a fourth embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: semiconductor substrate 20, 21, 22: N-type semiconductor layer

30: active layer 40: P-type semiconductor layer

50: N-type pad 60: P-type pad

100: light emitting cell 200: metal wiring

301 and 302: electrode pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device, and relates to a light emitting device in which a plurality of light emitting cells are connected in series and usable in direct current as well as alternating current.

A light emitting diode refers to a device that generates a small number of carriers (electrons or holes) injected using a P-N junction structure of a compound semiconductor, and emits predetermined light by recombination thereof. Such a light emitting diode is used as a display element and a backlight, and recently, research is being actively conducted to apply it to general lighting purposes.

This light emitting device using a light emitting diode is less than the conventional light bulb or fluorescent lamp, power consumption is several to several tens of times, it is superior in terms of power consumption reduction and durability.

In general, in order to use a light emitting diode for lighting, a light emitting device is formed through a separate packaging process, a plurality of individual light emitting devices are connected in series through wire bonding, and a protective circuit and an AC / DC converter are installed from the outside. Made in the form of a lamp. This conventional technology has a problem in that the size of the lamp is increased by disconnection of the wire, an external protection circuit, and an AC / DC converter in connecting a plurality of individual light emitting devices with a wire.

Accordingly, active research is being conducted on a technology of manufacturing a light emitting chip by connecting a plurality of light emitting cells in series or in parallel at a wafer level, and using a light emitting chip to manufacture a lamp that can be driven by an AC power source. However, a light emitting cell was manufactured by applying a conventional light emitting chip manufacturing process of manufacturing a light emitting chip by connecting a plurality of light emitting cells in series or in parallel at a wafer level, and then cutting individual light emitting cells into a single chip. Without manufacturing, adjacent light emitting cells were connected in series or in parallel.

The conventional light emitting cells manufactured as described above are manufactured in the shape of a substantially rectangular shape, so that the interval between each light emitting cell is narrow, and the heat of diverging is not effectively emitted to the outside. Accordingly, a problem arises in that the luminance of the light emitting chip is lowered due to light reflection between adjacent light emitting cells and loss of light emitted from the side surface is generated.

Therefore, in order to solve the above problems, the present invention provides a sufficiently wide spacing between cells when forming light emitting cells at the wafer level, and improves the brightness of light and loss of light emitted to the side by changing the shape of individual light emitting cells. It is an object of the present invention to provide a light emitting device which can prevent and reduce the thermal burden by adjacent cells.

A plurality of circular light emitting cells formed on a semiconductor substrate according to the present invention, a plurality of metal wirings connecting the circular light emitting cells and the first and second electrodes for applying power to the circular light emitting cells Provided is a light emitting chip including a pad.

In the above, a reflective metal film that reflects light is formed under the semiconductor substrate.

Here, the plurality of circular light emitting cells each include a first light emitting cell group and a second light emitting cell group connected in series, and the first and second light emitting cell groups are disposed between the first and second electrode pads. Are connected in parallel. The first light emitting cell group and the second light emitting cell group are connected through a reverse voltage preventing wiring.

In this case, the circular light emitting cell includes an N-type semiconductor layer formed in a circular shape on the semiconductor substrate, an active layer formed in a circular shape in a portion of an upper portion of the N-type semiconductor layer, and formed in a circular shape on the active layer. And a P-type semiconductor layer, an N-type pad formed on the N-type semiconductor layer, and a P-type pad formed on the P-type semiconductor layer.

A transparent photoelectrode layer such as ITO is formed on the P-type semiconductor layer. In addition, the P-type semiconductor layer is formed so that the edge of the N-type semiconductor layer is exposed. In this case, each of the N-type pad and the P-type pad is formed in a band shape surrounding at least a portion around the edge of the N-type semiconductor layer and the P-type semiconductor layer. In addition, the P-type pad is formed at the center of the P-type semiconductor layer.

In the light emitting diode according to the present invention, there is provided a light emitting diode package in which the light emitting chip according to any one of claims 1 to 5 is mounted, and a phosphor topping on the light emitting chip.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a perspective view of a light emitting chip according to a first embodiment of the present invention, and FIG. 2 is a plan view of a light emitting chip according to a first embodiment of the present invention. 3 is a cross-sectional view of a single cell in a light emitting chip according to the first embodiment of the present invention.

1 to 3, a light emitting chip according to the present invention includes a plurality of circular light emitting cells 100 formed on a semiconductor substrate 10, and first and second electrode pads 301 to which external power is input. , 301 and a plurality of metal wires 200 connecting the light emitting cells 100. In addition, a reflective metal film 400 may be further formed below the semiconductor substrate 10 to improve light reflectance. As the reflective metal film 400, a metal material film including aluminum or gold is used. Of course, the reflective metal film 400 may not be formed. In the present embodiment, the shape of the light emitting cell 100 may be formed in a circular shape to improve light emission efficiency, and the distance between the cells may be widened to reduce interference of light radiated to the side.

Sapphire or SiC substrate is used as the semiconductor substrate 10, and the shape thereof is formed in a quadrangular shape as shown in Figs. Circular first and second electrode pads 301 and 302 are disposed at opposite vertices of the quadrangular semiconductor substrate 10. Then, a plurality of circular light emitting cells 100 are arranged in a matrix on the rectangular semiconductor substrate 100. The plurality of light emitting cells 100 are separated into two series connected groups. That is, the light emitting cell group 111 is separated into a circular first light emitting cell group 111 and a circular second light emitting cell group 112. Here, the circular first light emitting cell group 111 emits light when a positive voltage is inputted to the first electrode pad 301, and the second circular light emitting cell group 112 has a second electrode pad. When positive voltage (+) is input to 302, it emits light. That is, the first and second light emitting cell groups 111 and 112 are connected in parallel between the first and second electrode pads 301 and 302.

In this embodiment, thirty-four circular light emitting cells 100 are arranged in a matrix. In this case, seventeen light emitting cells 100 are connected in series to the first and second light emitting cell groups 111 and 112, respectively.

The light emitting cell 100 includes an N-type semiconductor layer 20 formed in a circular shape on the semiconductor substrate 10, an active layer 30 formed in a circular shape on a portion of the N-type semiconductor layer 20, and P-type semiconductor layer 40 formed in a circular shape on the active layer 30, transparent electrode layer 45 formed in a circular shape on the P-type semiconductor layer 40, and the exposed N-type semiconductor layer 20 N-type pad 50 formed in a circular band shape on the (), and a P-type pad 60 formed on the transparent electrode layer 45.

In this case, the N-type semiconductor layer 20 may be formed of the first N-type semiconductor layer 21 formed on the semiconductor substrate 10 and the second N-type semiconductor layer 22 formed thereon. As shown in FIG. 3B, the second N-type semiconductor layer 22 is donut-shaped and is removed between the center and the edge to expose the lower first N-type semiconductor layer and the second N-type semiconductor at the center. The active layer 30, the P-type semiconductor layer 40, the transparent electrode layer 45, and the P-type pad 60 are formed on the layer 22, and the N-type pad ( 50) is formed. In this case, the transparent electrode layer 45 uses ITO, and the N-type pad 50 is formed at the edge of the N-type semiconductor layer 20. In this case, since the active layer 30 is formed in a circular shape, the current density (I / A) is more than doubled when compared to the square patterning, thereby improving brightness and minimizing the area occupied by the cell. In addition, the P-type pad 60 may be disposed in the center of the circular transparent electrode layer 45 to minimize the optical radiation disturbance factor. In addition, the transparent electrode layer 45 may not be formed.

Hereinafter, a manufacturing method of a light emitting chip according to the present embodiment having the above-described structure will be described.

The N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 are sequentially formed on the semiconductor substrate 10. Thereafter, a photoresist film is coated on the entire structure, and then a photovisual process using a mask is performed to form a first photoresist pattern for patterning individual cells. At this time, the shape of the cell region shielded by the first photosensitive film pattern is circular. Next, the P-type semiconductor layer 40, the active layer 30, and the N-type semiconductor layer 20 are removed through an etching process using the first photoresist pattern as an etching mask. Thereafter, the first photoresist pattern is removed to physically and electrically separate the circular light emitting cell patterns.

After the photoresist is coated on the entire structure, a photolithography process using a mask is performed to form a second photoresist pattern. The N-type semiconductor layer 20 exposed through the second photosensitive film pattern is formed in a circular band shape. That is, the second photosensitive film pattern remains in a circular shape in the center region of the separated light emitting cell pattern, and the edge region of the light emitting cell pattern is removed in a circular band shape. Next, an etching process using the second photoresist pattern as an etching mask is performed to remove the P-type semiconductor layer 40 and the active layer 20 to expose the N-type semiconductor layer 20. The second photoresist pattern is removed through a predetermined strip process. At this time, the N-type semiconductor layer may also be removed with a predetermined thickness.

A transparent electrode layer 45 using ITO is formed on the P-type semiconductor layer 40. That is, after forming the third photoresist layer pattern exposing the P-type semiconductor layer 40, the transparent electrode layer 45 is formed thereon, and the third photoresist layer pattern is removed through a stripping process, the P-type semiconductor layer 40 Is formed on the transparent electrode 45.

N-type pads 50 and P-type pads 60 are formed on the P-type semiconductor layer 40 and the N-type semiconductor layer 20, respectively. At this time, the P-type pad 60 is formed in the center of the P-type semiconductor layer 40, the N-type pad 50 is formed in a circular band shape on the edge of the exposed circular N-type semiconductor layer 20. . That is, after the photoresist is coated on the entire structure, a fourth photoresist pattern is formed to expose the edge region of the N-type semiconductor layer 20 exposed through the photolithography process and the center region of the transparent electrode 45. Thereafter, metallic conductive films such as gold, silver, platinum, aluminum, and copper are formed on the entire structure to expose the circular light emitting cell 100 having the N-type pad 50 and the P-type pad 60. To make.

The N-type pad 50 of the adjacent one light emitting cell 100 and the P-type pad 60 of the other light emitting cell 100 are connected to the metal wiring 200 through an air bridge process or a step coverage process. In the above process, the first and second electrode pads 301 and 302 are formed together, and the N-type pads 50 and the P-type pads 60 of the two light emitting cells 100 positioned at the edges of the metal wiring ( 200 to connect to the first and second electrode pads 301 and 302, respectively.

Thereafter, a reflective metal film 400 is formed under the semiconductor substrate 10. At this time, the lower surface of the semiconductor substrate 10 is cut to have a target thickness, and then the reflective metal film 400 is formed on the upper surface of the cut surface.

In the present embodiment, the manufacturing method of the circular light emitting cell is not limited thereto, and may be variously changed. That is, the N-type semiconductor layer 20 may be formed in two layers.

Of course, in the above-described fabrication method, the cells are separated and then the N-type semiconductor layer 20 is exposed. In the present description, the first and second N-type semiconductor layers 21 and 22 are patterned and exposed, and then the cells are separated. do. The above-mentioned methods are not limited to each description, but can be applied in parallel with each other.

Thereafter, the transparent electrode layer 45 and the P-type pad 60 are formed on the P-type semiconductor layer 40, and the N-type pad 50 is formed on the second N-type semiconductor layer 22.

 In addition, the present invention is not limited thereto, and the shape of the N-type pad and the P-type pad may be variously changed. Hereinafter, a second embodiment of the present invention in which an N-type pad is formed in a portion of the edge of a circular light emitting cell and a P-type pad is also formed in the edge region of a P-type semiconductor layer will be described with reference to the drawings. In the following embodiment, a description overlapping with the first embodiment described above will be omitted.

4 is a perspective view of a light emitting chip according to a second embodiment of the present invention. 5 is a cross-sectional view of a single cell in a light emitting chip according to a second embodiment of the present invention.

4 and 5, the light emitting chip according to the present embodiment includes a plurality of circular light emitting cells 100 formed on the semiconductor substrate 10, and first and second electrode pads to which external power is input. 301 and 301 and a plurality of metal wires 200 connecting the light emitting cells 100.

The light emitting cell 100 includes an N-type semiconductor layer 20 formed in a circular shape on the semiconductor substrate 10, an active layer 30 formed in a circular shape on a portion of the N-type semiconductor layer 20, and P-type semiconductor layer 40 formed in a circular shape on the active layer 30, transparent electrode layer 45 formed in a circular shape on the P-type semiconductor layer 40, and the exposed N-type semiconductor layer 20 N-type pad 50 formed on a portion of the edge on the (), and a P-type pad 60 formed on a portion of the edge on the transparent electrode layer 45. That is, as shown in FIG. 4, the N-type pad 50 of the one-shaped light emitting cell 100 is located in an area adjacent to the P-type pad 60 of the elliptic light emitting cell 100 to be connected thereto. Is formed. The P-type pad 60 of the circular light emitting cell 100 is formed in an area adjacent to the N-type pad 50 of the elliptic light emitting cell 100 connected thereto. This can reduce the length of the metal wiring connecting them and improve the luminous efficiency of the chip. In addition, the N-type pad 50 and the P-type pad 60 of the circular light emitting cells 100 adjacent to the first and second electrode pads 301 and 302 may have the first and second electrode pads 301 and 302. ) Is formed in the adjacent area. In addition, a separate metal electrode connected to the P-type semiconductor layer 40 may be further formed at a portion of the edges on the first and second electrode pads 301 and 302.

At this time, the N-type pad 50 and the P-type semiconductor of the elliptic light-emitting cell 100 formed on a portion of the edge of the N-type semiconductor layer 20 of the circular-shaped light emitting cell 100 through the metal wiring 200. P-type pads 40 formed on a portion of the edge of layer 40 are electrically connected.

Here, the N-type pad 50 and the P-type pad 60 has a band shape surrounding the edges of the exposed N-type semiconductor layer 50 and the P-type semiconductor layer 40 by 15 to 85%, and the edge It is desirable to enclose around 25-50% of the circumference. This can reduce the factors that prevent the emission of light.

In addition, as illustrated in FIGS. 5A and 5B, the N-type pad 50 and the P-type pad 60 formed on the single circular light emitting cell 100 may include a plurality of light emitting cells 100. The distances may be adjacent or separated to facilitate serial connection between them.

In addition, in the present invention, a P-type pad for evenly applying power to the P-type semiconductor layer may be formed in a band shape in the edge region of the P-type semiconductor layer. Such a third embodiment of the present invention will be described with reference to the drawings. In the following embodiment, a description overlapping with the above-described first and second embodiments will be omitted.

6 is a perspective view of a light emitting chip according to a third embodiment of the present invention. 7 is a cross-sectional view of a single cell in a light emitting chip according to a third embodiment of the present invention.

6 and 7, the light emitting chip according to the present embodiment includes a plurality of circular light emitting cells 100 formed on the semiconductor substrate 10, and first and second electrode pads receiving external power. 301 and 301 and a plurality of metal wires 200 connecting between the circular light emitting cells 100.

Here, the circular light emitting cell 100 has an N-type semiconductor layer 20 formed in a circular shape on the semiconductor substrate 10 and an active layer 30 formed in a circular shape on a part of the upper portion of the N-type semiconductor layer 20. ), A P-type semiconductor layer 40 formed in a circular shape on the active layer 30, a transparent electrode layer 45 formed in a circular shape on the P-type semiconductor layer 40, and the exposed N-type semiconductor. An N-type pad 50 formed at a portion of the edge on the layer 20 and a circular band-shaped P-type pad 60 surrounding the edge on the transparent electrode layer 45 are included. That is, as shown in FIG. 6, the N-type pad 50 of the one-shaped light emitting cell 100 is located in an area adjacent to the P-type pad 60 of the elliptic light emitting cell 100 to be connected thereto. Is formed.

As such, the P-type pad 60 having a shape surrounding the P-type semiconductor layer 40 can be formed to apply current evenly to the P-type semiconductor layer 40, thereby improving the electrical / optical performance of the device. have.

In addition, according to the present invention, the N-type pad and the P-type pad respectively surround the N-type semiconductor layer and the P-type semiconductor layer so that external power is evenly applied to the semiconductor layer. This fourth embodiment of the present invention will be described with reference to the drawings. In the following embodiments, descriptions overlapping with those of the first to third embodiments described above will be omitted.

8 is a perspective view of a light emitting chip according to a fourth embodiment of the present invention. 9 is a cross-sectional view of a single cell in a light emitting chip according to a fourth embodiment of the present invention.

8 and 9, the light emitting chip according to the present embodiment includes a plurality of circular light emitting cells 100 formed on the semiconductor substrate 10, and first and second electrode pads receiving external power. 301 and 301 and a plurality of metal wires 200 connecting between the circular light emitting cells 100.

Here, the circular light emitting cell 100 has an N-type semiconductor layer 20 formed in a circular shape on the semiconductor substrate 10 and an active layer 30 formed in a circular shape on a part of the upper portion of the N-type semiconductor layer 20. ), A P-type semiconductor layer 40 formed in a circular shape on the active layer 30, a transparent electrode layer 45 formed in a circular shape on the P-type semiconductor layer 40, and the exposed N-type semiconductor. A circular strip-shaped N-type pad 50 surrounding the edge on the layer 20 and a circular strip-shaped P-type pad 60 surrounding the edge on the transparent electrode layer 45 are included. That is, as shown in FIG. 8, the N-type pad 50 of the one-shaped light emitting cell 100 is located in an area adjacent to the P-type pad 60 of the elliptic light emitting cell 100 to be connected thereto. Is formed.

As described above, an N-type pad having a shape surrounding the N-type semiconductor layer may be formed to apply current evenly to the N-type semiconductor layer, and the P-type pad 60 having a shape surrounding the P-type semiconductor layer 40 may be wrapped around the edge. It is possible to apply the current evenly to the P-type semiconductor layer 40 by forming a can improve the electrical / optical performance of the device, when connecting the N-type pad and the P-type pad by metal wiring, the connection range is limited Can be reduced.

In addition, the present invention can reduce the total voltage by electrically connecting a portion of the adjacent first and second cell groups. This fifth embodiment of the present invention will be described with reference to the drawings. In the following embodiments, descriptions overlapping with those of the first to fourth embodiments described above will be omitted.

10 is a perspective view of a light emitting chip according to a fifth embodiment of the present invention. 11 is a plan view of a light emitting chip according to a fifth embodiment of the present invention. 12 is an equivalent circuit diagram of a light emitting chip according to a fifth embodiment.

10 to 12, the light emitting chip according to the present embodiment includes a plurality of circular light emitting cells 100 arranged in a matrix on a semiconductor substrate 10, and first and second electrode pads receiving external power. 301 and 301 and the light emitting cell 100 are divided into a first light emitting cell group 111 and a second light emitting cell group 112 connected in series, respectively, and the first and second light emitting cell groups 111 are respectively connected. , A plurality of metal wires 200 connecting the first and second electrode pads 301 and 302, the metal wires 200 and the second light emitting cells of the first light emitting cell group 111. And reverse voltage preventing wirings 510, 520, and 530 connecting the metal lines 200 of the group 112.

In the present exemplary embodiment, circular first and second electrode pads 301 and 302 are disposed at opposite vertices of the rectangular semiconductor substrate 10. The plurality of light emitting cells 100 are separated into two series connected groups by the metal wire 200. That is, the first light emitting cell group 111 and the second light emitting cell group 112 are formed in a circular shape, and some of them are divided again through the reverse voltage preventing wirings 510, 520, and 530.

That is, as shown in the equivalent circuit of the present embodiment, the plurality of series-connected first and second light emitting cell groups 111 and 112 are part of both light emitting cell groups by the reverse voltage preventing wirings 510, 520, and 530. Are connected and a part thereof is connected in parallel. That is, a plurality of groups (see A, B, C, and D of FIG. 12) in which the first and second light emitting cell groups 111 and 112 connected in series by the reverse voltage preventing wirings 510, 520, and 530 are connected in parallel. ), And a plurality of groups A, B, C, and D connected in parallel are connected in series.

In the present embodiment, as shown in FIGS. 10 and 11, 18 circular light emitting cells 100 are arranged in a matrix, and the first and second light emitting cell groups 111 and 112 are each of 14 light emitting cells ( 100 is connected in series. In addition, the thirteen metal wires 200, the light emitting cell groups 111 and 112, and the first and second electrode pads 301 are connected to connect the light emitting cells 100 in the light emitting cell groups 111 and 112. , 302 consists of two metal wires (200) for connecting. In addition, the metal wires 200 of the first and second light emitting cell groups 111 and 112 are connected to each other through the three reverse voltage preventing wirings 510, 520, and 530.

 In this case, when the metal wires 200 sequentially connecting the first electrode pads 301 to the light emitting cells 110 are sequentially numbered, the fourth metal wires 200 of the first light emitting cell group 111 may be numbered. And the fourth metal wiring 100 of the second light emitting cell group 112 are connected through the first reverse voltage preventing wiring 510. The seventh metal wiring 200 of the first light emitting cell group 111 and the ninth metal wiring 200 of the second light emitting cell group 112 are connected through the second reverse voltage preventing wiring 520. In addition, the twelfth metal wiring 200 of the first light emitting cell group 111 and the twelfth metal wiring 200 of the second light emitting cell group 112 are connected through the third reverse voltage preventing wiring 530.

In this case, when there is no reverse voltage preventing wirings 510, 520, and 530 connecting the middles of the first and second light emitting cell blocks 111 and 112 connected in series, a VR (reverse voltage) problem, which is VF × 14 times, occurs. However, as described above, every three to five light emitting cells in the first and second light emitting cell groups 111 and 112 are intermediate by using reverse voltage preventing wirings 510, 520, and 530 on the bottom layer where there is no light path. By making the connection, the VF × 14 VRs alleviate the impact on the opposite light emitting cell group. That is, the reverse voltage applied in one direction is lowered from (3/14) x VR to (5/14) x VR depending on the number of intermediate connections, so that the impact of the capacitance due to VR at the PN junction of the light emitting cell 100 is reduced. Leads to a decrease in current. For example, when VF is 3.4V, VR = VF × 14 = 3.4V × 14 = 47.6V. However, when the reverse voltage preventing wiring according to the present embodiment is connected, VR is securely applied at (3/14) × 47.6V to (5/14) × 47.6V, that is, 10.2 to 17.0V.

The reverse voltage preventing wirings 510, 520, and 530, which are intermediate connections, are formed in the middle of the first and second light emitting cell groups 111 and 112 arranged in series, thereby reducing the reverse voltage applied to the opposite light emitting cell groups. Can be.

The light emitting diode can be manufactured using the light emitting chip of the above-described embodiment.

The light emitting chip according to the first to fifth embodiments described above may be mounted in a light emitting diode package, and then a light emitting diode having white light may be implemented by topping a phosphor thereon.

The light emitting chip described above is mounted on a light emitting diode package including a PCB substrate, a metal slug, a metal substrate, a lead frame, a heat sink, and the like, and is connected to an electrode using a wire. Thereafter, a thin coating of the phosphor on the light emitting chip is formed, and then a molding part encapsulating the light emitting chip is formed. Here, as the phosphor, a phosphor having a garnet structure or a silicate structure is used, and various kinds of phosphors may be used as long as the phosphor emits light of a desired color by converting a wavelength of light emitted by a light emitting chip. For example, a white YAG: Ce phosphor is ported on a light emitting chip emitting blue light.

As described above, the present invention forms the shape of the light emitting cells in a circular shape and maintains a constant gap therebetween, thereby improving current density and reducing light reflection emitted to the side, compared to the square light emitting cells. The thermal stress due to the heat emitted by the individual light emitting cells can be reduced.

In addition, by controlling the pattern of the N-type pad and P-type pad formed in the circular light emitting cell, it is possible to minimize the factors that interfere with the radiation of the light emitted by the light emitting cell, and to evenly transmit external power to the semiconductor layer. have.

In addition, the circular light emitting cells may be connected in series or in parallel between the electrode pads to operate as a flicker-free LED light source in a domestic AC power supply without a separate circuit.

In addition, when power is applied to one end of the light emitting cells arranged in series, the reverse voltage applied to the opposite end of the light emitting cells can be reduced.

Claims (10)

A plurality of light emitting cells in which a circular N-type semiconductor layer formed on a semiconductor substrate, an active layer formed in a partial region on the N-type semiconductor layer, and a circular P-type semiconductor layer are formed on the active layer; First and second electrode pads provided on N-type and P-type semiconductor layers of the plurality of light emitting cells; And A light emitting chip comprising a plurality of metal wires connecting the plurality of light emitting cells. The method according to claim 1, A light emitting chip having a reflective metal film formed under light of the semiconductor substrate. The method according to claim 1, The plurality of circular light emitting cells each include a first light emitting cell group and a second light emitting cell group connected in series, and the first and second light emitting cell groups are connected in parallel between the first and second electrode pads. Luminous chip. The method according to claim 3, And the first light emitting cell group and the second light emitting cell group are connected through a reverse voltage preventing wiring. delete The method according to claim 1, A light emitting chip having a transparent electrode layer such as ITO formed on the P-type semiconductor layer. The method according to claim 1, The P-type semiconductor layer is a light emitting chip formed so that the edge of the N-type semiconductor layer is exposed. The method according to claim 1, Each of the first and second electrode pads is formed in a band shape surrounding at least a portion around edges of the N-type semiconductor layer and the P-type semiconductor layer. The method according to claim 1, The second electrode pad is a light emitting chip formed in the center of the P-type semiconductor layer. delete

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