KR100649222B1 - Light emitting display apparatus and driving device and method thereof - Google Patents

Abstract

In a current write type organic electroluminescent display, the data line is precharged with a precharge current before data is written to the first pixel connected to the first scan line. A precharge current is distributed and transferred to a plurality of second pixels connected to second scan lines other than the first pixel to which data is to be written, and the data lines are precharged, and the precharge operation is performed by precharging pulses of the first scan line and the second scan line. Is performed when passed to A selection pulse is applied to the next first scan line to perform a data write operation. Here, the selection signal applied to the first scan line has a plurality of precharge pulses and selection pulses. The precharge pulse is generated in a period where the level of the first signal having the high level and the low level at regular intervals is different from the level of the second signal from which the first signal is moved by the precharge period.

Organic EL, Light Emitting, Precharge, Current Write, Shift Register, Flip-Flop

Description

LIGHT EMITTING DISPLAY APPARATUS AND DRIVING DEVICE AND METHOD THEREOF}

1 is a graph illustrating a change in data writing time for each gray level in a conventional light emitting display device.

2 is a schematic plan view of a light emitting display device according to a first embodiment of the present invention.

3 is a circuit diagram of a pixel of a light emitting display device according to a first embodiment of the present invention.

4 is a driving timing diagram of a light emitting display device according to a first embodiment of the present invention.

5A is a diagram illustrating a state in which a current is supplied in a precharge step.

5B is a diagram illustrating a state in which a current is supplied in the data writing step.

6 is a diagram illustrating a scan driver in a light emitting display device according to a second embodiment of the present invention.

7 is a signal timing diagram of a scan driver in accordance with a third embodiment of the present invention.

FIG. 8 is a schematic circuit diagram of a first or second shift register used in the scan driver of FIG. 6.

9 is a schematic circuit diagram of a third shift register used in the scan driver of FIG. 6.

10 is a timing diagram of an output signal of a flip-flop and an output signal of a NOR gate used in the shift register of FIG. 9.

11A and 11B are schematic diagrams of flip-flops used in the shift registers of FIGS. 9 and 8, respectively.

12 is a signal timing diagram of a scan driver in accordance with a third embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device, a driving device and a driving method thereof, and more particularly, to a light emitting display device using electroluminescence (hereinafter, referred to as "organic EL") of an organic material.

In general, an organic EL display device is a display device for electrically exciting a fluorescent organic compound to emit light, and is capable of displaying an image by driving a plurality of organic light emitting cells by voltage driving or current driving. The organic light emitting cell has a structure of an anode, an organic thin film, and a cathode layer. The organic thin film has a multilayer structure including an emission layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) in order to improve the emission efficiency by improving the balance between electrons and holes. It may also include a separate electron injection layer (EIL) and a hole injection layer (HIL).

As such a method of driving the organic light emitting cell, there is a simple matrix method and an active driving method using a thin film transistor. In the simple matrix method, the anode and the cathode are orthogonal and the line is selected and driven, whereas the active driving method is a thin film transistor connected to each pixel electrode, and the voltage maintained by the capacitor of the capacitor connected to the gate of the thin film transistor. It is a way to drive. At this time, the active driving method is divided into a voltage writing method and a current writing method according to the type of signal applied to set the voltage to the capacitor.

In the conventional voltage write type pixel circuit, there is a problem in that it is difficult to obtain a high gradation due to variation in the threshold voltage of the thin film transistor and the mobility of the carrier caused by the nonuniformity of the manufacturing process. For example, when driving a thin film transistor of a pixel at 3 V, a voltage must be applied to a gate of the thin film transistor at intervals of 12 mV (= 3 V / 256) or less in order to express an 8-bit 256 gray level. When the variation in the threshold voltage of the thin film transistor due to unevenness is 100 Hz, it is difficult to express high gray scale.

On the contrary, in the pixel circuit of the current write method, if the current source for supplying the current to the pixel circuit is uniform through the panel, even if the driving transistors in each pixel have non-uniform voltage-current characteristics, uniform display characteristics can be obtained.

However, in the current write type pixel circuit, the data write time is long because of the parasitic capacitance present in the data line. Specifically, the time (data writing time) for writing data to the current pixel line is affected by the voltage state of the data line according to the data of the previous pixel line, and in particular, the data line is a target voltage (voltage corresponding to the current data). The data writing time becomes longer when the difference is charged with a large voltage. This phenomenon appears larger as the gray level is lower (near black). 1 is a graph illustrating a change in data writing time for each gray level in a conventional light emitting display device. 1, time t1 to t7 represent the data writing time, and the legend on the right side of the graph represents the gradation level of data written to the pixel circuit connected to the previous pixel line.

For example, when the gradation level of the data written in the pixel circuit connected to the previous pixel line is "8", when the gradation level of the data to be written in the pixel circuit connected to the current pixel line is 8 (the point where the curve is in contact with the horizontal axis). Since the voltage state of the data line does not differ from the target voltage, the time required for data writing becomes almost " 0 ".

However, as the gradation level of the data to be written currently becomes farther from 8, the voltage state of the data line becomes larger than the target voltage, so that the time required for data writing increases. On the other hand, the time required for data writing is inversely proportional to the magnitude of the data current driving the data line. Therefore, when the gradation level is lowered, the data current for driving the data line also becomes smaller, so that the data writing time increases rapidly. That is, as shown in Fig. 1, the lower the gradation level (near the black level), the higher the data write time is because the data line voltage is changed to a larger voltage range at a lower current.

An object of the present invention is to reduce the data write time in the current driving type light emitting display device.

According to an aspect of the present invention, there is provided an apparatus for driving a light emitting display device including a plurality of scan lines extending in one direction and transmitting a selection signal, wherein the selection signal is a first pulse of a first integer number of first levels. And a second pulse of the first level. The driving apparatus of the present invention includes a first driver for outputting a first signal having at least one third pulse of a second level, and a second having a fourth pulse in which the at least one third pulse is moved by a first period. A second driver for outputting a signal, a third driver for outputting a third signal having a fifth pulse of a third level in a period in which a signal level of the first signal and the second signal is different, and the third signal of the third signal And a fourth driver configured to generate the first pulse in response to the fifth pulse.

According to one embodiment of the invention, the first period is substantially equal to the width of the first pulse.

According to another embodiment of the present invention, when there are a plurality of third pulses, a period of a fourth level between two adjacent third pulses is substantially equal to the width of the third pulse.

According to another embodiment of the invention, the first period is shorter than the width of the third pulse.

According to another embodiment of the present invention, the driving device of the present invention further includes a fifth driver for outputting a fourth signal having a sixth pulse corresponding to the second pulse, wherein the fourth driver is the first driver. The selection signal is output in response to the fifth pulse of three signals and the sixth pulse of the fourth signal.

According to another embodiment of the present invention, the start time point of the sixth pulse of the fourth signal is shifted by a second integer multiple of the width of the third pulse relative to the start time point of the fifth pulse of the third signal. It is. In this case, the second integer may correspond to a value obtained by subtracting 1 from twice the first integer or twice the first integer.

According to another feature of the present invention, a plurality of data lines extending in one direction and transmitting data signals, a plurality of scanning lines extending in a direction crossing the data lines, and a plurality of pixels connected to the data lines and the scanning lines, respectively A display area including a display area and a scan driver configured to apply a selection signal having at least one first pulse of a first level and a second pulse of the first level to the plurality of scan lines are provided.

According to still another aspect of the present invention, a method of driving a light emitting display device including a plurality of scan lines extending in one direction and transmitting a selection signal is provided. The driving method of the present invention may include outputting a first signal having at least one first pulse of a first level, having at least one second pulse of the first level, and a starting time point of the second pulse being the first signal; Outputting a second signal shifted by a predetermined period with respect to a start point of one pulse; a third having a third pulse of a third level in at least one period in which the levels of the first signal and the second signal are different from each other; Outputting a signal, and generating at least one fourth pulse in response to each of the at least one third pulse of the third signal, and outputting the selection signal having the at least one fourth pulse; Include.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a direct connection but also an indirect connection between other elements in between.

A light emitting display device and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings. In the embodiment of the present invention, the organic EL display device is described as an example of the light emitting display device, but the present invention is not limited thereto.

First, a light emitting display device according to a first exemplary embodiment of the present invention will be described in detail with reference to FIG. 2. 2 is a schematic plan view of a light emitting display device according to a first embodiment of the present invention.

As shown in FIG. 2, the light emitting display device according to the first embodiment of the present invention includes a display panel 100, a data driver 200, a scan driver 300, and a light emission control driver 400.

The display panel 100 includes a plurality of data lines Y _{1 to} Y _n extending in the vertical direction, a plurality of selection signal lines X _{1 to} X _m extending in the horizontal direction, and a plurality of light emitting scan lines Z _{1 to} Z _m. ) And a plurality of pixel circuits 110. The selection scan lines X _{1 to} X _m transmit a selection signal for selecting pixels, and the emission scan lines Z _{1 to} Z _m transmit a light emission signal for controlling the light emission period of the organic EL element. The pixel circuit 110 is formed in the pixel region defined by the data lines Y _{1 to} Y _n and the selection scan lines X _{1 to} X _m .

The data driver 200 is to precharge the data line data line (Y ₁ ~Y _n) applied to the data current (I _DATA) in the (Y ₁ ~Y _n), and also prior to applying the data current (I _DATA) For this reason, the precharge current NI _{DATA which} is N times larger than the data current I _DATA is applied to the data lines Y _{1 to} Y _n . To this end, the data driver 200 includes a current source for generating data current I _DATA and a current source for generating precharge current NI _DATA . The precharge current NI _DATA may be generated from the data current I _DATA through a current mirror circuit and the like, and thus the detailed description thereof will be omitted since the current generation process is obvious to those skilled in the art. Meanwhile, the data driver 200 selectively selects the precharge current NI _DATA and the data current I _DATA according to a control signal applied from an external controller (not shown), and transmits the data lines Y _{1 to} Y _n . To supply.

The scan driver 300 sequentially applies a selection signal for selecting the pixel circuit 110 to the selection scan lines X _{1 to} X _m , and the emission control driver 400 controls the light emission of the pixel circuit 110. Are sequentially applied to the emission scanning lines Z _{1 to} Z _m .

The scan driver 300, the emission control driver 400, and / or the data driver 200 may be electrically connected to the display panel 100, or may be attached to the display panel 100 and electrically connected to the tape carrier package. tape carrier package, TCP) or the like in the form of a chip. Alternatively, the display panel 100 may be mounted in a flexible printed circuit (FPC) or a film that is adhered to and electrically connected to the display panel 100 in the form of a chip. Alternatively, the scan driver 300, the emission control driver 400, and / or the data driver 200 may be directly mounted on the glass substrate of the display panel, and may be formed of the same layers as the scan line, the data line, and the thin film transistor on the glass substrate. It may be replaced with the driving circuit formed.

According to the first embodiment of the present invention, before applying the data current I _DATA to the pixel circuit connected to the data line Y _j and the selection scan line X _i , the pre-corresponds to N times the data current I _DATA . The charge current NI _DATA is applied to the data line Y _j . When the precharge current NI _DATA is applied to the data line Y _j , the pixel circuit connected to the selection scan line X _i and the selection scan lines of (N-1) pixel circuits adjacent to the pixel circuit in the vertical direction. The low level select signal is simultaneously applied to (X _{i + 1 to} X _{i + N-1} ). Next, only the selection signal applied to the selection scan line X _i is kept at the low level and the data current I _DATA is applied to the data line Y _j . In this form of the invention, the data current (I _DATA) the data current (I _DATA) to the data line (Y _j) the data line (Y _j) after the fast pre-charge to a desired voltage by a larger charge current (NI _DATA) is Since the voltage is applied to the pixel circuit, the voltage corresponding to the data current I _DATA may be quickly transmitted and charged.

Hereinafter, operations of the light emitting display device according to the first embodiment of the present invention will be described in detail with reference to FIGS. 3, 4, 5A, and 5B. For convenience of explanation, it is assumed that N is 5, that is, the precharge current is 5 times the data current.

First, the pixel circuit 110 of the light emitting display device according to the first embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a circuit diagram of a pixel circuit according to a first embodiment of the present invention. 3 illustrates a pixel circuit connected to the j th data line Y _j , the i th selected scan line X _i , and the emission scan line Z _i .

As shown in FIG. 3, the pixel circuit 110 according to the first embodiment of the present invention includes an organic EL element OLED, four transistors T1 to T4, and a capacitor C. As shown in FIG. Although transistors T1 to T4 are shown as PMOS transistors in FIG. 3, the present invention is not limited thereto. The transistor may be formed as a thin film transistor having a gate electrode, a drain electrode, and a source electrode formed on the glass substrate of the display panel 100 as a control electrode and two main electrodes, respectively.

Specifically, the transistor T1 has its three terminals connected to the selection scan line X _i , the data line Y _j , and the gate of the transistor T3, respectively, in response to a selection signal from the selection scan line X _i . The data current I _DATA from the data line Y _j is transferred to the gate of the transistor T3. The transistor T3 has a source connected to a power supply voltage VDD, and a capacitor C for storing a voltage between the gate and the source is connected. The transistor T2 is connected between the drain of the transistor T3 and the data line Y _j , and the transistors T1 and T2 diode diode T3 in response to a selection signal from the selection scan line X _i . Connect. This transistor T2 may be directly connected between the gate and the drain of the transistor T3.

At this time, the data current I _DATA is applied to the data line Y _j , and the selection signal (select [1] in FIG. 4) from the selection scan line X _i is at a low level so that the transistors T1 and T2 are turned on. In this case, the transistor T3 is in a diode-connected state. Then, a current flows in the capacitor C, the voltage is charged, and the gate potential of the transistor T3 decreases, so that a current flows from the source to the drain. When the charging voltage of the capacitor C becomes high as time passes and the drain current of the transistor T3 becomes equal to the data current I _DATA , the charging current of the capacitor C is stopped to stabilize the charging voltage. Therefore, the voltage corresponding to the data current I _DATA from the data line Y _j is stored in the capacitor C.

Next, the selection signal (select [1] in FIG. 4) from the selection scan line X _i becomes high level and the emission signal (emitter [1] in FIG. 4) from light emission scan line Z _i becomes low level. . Then, the transistors T1 and T2 are turned off and the transistor T4 connected between the transistor T3 and the organic EL element OLED is turned on to transfer current from the transistor T3 to the organic EL element OLED. The cathode of the organic EL element OLED is connected to a voltage VSS lower than the power supply voltage VDD, and the organic EL element OLED emits light corresponding to the current supplied through the transistor T4. The current I _OLED transmitted to the organic EL element _OLED is represented by Equation 1 according to the voltage charged in the capacitor C of the transistor T3.

Here, V _GS is a voltage between the gate and the source of the transistor T3, V _TH is the threshold voltage of the transistor T3, and β represents a constant value.

Next, operations of the light emitting display device according to the first embodiment of the present invention will be described in detail with reference to FIGS. 4, 5A, and 5B.

4 is a driving timing diagram of a light emitting display device according to a first embodiment of the present invention. FIG. 5A is a diagram illustrating a state in which a current is supplied in a precharge step, and FIG. 5B is a diagram illustrating a state in which a current is supplied in a data writing step. In Figures 5a and 5b are shown only five pixel circuit coupled to for convenience first to fifth selection scan lines (X ₁ ~X ₅₎ and the light emitting scan lines (Z ₁ ~Z ₅₎ of the description. 4, 5A, and 5B, the selection signal applied to the selection scan line X _i is represented by select [i], and the emission signal applied to the emission scan line Z _i is represented by emit [i]. The reference numerals X _i and Z _i corresponding to the light emission scan lines are omitted.

, First if you wish to write data to the pixel circuit coupled to the second selection scan line (X _1), the first selection signal of the first second to fifth selection scan lines (X ₁ ~X ₅₎ low level (select as shown in Figure 4. [ 1] to select [5]) are supplied, and at the same time, the data driver 200 applies a precharge current 5I _DATA to the data line Y _j to perform a precharge operation during the precharge period Tp. .

Transistors T1 and T2 of the pixel circuit 110 connected to the selection scan lines X _{1 to} X ₅ are turned on in response to the low-level selection signals select [1] to select [5] to turn on the transistor T3. The diode is connected. Accordingly, as shown in FIG. 5A, the precharge current 5I _DATA flows along the data line Y _j . At this time, if the ratio (W / L, hereinafter referred to as "transistor size") of the channel width W and the channel length L of the transistors T3 of the five pixel circuits is the same, from the data line Y _j The precharge current of 5I _DATA is delivered to each pixel circuit by 1/5. That is, the data current I _DATA is transmitted to each of the five pixel circuits. Then, the voltage V _GS corresponding to Equation 1 is charged in the capacitor C. That is, the precharge voltage corresponding to the gate voltage V _G is applied to the data line Y _{j in} the gate-source voltage V _GS of the transistor T3. The precharge voltage may not be a voltage that should actually be applied to the data line Y _j by the data current I _DATA if the length of the precharge period Tp is short. However, since the magnitude of the precharge current (5I _DATA) larger than the data current (I _DATA) voltage close to the voltage of the precharge period (Tp) corresponding to the shorter data lines a data current (I _DATA) to (Y _j) This can take

Next, as shown in FIG. 4, only the select signal select [1] applied to the first select scan line X ₁ is kept at a low level, and the remaining select signals select [2] to select [5] are high. Change to level. At the same time, the data driver 200 applies a data current I _DATA , that is, a current corresponding to 1/5 times the precharge current 5I _DATA to the data line Y _j . Then, as shown in FIG. 5B, only transistors T1 and T2 of the pixel circuit connected to the first selection scan line X ₁ are turned on to transmit the data current I _DATA to the transistor T3. Therefore, a voltage corresponding to the data current I _DATA is charged in the capacitor C of the pixel circuit connected to the first selection scan line X ₁ to perform a data writing operation. At this time, since the precharge voltage (the voltage close to the voltage corresponding to the data current I _DATA ) is applied to the data line Y _j according to the previous precharge operation, the capacitor C is connected to the data current I _DATA . The corresponding voltage can be charged quickly.

Thereafter, when data writing is completed, the selection signal select [1] is also at a high level so that the transistors T1 and T2 are turned off, and the low level emission signal emit [1] applied from the emission scan line Z ₁ . Transistor T4 is turned on. Then, the current I _OLED from the transistor T3 is supplied to the organic EL element _OLED through the transistor T4, and the organic EL element OLED emits light corresponding to the current I _OLED .

Thus, applying the first selection scan line (X ₁₎ at the same time that this light-emitting operation of the pixel circuit is performed, the selection scan line (X ₂ ~X ₆₎ the selection signal (select [2] ~select [6 ]) connected to a low level in And a precharge current 5I _DATA corresponding to five times the data current I _DATA corresponding to the pixel circuit connected to the selection scan line X ₂ is applied to the data line Y _j , whereby the second selection scan line X is applied. _A precharge operation is performed on the pixel circuit connected to ₂ ). After the precharge operation, the selection signals select [3] to select [6] become high levels, and the data current I _DATA corresponding to the pixel circuit connected to the selection scan line X ₂ is the data line Y _j. ) Is applied to the pixel circuit connected to the second selection scan line X ₂ to perform a data write operation.

In this way, in the first embodiment of the present invention, before writing data to the pixel circuit connected to the i-th selection scan line X _i , the i-th to (i + N-1) th selection scan lines X _{i to} X _{i +. N-1} ) while applying the selection signal, the precharge current NI _DATA corresponding to N times the data current I _DATA is applied. Then, if the transistors T3 of the pixel circuits adjacent in the vertical direction are the same in size, the current corresponding to 1 / N of the precharge current NI _DATA is in the i-th to (i + N-1) th selective scan lines X _i to The precharge operation is performed by transferring to the N pixel circuits connected to X _{i + N-1} ). Next, in the state where the selection signal of the i-th selection scan line X _i is set at the low level, the (i + 1) th to (i + N-1) th selection scan lines X _{i + 1 to} X _{i + N-1} . The data write operation is performed by applying the data current I _DATA to the data line Y _j while keeping the select signal of.

As described above, in the first embodiment of the present invention, data can be written within a given time by precharging the data line with a precharge current larger than the data current.

In the following, in the selection signal select [i] of FIG. 4, a pulse having a low level only during the precharge period is referred to as a “precharge pulse” and a pulse having a low level during the precharge period and the data writing period is referred to as a “select pulse”. do. Then, as shown in FIG. 4, the selection signal select [i] applied to the selection scan line X _i has one selection pulse and at least one precharge pulse per cycle. This selection signal select [i] has the same interval between the start time of two adjacent precharge pulses and the start time of the selection pulse and the precharge pulse adjacent to this selection pulse and is free in addition to the pixel into which data is written. The number of pixels used for charge may be generated to have precharge pulses. The precharge period Tp is equal to the width of the precharge pulse.

Hereinafter, a driving unit for generating such a driving waveform will be described in detail with reference to FIGS. 6 to 12.

6 is a diagram illustrating a scan driver 300 according to a second embodiment of the present invention, and FIG. 7 is a signal timing diagram of the scan driver according to a second embodiment of the present invention.

As shown in FIG. 6, the scan driver 300 according to the third embodiment of the present invention includes three shift registers 310, 320, and 330, a plurality of exclusive OR gates XOR _{1 to} XOR _m , and A plurality of NOR gates NOR _{11 to} NOR _1m are included. 6 and 7, it is assumed that the outputs of the shift registers 310, 320, and 330 are m corresponding to the number of the selection scan lines X _{1 to} X _m , and the XOR gates XOR _{1 to} XOR _m and the NOR gates. It is also assumed that (NOR _{11 to} NOR _1m ) are also m each. For convenience of description, in FIG. 6 and FIG. 7, four neighboring pixel circuits are used when precharging the pixel circuits for data writing, so that the selection signal select [i] has four precharge pulses. Assume that

As shown in Figs. 6 and 7, the shift register 310 receives the clock VCLK1 and the start signal VSP1 to shift the output signals out1 [1] to out1 [m] by one clock VCLK1. Outputs sequentially. The output signal out1 [i] has two high level pulses for one period, the high level pulses having a width equal to the period Tc1 of the clock VCLK1 and the period of the period Tc1 of the clock VCLK1. Equal to 2 times, where i is an integer between 1 and m.

The shift register 320 receives the clock VCLK2 and the start signal VSP2 and sequentially outputs the output signals out2 [1] to out2 [m] by one clock VCLK2. The clock VCLK2 has the same period Tc1 as the clock VCLK1 and is shifted by a predetermined period Tp with respect to the clock VCLK1. The output signal out2 [i] also has two high level pulses for one period, the width of which is equal to the period of the clock VCLK2 and the period equal to twice the period of the clock VCLK2 ( Where i is an integer between 1 and m). The output signal out2 [i] of the shift register 320 is a signal shifted by the predetermined period Tp with respect to the output signal out1 [i] of the shift register 310, and this constant period Tp is It is the same as the precharge period in FIG. That is, the precharge period is determined by the Tp period.

The XOR gates XOR _{1 to} XOR _m are the output signals out1 [1] to out1 [m] of the shift register 310 and the output signals out2 [1] to out2 [m] of the shift register 320, respectively. XOR operation to output the output signals scan1 [1] to scan1 [m]. The output signal scan1 [i] becomes a high level when only one of the two output signals out1 [i] and out2 [i] is high level by an XOR operation. Since the output signal out2 [i] is shifted by the Tp period with respect to the output signal out1 [i], if this Tp period is shorter than one clock VCLK1, the output signal scan1 [i] is for one period. Have four high level pulses. Here, the width of the high level pulse of the output signal scan1 [i] is equal to the Tp period, and the period of the high level pulse is equal to the period Tc1 of the clock VCLK1. Further, since the output signals out1 [i + 1] and out2 [i + 1] are shifted by one clock VCLK1 with respect to the output signals out1 [i] and out2 [i], the XOR gate XOR output signals (scan1 [i + 1] of the _{i + 1))} are with the signal shifted by one clock (VCLK1) to the output signals (scan1 [i]) of the XOR gate (XOR _i), 4 of the high level pulse Three of them coincide with the high level pulse of the output signal scan1 [i].

The shift register 330 receives the clock VCLK3 and the start signal VSP3 and shifts the output signals scan2 [1] to scan2 [m] having one high level pulse for one period by one half clock VCLK3. While outputting sequentially, the width of the high level pulse of the output signal scan2 [i] corresponds to half the period of the clock VCLK3, and the period of the clock VCLK3 is twice the period of the clock VCLK1. The start time of the high level pulse of the output signal scan2 [i] is separated by one clock VCLK1 from the start time of the last high level pulse of the output signal scan1 [i].

The NOR gates NOR _{11 to} NOR _1m are the output signals scan2 [1] to scan2 [m] of the shift register 330 and the output signals scan1 [1] to scan1 [of the XOR gates XOR _{1 to} XOR _m . m]) are respectively subjected to NOR operation to output the selection signals select [1] to select [m]. The output signal select [i] of the NOR gate NOR _1i has a low level if any one of the two output signals scan1 [i] and scan2 [i] is high level by a NOR operation. Therefore, the output signal select [i] of the NOR gate NOR _1i has four low level pulses (precharge pulses) having a width of Tp length as shown in FIG. ) Once. Here, the width and the period of the precharge pulse are equal to the width and the period of the high level pulse of the output signal scan1 [i], respectively, and the width of the selection pulse is the width of the high level pulse of the output signal scan2 [i]. Is the same as Therefore, as shown in FIGS. 4 and 7, the selection signal select [i] applied to the selection scan line X _i may be generated as the output signal select [i] of the NOR gate NOR _1i .

Next, referring to FIGS. 8 to 11, the shift registers 310, 320, and 330 capable of generating the output signals out1 [i], out2 [i], and scan2 [i] described with reference to FIGS. 6 and 7 will be described. It will be described in detail.

FIG. 8 is a schematic circuit diagram of the shift registers 310 and 320 of FIG. 6, and FIG. 9 is a schematic circuit diagram of the shift register 330 of FIG. 6. 10 is a timing diagram of an output signal of a flip-flop and an output signal of a NOR gate used in the shift register of FIG. 9. In FIG. 8 and FIG. 9, the inverted signals of the clocks VCLK1 and VCLK3 are represented as VCLK1b and VCLK3b, respectively, and VCLK3b is omitted in the signal timing diagram of FIG. 10. Since the shift registers 310 and 320 have the same output signal type, the shift registers having the same structure can be used. Hereinafter, the shift registers 310 and 320 will be described with reference to the shift register 310.

Referring to Figure 8, the shift register 310 of FIG. 6 m flip-flops (FF ₁₁ ~FF _1m) and the included, the output of each flip-flop output signal shift register 310 (FF ₁₁ ~FF _1m) Signal out1 [1] to out1 [m].

In FIG. 8, the input signal of the first flip-flop FF ₁₁ is the start signal VSP1 of FIG. 7, and the output signal out1 [i] of the i-th flip-flop FF _1i is (i + 1) th. An input signal in of the flip-flop FF _{1 (i + 1)} is obtained. Flip-flop FF _1i receives clocks VCLK1 and VCLK1b as internal clocks clk and clkb, respectively. The flip-flop FF _1i receives the input signal when the clock clk is at the low level and outputs the latched input signal at the timing of the previous clock clk, and when the clock clk is at the low level. The input signal is latched and output. Accordingly, the flip-flop FF _1i delays the input signal by a half clock clk when the clock clk is at the low level and outputs the signal for one clock clk.

As shown in FIG. 7, the output signal out1 [i] of the flip-flop FF _1i has two high level pulses for one period, and the width of the high level pulses is equal to the period of the clock VCLK1. The period is twice the period of the clock VCLK1. Therefore, the start signal VSP1, which is the input signal in of the flip-flop FF ₁₁ , has a high level pulse when the clock VCLK1 is at a low level at intervals of two clocks VCLK1 for one period, and has a total of two times. . The flip-flops FF _{11 to} FF _1m may sequentially output the output signals out1 [1] to out1 [m] having the high level pulse twice by one clock VCLK1.

In addition, in the state where the shift register 320 has the same structure as the shift register 310, the clock VCLK2 and the start signal VSP2 are precharge periods Tp with respect to the clock VCLK1 and the start signal VSP1, respectively. It may be moved by) and input to the shift register 320. Then, the output signal out2 [i] shifted by the Tp period with respect to the output signal out1 [i] as shown in FIG. 7 is sequentially output from the shift register 320.

Next, the shift register 330 of FIG. 6 will be described with reference to FIGS. 9 and 10.

Referring to FIG. 9, the shift register 330 of FIG. 6 includes (m + 1) flip-flops FF _{21 to} FF _{2 (m + 1} ) and m NOR gates (NOR _{21 to} NOR _2m ). The output signals of the NOR gates NOR _{21 to} NOR _2m become the output signals scan2 [1] to scan2 [m] of the shift register 330. The input signal of the first flip-flop FF ₂₁ is the start signal VSP3 of FIGS. 7 and 10, and the output signal SR _i of the i-th flip-flop FF _2i is the (i + 1) th flip-flop ( FF _{2 (i + 1)} ). i < th NOR gate (NOR _2i) is the i-th flip-flop output signal (SR _{i + 1} of the output signal (SR _i) and (i + 1) th flip-flop (FF _{2 (i + 1))} of (FF _3i) ) Is NOR-calculated and output as an output signal scan2 [i].

The flip-flop FF _2i outputs the input signal in as it is when the clock clk is at the high level, and latches and outputs the input signal in at the high level when the clock clk is at the low level. As shown in FIG. 10, the output signal SR _{i + 1} of the flip-flop FF _{2 (i + 1)} is half a clock VCLK3 with respect to the output signal SR _i of the flip-flop FF _2i . Since it is shifted, the clock clk should be used inverted in two adjacent flip-flops FF _2i and FF _{2 (i + 1)} . That is, the clocks VCLK3 and VCLK3b are inputted oppositely to the two flip-flops FF _2i and FF _{2 (i + 1)} .

Specifically, in FIG. 9, the flip-flop FF _2i positioned in the odd-numbered direction in the vertical direction receives the clocks VCLK3 and VCLK3b as the internal clocks clk and clkb, respectively, and the flip-flop FF _2i positioned in the even-numbered positions. ) Receives clocks VCLK3b and VCLK3 as internal clocks clk and clkb, respectively. As shown in FIG. 10, since the output signal SR ₁ of the flip-flop FF ₂₁ has a low level pulse once for one period, the start signal (which is the input signal in of the flip-flop FF ₂₁ ) VSP1 may have a low level once when the clock VCLK3 is at a high level for one period. Then, while shifted by the flip-flop _{(FF 21 ~FF 2 (m +} 1)) by a half clock is the output signal (SR ₁ ~SR _{m + 1)} having a low level pulse time 1 (VCLK3) can be outputted in sequence.

i < th NOR gate (NOR _2i) is a flip-flop _{(FF 2i, FF 2 (i} + 1)) output signal (SR _i, SR _{i + 1)} a, so NOR operation, the output signal (SR _i, SR _{i + 1} of Only when both) are low level, high level pulse is output. Since the output signal SR _{i + 1} is a signal shifted by half the clock VCLK3 with respect to the output signal SR _i , as shown in FIG. 10, the output signal scan2 [i] of the NOR gate NOR _2i . ) Has a high level pulse for a period corresponding to half clock VCLK3. The output signal scan2 [i + 1] of the NOR gate NOR _{2 (i + 1} ) is shifted by a half clock VCLK3 with respect to the output signal scan2 [i] of the NOR gate NOR _2i . It becomes

Next, an example of flip-flops used in the shift register 310 of FIG. 8 and the shift register 330 of FIG. 9 will be described with reference to FIGS. 11A and 11B.

FIG. 11A is a schematic diagram of a flip-flop used in the shift register 330 of FIG. 9, and FIG. 11B is a schematic diagram of a flip-flop used in the shift register 310 of FIG. 8.

Referring to FIG. 11A, the flip-flop FF _2i used in the shift register 330 of FIG. 9 includes a three-phase inverter 331a positioned at an input terminal, an inverter 331b forming a latch, and a three-phase inverter 331c. Include. When the clock clk is at the high level, the three-phase inverter 331a inverts and outputs the input signal in, and the inverter 331b inverts and outputs the output signal of the three-phase inverter 331a. When the clock clk becomes low, the output of the three-phase inverter 331a is cut off, the output of the inverter 331b is input to the three-phase inverter 311c, and the output of the three-phase inverter 331c is supplied to the inverter 331b. An input latch is formed. The output signal of the inverter 331b becomes the output signal out of the flip-flop FF _2i .

Accordingly, the flip-flop FF _2i may output the input signal in as it is when the clock VCLK3 is at a high level, and may latch and output the input signal in at the high level when the clock VCLK3 is at a low level.

Referring to FIG. 11B, the flip-flop FF _1k used in the shift register 310 of FIG. 8 is formed of a master / slave latch. The master and slave latches 311 and 312 of the flip-flop FF _1i may be formed in the same structure as the flip-flop of FIG. 11A, respectively. At this time, the master latch 311 uses the clocks clk and clkb in reverse with respect to the flip-flop of FIG. 11A, and the slave latch 312 uses the flip-flops and the clocks clk and clkb in FIG. 11A in the same manner.

Then, the master latch 311 outputs the input signal in when the clock clk is at the low level for one clock clk, and the slave latch 312 is the master latch when the clock clk is at the high level. The output signal of 311 is output for one clock clk. Accordingly, the flip-flop FF _1i of FIG. 11B may delay the input signal in when the clock VCLK1 is at the low level by one half clock VCLK1 and output the same for one clock VCLK1.

In the second embodiment of the present invention, the case of generating four precharge pulses has been described as an example. However, the scan driver 300 of the second embodiment may be applied to the case of generating a different number of precharge pulses. . That is, when there are 2n precharge pulses, n high level pulses are generated from the output signals out1 [i] and out2 [i] of the shift registers 310 and 320, and the period of the high level pulses is 2 of the width. Double it.

In addition to the even number of precharge pulses, the scan driver 300 according to the second embodiment may be applied to generate an odd number of precharge pulses. That is, when generating an odd number of precharge pulses, the output signal scan2 [i] of the shift register 330 overlaps with the last high level pulse of the output signal scan1 [i] of the XOR gate XOR _i . Just do it. Then, the last high level pulse of the output signal scan1 [i] and the high level pulse of the output signal scan2 [i] are NOR-operated to be output at the low level, so that one precharge pulse can be removed. Precharge pulses may be generated. The detailed operation in such a case can be easily seen from the foregoing description, so the description thereof is omitted.

In the case of generating two precharge pulses, the scan driver 300 of FIG. 6 may be implemented using the shift register of FIG. 9, which will be described in detail with reference to FIG. 12.

12 is a signal timing diagram of a scan driver in accordance with a third embodiment of the present invention.

As described above, when there are two precharge pulses, since only one high level pulse needs to be generated from the output signals out1 [i] and out2 [i] of the shift registers 310 and 320, as shown in FIG. A shift register of 9 can be applied to the shift registers 310 and 320. At this time, the clocks VCLK1 and VCLK2 input to the shift registers 310 and 320 may also have the same period as the clock VCLK3 of the shift register 330. Then, even in the shift registers 310 and 320, the high-level pulse corresponding to the half clock VCLK3 is output while being shifted by the half clock VCLK3, so that the output signals out1 [i] and out2 [i shown in FIG. ]) Can be printed. Since the structure and operation of the scan driver 300 can be easily understood from the foregoing description, a detailed description thereof will be omitted. As such, when the shift registers 310, 320, and 330 of the scan driver 300 are all used as the shift registers of FIG. 9, the structure of the scan driver 300 may be simplified, and the periods of the clocks VCLK1 and VCLK2 are also illustrated in FIG. 7. You can also reduce the frequency because it is longer than the clock.

As described above, the scan driver 300 according to the exemplary embodiment of the present invention may sequentially output a selection signal having a predetermined number of precharge pulses and one selection pulse. Here, the interval between the rising time point of two adjacent precharge pulses and the interval between the rising time point of the last precharge pulse and the selection pulse are constant, and the selection signal is shifted by the period of the precharge pulse and is sequentially output. In order to generate such a selection signal, an embodiment of the present invention has high level pulses equal to half of the number of precharge pulses (or one greater than half of the precharge pulses), and the period of the high level pulses is equal to the width. A shift register 310 for sequentially outputting a double output signal and a second shift signal 320 for sequentially outputting a second output signal shifted by a precharge period from the output signal are used. A pulse corresponding to the precharge pulse is generated in a period in which the first output signal and the second output signal have different levels.

In the embodiment of the present invention, the selection signal output from the scan driver 300 is directly applied to the selection scan line. However, the selection signal may be input through a buffer formed between the scan driver and the display area. In some cases, a level shifter may be formed between the scan driver and the display area to change the level of the selection signal and the light emission signal.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the time required for charging the data line can be reduced, data writing can be performed quickly and accurate gradation representation can be achieved.

Claims (23)

An apparatus for driving a light emitting display device including a plurality of scan lines extending in one direction and transmitting a selection signal. The selection signal has a first pulse of a first integer number of first levels and a second pulse of the first level, A first driver for outputting a first signal having at least one third pulse of a second level; A second driver configured to output a second signal having a fourth pulse shifted by the at least one third pulse by a first period; A third driver for outputting a third signal having a fifth pulse having a third level in a period in which a signal level of the first signal and the second signal is different; and And a fourth driver configured to generate the first pulse in response to the fifth pulse of the third signal. The method of claim 1, And a first period is substantially equal to the width of the first pulse. The method of claim 2, And a plurality of third pulses having a fourth level between two adjacent third pulses substantially equal to a width of the third pulse. The method of claim 3, And the first period is shorter than the width of the third pulse. The method according to any one of claims 1 to 4, And a fifth driver configured to output a fourth signal having a sixth pulse corresponding to the second pulse. And the fourth driver outputs the selection signal in response to the fifth pulse of the third signal and the sixth pulse of the fourth signal. The method of claim 5, And a start time of the sixth pulse of the fourth signal is shifted by a second integer multiple of the width of the third pulse with respect to the start time of the fifth pulse of the third signal. The method of claim 6, And wherein the second integer is twice the first integer. The method of claim 6, And wherein the second integer is equal to a value obtained by subtracting 1 from twice the first integer. The method of claim 5, The first driver, the second driver, and the fifth driver each include a shift register, and the period of the clock used in the fifth driver corresponds to twice the period of the clock used in the first driver and the second driver. A driving device of a light emitting display device. The method of claim 5, The first driving unit, the second driving unit, and the fifth driving unit each include a shift register, and the period of the clock used in the fifth driver is the same as the period of the clock used in the first driver and the second driver. Driving device. A display area including a plurality of data lines extending in one direction and transmitting data signals, a plurality of scanning lines extending in a direction crossing the data lines, and a plurality of pixels connected to the data lines and the scanning lines, respectively; And a scan driver for sequentially applying a selection signal having at least one first pulse of a first level and a second pulse of the first level to the plurality of scan lines. The method of claim 11, The light emitting display device of which the width of the first pulse is shorter than the width of the second pulse. The method of claim 12, And a second pulse is output after the first pulse is repeated a predetermined number. The method of claim 13, The first pulse is applied to at least one second scan line different from the first scan line among the plurality of scan lines during a period during which a selection signal having the second pulse is applied to the first scan line among the plurality of scan lines. The light emitting display device to which the selection signal is applied. The method of claim 13, And a period between a start point of two adjacent first pulses is substantially equal to a period between a start point of the second pulse and a start point of the first pulse adjacent to the second pulse. The method according to any one of claims 11 to 15, The pixel, At least one first switching element transferring a data signal from the data line in response to the first level of a selection signal applied to the scan line; A capacitor charging a voltage corresponding to the transmitted data signal, A transistor for outputting a current according to the voltage charged in the capacitor, and And a light emitting element emitting light in accordance with the current from the transistor. The method of claim 16, The data signal is a signal in the form of a current, The data line during a first period in which a selection signal of the second pulse is applied to a first scan line among the plurality of scan lines and a selection signal of the first pulse is applied to at least one second scan line different from the first scan line. The first current is applied to, The data signal corresponding to the pixel connected to the first scan line is applied to the data line during a second period during which the selection signal of the second pulse is applied to the first scan line and the selection signal of the second level is applied to the second scan line. The light emitting display device is applied. The method of claim 17, And the first current is substantially equal to the product of the data signal obtained by adding 1 to the number of the second scan lines to which the selection signal of the first pulse is applied in the first period. The method of claim 17, And a current corresponding to the data signal to the pixels connected to the first scan line and the second scan line, respectively, in the first period by the first current. A method of driving a light emitting display device including a plurality of scan lines extending in one direction and transmitting a selection signal, the method comprising: Outputting a first signal having at least one first pulse of a first level, Outputting a second signal having at least one second pulse of the first level and a start time of the second pulse shifted by a predetermined period with respect to the start time of the first pulse; Outputting a third signal each having a third pulse of a third level in at least one period in which the levels of the first signal and the second signal are different; and Generating at least one fourth pulse in response to the at least one third pulse of the third signal, and outputting the selection signal having the at least one fourth pulse; Way. The method of claim 20, The selection signal further has a fifth pulse longer in width than the fourth pulse after the fourth pulse, and an interval between a start point of the fifth pulse and a start point of a fourth pulse adjacent to the fifth pulse is adjacent to the fourth pulse. A driving method of a light emitting display device, which is equal to an interval between two start points of the fourth pulse. The method of claim 20 or 21, A method of driving a light emitting display device, wherein the widths of the first pulse and the second pulse are the same and the predetermined period is shorter than the width of the first pulse. The method of claim 22, In a case where at least two first pulses exist in the first signal, a period of a fourth level between two adjacent first pulses is equal to a width of the first pulse, and the second signal in the second signal And a period in which the fourth level is equal to a width of the second pulse between two adjacent second pulses when there are at least two pulses.

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