KR100648240B1 - Method of forming self aligned contact of semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a self-aligned contact of a semiconductor device, the method comprising: forming a plurality of gate patterns on a semiconductor substrate, forming a spacer on sidewalls of the gate pattern, and forming an interlayer insulating film on the entire surface of the resultant formed spacer. Forming a self-aligned contact hole by etching a predetermined region of the interlayer insulating layer using the gate pattern and the spacer as an etch mask to expose the semiconductor substrate between the gate patterns, and exposing the self-aligned contact hole. Implanting a first impurity of a conductivity type different from the semiconductor substrate into the first semiconductor substrate as a first energy, and forming an undoped semiconductor film or a low concentration semiconductor film on the entire surface of the resultant in which the first impurity is injected; The first impurity on the entire surface of the product on which the undoped semiconductor film or the low concentration semiconductor film is formed Injecting a second impurity of the same conductivity type as a second energy lower than the first energy to increase the surface concentration of the semiconductor substrate exposed by the self-aligned contact hole, and to the entire surface of the resultant implanted with the second impurity Forming a high concentration semiconductor film having a higher impurity concentration than the film.

Description

Method for forming self-aligned contact of semiconductor device {METHOD OF FORMING SELF ALIGNED CONTACT OF SEMICONDUCTOR DEVICE}

1A to 1D are cross-sectional views sequentially illustrating a process of forming a self-aligned contact of a conventional semiconductor device;

2A through 2D are cross-sectional views sequentially illustrating a process of forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10,100: semiconductor substrate 12,120: gate pattern

14.140: spacer 15,150: source / drain

16,160: interlayer insulating film 17,170: contact hole

18,180: first energy ion implantation 20,200: second energy ion implantation

24,240: low concentration polysilicon 26,260: high concentration polysilicon

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a self-aligned contact.

The process of manufacturing a semiconductor device includes laminating a plurality of material layers, in particular a conductive layer and an insulating layer, and patterning them in a suitable form. An interlayer insulating film is always formed between two conductive layers or between a substrate and a specific conductive layer, and the two conductive layers are contacted through a predetermined region of the interlayer insulating film. This process is called a contact process, and a hole formed in an interlayer insulating film so that two conductive layers can contact each other is called a contact hole. In particular, as the integration of semiconductor devices increases, the size of MOS devices decreases. In order to improve the device's operating speed and current driving capability, the channel length is reduced to deep sub-micron, which makes the formation of contact holes in semiconductor micropatterns the alignment and resolution in the photolithography process. ) Shows its limitations. In order to overcome such a problem of forming the fine contact hole, a self-aligned contact method is widely used. In the self-aligned contact, the conductive layers stacked above and below the interlayer insulating film may be formed using the same material, but generally, material layers having different electrical characteristics are used. In addition, the contact state of the interface between the conductive layer formed through the contact hole and the semiconductor substrate becomes very important. When a conductive layer having a different electrical property and a semiconductor substrate contact each other, a potential barrier difference exists between the contact surfaces, and thus contact resistance increases at the interface than when the same material is used.

1A through 1D are cross-sectional views sequentially illustrating a process of forming a self-aligned contact of a conventional semiconductor device.

Referring to FIGS. 1A and 1B, the gate insulating layer 12a, the polysilicon 12b, the metal silicide 12c, and the capping layer 12d are sequentially stacked on the semiconductor substrate 10, and then etched to form the gate pattern 12. ). The gate insulating film 12a is preferably formed of a thermal oxide film. In addition, the metal silicide film 12c is preferably formed of a heat resistant metal silicide film such as a tungsten silicide film, and the capping film 12d is preferably formed of a silicon nitride film having a high etching selectivity with respect to the silicon oxide film. Impurities are implanted into the semiconductor substrate 10 on which the gate pattern 12 is formed to form the source / drain 15 on the semiconductor substrates on both sides of the gate pattern 12. An insulating film is conformally deposited on the entire surface of the resultant product in which the gate pattern 12 and the source / drain 15 are formed, and a spacer 14 is formed on the sidewall of the gate pattern 12 through an etch back process. After the etch back process, the interlayer insulating layer 16 is formed on the entire surface of the resultant in which the spacers 14 are formed on the sidewalls of the gate pattern 12. The interlayer insulating film is patterned to form contact holes 17 exposing the source / drain 15. In order to prevent a leakage current occurring at the junction between the semiconductor substrate 10 and the source / drain, the first impurity may be deeply injected into the source / drain 15. Ion implantation 18 is performed. In addition, in order to improve the contact resistance caused by the potential barrier difference between the polysilicon, which is a conductive film formed in the contact hole 17 and the semiconductor substrate, in the subsequent process, the second impurity is lower than the first energy so as to be shallowly implanted. Ion implantation (20) with 2 energy.

Referring to FIG. 1C, after the second energy ion implantation 20, a high concentration polysilicon (hereinafter, upper polysilicon) 26 is formed on the entire surface of the resultant including the contact hole 17. However, in a subsequent thermal process, impurities in the upper polysilicon layer 26, that is, phosphorus components, diffuse into the semiconductor substrate. In this case, the effective channel length of the transistor is shortened, thereby lowering a threshold voltage, thereby making the refresh refresh characteristic of the transistor vulnerable. Therefore, in order to improve this, before forming the upper polysilicon 26 as shown in FIG. 1D, the concentration is lower than the upper polysilicon or undoped polysilicon (hereinafter lower polysilicon: 24) thin and conformal (conformal) After the formation, the method of forming the upper polysilicon 26 on the entire surface of the resultant including the lower polysilicon 24 is widely used.

However, if a low concentration or undoped lower polysilicon 24 is formed prior to forming the upper polysilicon, a potential barrier at the interface between the lower polysilicon 24 and the semiconductor substrate 10 is formed. Since the contact resistance is increased by), there is a problem that causes the device to fail.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method for forming a self-aligned contact of a semiconductor device which improves the contact resistance between the conductive film and the semiconductor substrate without making the refresh characteristics weak. .

Self-aligned contact forming method of the semiconductor device of the present invention for achieving the above object, the step of forming a plurality of gate patterns on the semiconductor substrate, forming a spacer on the sidewall of the gate pattern, the spacer is formed Forming an interlayer insulating film on the entire surface of the resultant, forming a self-aligning contact hole exposing a semiconductor substrate between the gate patterns by etching a predetermined region of the interlayer insulating film using the gate pattern and the spacer as an etching mask, and Injecting a first impurity of a conductivity type different from that of the semiconductor substrate with first energy into the semiconductor substrate exposed by the alignment contact hole, and forming an undoped semiconductor film or a low concentration semiconductor film on the entire surface of the resultant implanted first impurity. Forming a foam, and forming an undoped semiconductor film or a low concentration semiconductor film over the entire surface of the resultant product. Injecting a second impurity of the same conductivity type as the first impurity with a second energy lower than the first energy to increase the surface concentration of the semiconductor substrate exposed by the self-aligned contact hole and the entire surface of the resultant implanted with the second impurity Forming a high concentration semiconductor film having a higher impurity concentration than the low concentration semiconductor film.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2D.

2A through 2D are cross-sectional views sequentially illustrating a method of forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, the gate insulating layer 120a, the polysilicon 120b, the metal silicide 120c, and the capping layer 120d are sequentially stacked on the semiconductor substrate 100, and the gate pattern 120 is formed by photo etching. do. The gate insulating film 120a is preferably formed of a thermal oxide film. In addition, the metal silicide layer 120c may be formed of a heat resistant metal silicide layer such as a tungsten silicide layer, and the capping layer 120d may be formed of a silicon nitride layer having a high etching selectivity with respect to the silicon oxide layer. At this time, the thickness of the gate insulating film 120a is 65 kPa to 75 kPa, the thickness of the polysilicon 120b is 1000 kPa, the thickness of the metal silicide film 120c is 1500 kPa, and the capping film 120d is 1500 kPa to 2500 kPa, respectively. Deposit. An impurity is implanted into the semiconductor substrate 100 using the gate pattern 120 as an ion implantation mask to form a source / drain 150 on semiconductor substrates adjacent to the gate pattern 120. In addition, an insulating film is conformally deposited on the entire surface of the resultant material on which the gate pattern 120 and the source / drain 150 are formed, and a spacer 140 is formed on sidewalls of the gate pattern 120 through an etch back process. do. In addition, an interlayer insulating layer 160 is formed on the entire surface of the product on which the spacers 140 are formed. The interlayer insulating film is preferably formed of an oxide film such as boro phospho silicate glass (BPSG). A photoresist layer (not shown) is coated on the entire surface of the resultant layer on which the interlayer insulating layer 160 is formed, and is exposed and developed to form a pattern. The self-aligned contact hole 170 exposing the source / drain 150 is formed by dry etching using the patterned photoresist layer, the capping layer 120d and the spacer 140 as a mask. In order to prevent a leakage current at a junction between the source / drain 150 and the semiconductor substrate 100, a first impurity is deposited on the semiconductor substrate exposed by the contact hole 170. Ion implantation 180 is performed with the first energy to be implanted deeply. In the impurity ion implantation, the dopant is preferably the same dopant as the impurity formed in the source / drain 150 region, for example, phosphorus ion, and the ion implantation energy is 50 KeV to 80 KeV.

Referring to FIG. 2B, a low concentration or undoped polysilicon 240 is conformally deposited on the entire surface of the first implanted resultant impurity. The low concentration or undoped polysilicon 240 has a phosphorus component in the high concentration polysilicon, which is a conductive film formed in a subsequent process, diffused into the semiconductor substrate 100 to extend the effective channel length of the transistor. It serves to prevent the degradation of the threshold voltage characteristic by shortening. At this time, the thickness of the low concentration or undoped polysilicon is 100 kPa to 500 kPa.

Referring to FIG. 2C, a surface of the source / drain 150 may be implanted into a second impurity at a second energy lower than the first energy in a resultant product in which the low concentration or undoped polysilicon 240 is formed. Increase the concentration The second energy ion implantation 200 is contact resistance due to a potential barrier between two layers at an interface between the low concentration or the undoped polysilicon 240 and the source / drain 150. The purpose is to prevent the device (fail) due to the increase of. In the implantation of the second impurity ion, a dopant is preferably phosphorus or arsenic (As) having a lower diffusivity than the phosphorus, and the dose is 1 × 10 ¹² atoms / cm 2. -1 * 10 <^14> atoms / cm <2> and ion implantation energy are implemented with 10 KeV-30 KeV. The energy and dose of the dopant used at this time are preferably considered in consideration of the thickness of the low concentration or undoped polysilicon and the interface resistance.

Referring to FIG. 2D, a high concentration of polysilicon 260 doped with phosphorus is formed on the entire surface of the second energy ion implantation 200. Therefore, the phosphorus component in the high concentration polysilicon can be significantly suppressed from diffusing into the semiconductor substrate due to the low concentration or the undoped polysilicon film.

The present invention improves the refresh characteristics by forming a self-aligned contact hole, performing a deep impurity ion implantation process, and conducting a low impurity ion implantation process after depositing low concentration or undoped polysilicon. There is an effect of improving the contact resistance between the film and the semiconductor substrate.

Claims (3)

Forming a plurality of gate patterns on the semiconductor substrate; Forming a spacer on sidewalls of the gate pattern; Forming an interlayer insulating film on an entire surface of the resultant product on which the spacers are formed; Etching a predetermined region of the interlayer insulating layer using the gate pattern and the spacer as an etching mask to form a self-aligning contact hole exposing the semiconductor substrate between the gate patterns; Injecting a first impurity of a conductivity type different from that of the semiconductor substrate into the semiconductor substrate exposed by the self-aligned contact hole as first energy; Conformally forming an undoped polysilicon film or a low concentration polysilicon film on the entire surface of the resultant implanted with the first impurity; A second impurity of the same conductivity type as the first impurity is injected into a second energy lower than the first energy and exposed by the self-aligned contact hole on the entire surface of the undoped polysilicon film or the low-concentration polysilicon film. Increasing the surface concentration of the semiconductor substrate; And Forming a high concentration semiconductor film having a higher impurity concentration than the low concentration semiconductor film on the entire surface of the resultant implanted second impurity. The method of claim 1, And the first and second impurities are phosphorus ions and arsenic ions, respectively. The method of claim 1, And the undoped polysilicon film and the low concentration semiconductor film are formed to a thickness of 100 to 500 GPa.

Images